1.

Universal Shift Register

library ieee;
use ieee.std_logic_1164.all;

entity reg_univ is
port (
Clk: in std_logic;
Reset: in std_logic;
S: in std_logic_vector(1 downto 0);
D: in std_logic_vector(3 downto 0);
ES: in std_logic;
Q: out std_logic_vector(3 downto 0);
SS: out std_logic
);
end reg_univ;

architecture behavioral of reg_univ is

signal sQ: std_logic_vector(3 downto 0); -- Cannot read Q
begin

Q <= sQ;
SS <= sQ(0) when S="01" else
sQ(3) when S="10" else
'0';

process(Clk,Reset)
begin
if Reset='1' then
sQ <= (others=>'0');
elsif rising_edge(Clk) then
case S is
when "01" => -- Shift right
sQ <= ES&sQ(3 downto 1);
when "10" => -- Shift left
sQ <= sQ(2 downto 0)&ES;
when "11" => -- Parallel load
sQ <= D;
when others =>
end case;
end if;
end process;

end behavioral;
2. Electronic die
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dado is
port (
Clk: in std_logic;
Reset: in std_logic;
E: in std_logic;
Q: out unsigned(2 downto 0)
);
end dado;

architecture behavioral of dado is

signal count: unsigned(2 downto 0);
begin

process(Clk,Reset)
begin
if Reset='1' then
count <= to_unsigned(1,3);
Q <= to_unsigned(1,3);
elsif rising_edge(Clk) then
if E='1' then -- Count
if count=6 then
count <= to_unsigned(1,3);
else
count <= count +1;
end if;
else -- E='0'
Q <= count; -- Write count to output
end if;
end if;
end process;

end behavioral;
3. Finite State Machine
library ieee;
use ieee.std_logic_1164.all;

entity fsm is
port (
Clk: in std_logic;
Reset: in std_logic;
E: in std_logic;
S: out std_logic_vector(1 downto 0)
);
end fsm;

architecture behavioral of fsm is

type stateT is (S0,S1,S2,S3,S4,S5);
signal state,next_state: stateT;
begin

process(Clk,Reset)
begin
if Reset='1' then
state <= S0;
elsif rising_edge(Clk) then
state <= next_state;
end if;
end process;

process(state,E)
begin
case state is
when S0 =>
S <= "00";
if E='0' then
next_state <= S0;
else
next_state <= S1;
end if;
when S1 =>
S <= "00";
if E='0' then
next_state <= S4;
else
next_state <= S2;
end if;
when S2 =>
S <= "01";
if E='0' then
next_state <= S2;
else
next_state <= S3;
end if;
when S3 =>
S <= "10";
 if E='0' then
next_state <= S5;
else
next_state <= S4;
end if;
when S4 =>
S <= "11";
if E='0' then
next_state <= S5;
else
next_state <= S2;
end if;
when S5 =>
S <= "01";
if E='0' then
next_state <= S2;
else
next_state <= S1;
end if;
when others =>
S <= "00";
next_state <= S0;
end case;
end process;

end behavioral;
4. Serial adder
-- This is a very odd way to make an adder, as a FSM

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sadder is
port (
Clk: in std_logic;
A: in std_logic;
B: in std_logic;
S: out std_logic
);
end sadder;

architecture behavioral of sadder is

type stateT is (NoCarry,Carry);
signal state,next_state: stateT;
signal AB: std_logic_vector(1 downto 0);
begin

process(Clk)
begin
-- Missing Reset, not a good idea
if rising_edge(Clk) then
state <= next_state;
end if;
end process;

AB <= A & B;

process(state, A,B)
begin
case state is
when NoCarry =>
case AB is
when "01" | "10" =>
S <= '1';
next_state <= NoCarry;
when "11" =>
S <= '0';
next_state <= Carry;
when others => --"00"
S <= '0';
next_state <= NoCarry;
end case;
when Carry =>
case AB is
when "01" | "10" =>
S <= '0';
next_state <= Carry;
when "11" =>
 S <= '1';
next_state <= Carry;
when others => --"00"
S <= '1';
next_state <= NoCarry;
end case;
when others =>
S <= '0';
next_state <= NoCarry;
end case;
end process;

end behavioral;
5. Sequencer
library ieee;
use ieee.std_logic_1164.all;

entity seq_detector is
port (
Clk: in std_logic;
Reset: in std_logic;
S: in std_logic;
Z: out std_logic
);
end seq_detector;

architecture behavioral of seq_detector is

type stateT is (Init,S1,S11,S0,S00);
signal state,next_state: stateT;
begin

process(Clk,Reset)
begin
if Reset='1' then
state <= S0;
elsif rising_edge(Clk) then
state <= next_state;
end if;
end process;

process(state,S)
begin
Z <= '0'; -- Zero by default
case state is
when Init =>
if S='0' then
next_state <= S0;
else
next_state <= S1;
end if;
when S0 =>
if S='0' then
next_state <= S00;
else
next_state <= S1;
end if;
when S00 =>
if S='0' then
next_state <= S00;
Z <= '1';
else
next_state <= S1;
end if;
when S1 =>
if S='0' then
next_state <= S0;
 else
next_state <= S11;
end if;
when S11 =>
if S='0' then
next_state <= S0;
else
next_state <= S11;
Z <= '1';
end if;
end case;
end process;

end behavioral;
6. Finite State Machine
library ieee;
use ieee.std_logic_1164.all;

entity fsm is
port (
Clk: in std_logic;
Reset: in std_logic;
A,B: in std_logic;
S: out std_logic
);
end fsm;

architecture behavioral of fsm is

type stateT is (Blocked,Start1,Start2,Stop1,Stop2);
signal state,next_state: stateT;
begin

process(Clk,Reset)
begin
if Reset='1' then
state <= Blocked;
elsif rising_edge(Clk) then
state <= next_state;
end if;
end process;

process(state,A,B)
begin
if A='1' and B='1' then
next_state <= Blocked;
else
next_state <= state; -- preserve state by default
case state is
when Blocked =>
S <= '0';
if A='1' then
next_state <= Stop1;
end if;
when Stop1 =>
S <= '0';
if B='1' then
next_state <= Stop2;
end if;
when Stop2 =>
S <= '0';
if B='0' then
next_state <= Start1;
end if;
when Start1 =>
S <= '1';
if B='1' then
next_state <= Start2;
 end if;
when Start2 =>
S <= '1';
if B='0' then
next_state <= Stop1;
end if;
when others =>
S <= '0';
next_state <= Blocked;
end case;
end if;
end process;

end behavioral;
7. LIFO stack
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lifo is
port (
Clk: in std_logic;
Reset: in std_logic;
Din: in std_logic_vector(7 downto 0);
Rd: in std_logic;
Wr: in std_logic;
Dout: out std_logic_vector(7 downto 0);
Full: out std_logic;
Empty: out std_logic
);
end lifo;

architecture behavioral of lifo is

type memT is array (0 to 15) of std_logic_vector(7 downto 0);
signal ram: memT;
signal addr: unsigned(4 downto 0);
signal sEmpty, sFull: std_logic;
begin

sEmpty <= '1' when addr=0 else '0';

sFull <= '1' when addr=16 else '0';

Empty <= sEmpty;

Full <= sFull;

process(Clk)
begin
if rising_edge(Clk) then
if Wr='1' and sFull='0' then
ram(to_integer(addr(3 downto 0))) <= Din;
end if;
if Rd='1' and sEmpty='0' then
Dout <= ram(to_integer(addr(3 downto 0))-1);
end if;
end if;
end process;

process(Clk,Reset)
begin
if Reset='1' then
addr <= "00000";
elsif rising_edge(Clk) then
if Wr='1' and sFull='0' then
addr <= addr+1;
elsif Rd='1' and sEmpty='0' then
addr <= addr-1;
end if;
 end if;
end process;

end behavioral;