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DDCO Submission

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11 views8 pages

DDCO Submission

Uploaded by

asmrquotes24
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Title of Project: Design& implement a sequence generator.

Project No : 13

SI Student Name SRN : Section Group


NO Number

1 Siddhanth D J PES1UG23CS575 J 13

2 Skanda k s PES1UG23CS580 J 13

3 Suhas Devamane PES1UG23CS605 J 13

4 Vikas k s PES1UG24CS838 J 13

Provide the following information

I. Verilog Code (All the Verilog code with the testbench code)

II. Verilog Code Screenshot

III. Verilog VVP Output Screenshot

IV. GTKWave Screenshot

V. Brief theory about the title

------------------------------------------------------------------------------------------------

I. Verilog Code (All the Verilog code with the testbench code)

main.v

module invert (input wire i, output wire o);


assign o = !i;
endmodule

module mux2 (input wire i0, i1, j, output wire o);


assign o = (j==0)?i0:i1;
endmodule
module df (input wire clk, in, output wire out);
reg df_out;
always@(posedge clk) df_out <= in;
assign out = df_out;
endmodule

module dfr (input wire clk, reset, in, output wire out);
wire reset_, df_in;
invert invert_0 (reset, reset_);
and2 and2_0 (in, reset_, df_in);
df df_0 (clk, df_in, out);
endmodule

module dfrl (input wire clk, reset, load, in, output wire out);
wire _in;
mux2 mux2_0(out, in, load, _in);
dfr dfr_1(clk, reset, _in, out);
endmodule

module and2 (input wire i0, i1, output wire o);


assign o = i0 & i1;
endmodule

module and3 (input wire i0, i1, i2, output wire o);
wire t;
and2 and2_0 (i0, i1, t);
and2 and2_1 (i2, t, o);
endmodule

module xor2 (input wire i0, i1, output wire o);


assign o = i0 ^ i1;
endmodule

module even_sequence_generator(input wire clk ,reset , output wire [0:3] o);


wire [0:2] i;
wire [0:10] t;
dfrl dfrl_0(clk,reset,1'b1,i[0],o[0]);
dfrl dfrl_1(clk,reset,1'b1,i[1],o[1]);
dfrl dfrl_2(clk,reset,1'b1,i[2],o[2]);
and3 and_0(!o[0],o[1],o[2],i[0]);
xor2 xor_0(o[1],o[2],t[0]);
and2 and_1(!o[0],t[0],i[1]);
and2 and_2(!o[0],!o[2],i[2]);
assign o[3]=1'b0;
endmodule

#main_tb.v

`timescale 1 ns / 100 ps

module tb;
reg clk, reset;
wire [0:3]out;
integer i;
initial begin $dumpfile("main_tb.vcd"); $dumpvars(0,tb); end
initial begin reset = 1'b1; #10 reset = 1'b0; end
initial clk = 1'b0; always #5 clk =~ clk;
even_sequence_generator eqg0(clk, reset,out);
initial begin
#110 $finish;
end
endmodule

II. Verilog Code Screenshot


III. Verilog VVP Output Screenshot

IV. GTKWave Screenshot

V. Brief theory about the title


Overview

The Even Sequence Generator is a digital sequential circuit designed to


generate even numbers in sequence from 0 to 8 (0,2,4,6,8) using synchronous
digital logic. The circuit uses flip-flops for state storage and combinational
logic to determine state transitions.

Architecture Components

State Storage

• Three D flip-flops with reset (DFRL)


• Fourth bit hardwired to 0
• Synchronous operation with clock input

Basic Building Blocks

• AND gates (2-input and 3-input)


• XOR gates
• Inverters (NOT gates)
• Multiplexers

Circuit Operation

• State Transitions
• Occurs on rising edge of clock
• Reset initializes to state 0
• Cycles through states sequentially

Present State Next State


S0 S1

S1 S2

S2 S3

S3 S4

S4 S0

State Encodings:

State S0 S1 S2

S0 0 0 0

S1 0 0 1

S2 0 1 0

S3 0 1 1

S4 1 0 0
State Transition Table(with Encodings):

S0 S1 S2 S0’ S1’ S2’

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 0 0 0

Solving for S0’,S1’,S2’, we get:

S0’ =S0
S1S2 S1’
=S0
(S1⊕S2)S2’
= S0 S2

Circuit Diagram
State Transition Diagram :

s0 | 0
________
0000

s4 | 8 s1 | 2
________ ________
1000 0010

s3 | 6 s2 | 4
________ _________
0100
0110

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