User’s Guide

December 2004
SBAU097A
 IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright  2004, Texas Instruments Incorporated

 EVM IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:

This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.

Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.

Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.

Persons handling the product must have electronics training and observe good laboratory practice standards.

No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright  2004, Texas Instruments Incorporated

 EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM with the operating conditions specified within Table 2−1 of
this document.

Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than
37°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright  2004, Texas Instruments Incorporated

 Contents

Preface

  

About This Manual

This user’s guide provides the information needed to set up and operate the
PCM4104EVM evaluation module. For a more detailed description of the
PCM4104, please refer to the product datasheet available from the Texas In-
struments web site at http://www.ti.com. Additional support documents are
listed in the sections of this guide entitled Related Documentation from Texas
Instruments and Additional Documentation.

How to Use This Manual

Throughout this document, the acronym EVM and the phrase evaluation
module are synonymous with the PCM4104EVM.

Chapter 1 provides a product overview for the PCM4104 four-channel audio

digital-to-analog (D/A) converter. The PCM4104EVM block diagram and pri-
mary features are also discussed.

Chapter 2 provides general information regarding EVM handling and unpack-

ing, as well as absolute operating conditions for power supplies and input/out-
put connections.

Chapter 3 provides general hardware descriptions and configuration informa-

tion for the EVM. The information in this chapter is designed to guide the user
with the EVM setup.

Chapter 4 includes the EVM electrical schematic, PCB layout, and the bill of
materials.

Contents iii
Contents

Information About Cautions and Warnings

This book may contain cautions and warnings.

This is an example of a caution statement.

A caution statement describes a situation that could potentially
damage your software or equipment.

This is an example of a warning statement.

A warning statement describes a situation that could potentially
cause harm to you.

The information in a caution or a warning is provided for your protection.

Please read each caution and warning carefully.

iv
 Contents

Related Documentation From Texas Instruments

The following documents provide information regarding Texas Instrument inte-

grated circuits used in the assembly of the PCM4104EVM. These documents
are available from the TI web site. The last character of the literature number
corresponds to the document revision, which is current at the time of the writing
of this user’s guide. Newer revisions may be available from the TI web site at
http://www.ti.com or by calling the Texas Instruments Literature Response
Center at (800) 477−8924 or the Product Information Center at (972)
644−5580. When ordering, identify the document(s) by both title and literature
number.

Data Sheets: Literature Number:

NE5534A SLOS070

PCM4104 SBAS291

REG103 SBVS010

REG1117 SBVS001

SN74AHC245 SCLS230

SN74ALVC244 SCES188

SN74ALVC245 SCES271

SN74CBTLV3257 SCDS040

SN74LVC1G04 SCES214

Additional Documentation

The following documents or references provide information regarding se-

lected non-TI components used in the assembly of the PCM4104EVM. These
documents are available from the corresponding manufacturer.

Data Sheets: Manufacturer:

CS8414 Cirrus Logic, web site: http://www.cirrus.com

TORX173 Toshiba, web site: http://www.toshiba.com

Contents v
Contents

If You Need Assistance

If you have questions regarding either the use of this evaluation module or the
information contained in the accompanying documentation, please contact
the Texas Instruments Product Information Center at (972) 644−5580 or visit
the TI Semiconductor Online Technical Support pages at http://www.ti.com.

FCC Warning

This equipment is intended for use in a laboratory test environment only. It may
generate, use, or radiate radio frequency energy and has not been tested for
compliance with the limits of computing devices pursuant to sub−part J of part
15 of the FCC regulations, which are designed to provide reasonable protec-
tion against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.

Trademarks

All trademarks are the property of their respective owners.

vi
 Contents

 

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 PCM4104 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 PCM4104EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3 PCM4104EVM Description and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

2 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Unpacking the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Absolute Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

3 Hardware Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Analog Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Audio Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4 AES3 Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.5 Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5.1 Standalone Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5.2 Software Mode Configuration Using the Host Port . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.6 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

4 Schematic, PCB Layout, and Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Printed Circuit Board (PCB) Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Contents vii
Contents

 
1−1. PCM4104 Functional Block Diagram, Standalone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1−2. PCM4104 Functional Block Diagram, Software Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1−3. Simplified Functional Block Diagram for the PCM4104EVM . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
3−1. Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3−2. Audio Serial Port Interface Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3−3. Host Port Interface Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
4−1. PCM4104EVM Schematic Diagram: Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4−2. PCM4104EVM Schematic Diagram: Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4−3. Top-Side Silkscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4−4. Bottom-Side Silkscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4−5. Top Layer (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4−6. Ground Plane Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4−7. Power Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4−8. Bottom Layer (solder side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8


2−1. Absolute Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
3−1. Audio Data Source and Mode Selection Using Switch SW3 . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3−2. AES3 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3−3. Selecting the Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3−4. Standalone Configuration Using Switch SW1 (MODE = LO) . . . . . . . . . . . . . . . . . . . . . . . . 3-7
4−1. PCM4104EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

viii
 Chapter 1

  

This chapter provides a brief technical overview of the PCM4104 four-channel

audio, digital-to-analog (D/A) converter, as well as a general description and
feature list for the PCM4104EVM.

Topic Page

1.1 PCM4104 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 PCM4104EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3 PCM4104EVM Description and Block Diagram . . . . . . . . . . . . . . . . . . . 1-5

Introduction 1-1
PCM4104 Product Overview

1.1 PCM4104 Product Overview

The PCM4104 is a high-performance, four-channel D/A converter designed
for use in professional audio applications. The PCM4104 supports 16- to 24-bit
linear PCM input data and sampling frequencies up to 216kHz. The PCM4104
uses an 8x oversampling digital interpolation filter, followed by a multilevel
delta-sigma modulator and a single-pole switched capacitor output filter. This
architecture provides excellent dynamic and sonic performance, as well as a
high tolerance to clock phase jitter.
The PCM4104 incorporates a flexible audio serial port, which accepts 16- to
24-bit PCM audio data in both standard audio formats (Left Justified, Right
Justified, and Philips I2S) and time division multiplexed (TDM) formats. The
TDM formats are especially useful for interfacing to the synchronous serial
ports of digital signal processors. The TDM formats support daisy-chaining of
two PCM4104 devices on a single three-wire serial interface (for sampling
frequencies up to 108kHz), forming a high-performance 8-channel audio D/A
conversion system.
The PCM4104 offers two modes for configuration control: Software and
Standalone. Software mode makes use of a four-wire serial peripheral
interface (SPI) port to access internal control registers, allowing configuration
of the full PCM4104 feature set. Standalone mode offers a more limited subset
of the functions available in Software mode, while allowing for a simplified pin
programmed configuration mode.
Functional block diagrams, showing both Standalone and Software modes,
are shown in Figure 1−1 and Figure 1−2. The following bullets summarize the
features accessible in both Standalone and Software modes.
Standalone Mode Configuration Controls (pin-programmed)
- Sampling Mode
- Audio Data Format Selection
- TDM Sub-Frame Selection
- All-Channel Soft Mute
- Digital De-Emphasis Filters for 32kHz, 44.1kHz, and 48kHz Sampling
Frequencies
- Reset and Power Down

Software Mode Configuration Controls (register-programmed)

- Sampling Mode
- Audio Data Format Selection
- BCK and LRCK Polarity
- TDM Sub-Frame Selection (pin-programmed)
- All-Channel and Per-Channel Soft Mute (All-Channel Mute may also
be pin-programmed)
- Zero Data Mute
- Digital De-Emphasis Filters for 32kHz, 44.1kHz, and 48kHz Sampling
Frequencies
- Per-Channel Digital Output Attenuation, Providing an Integrated Vol-
ume Control Function
- Output Phase Inversion
- Reset and Power Down

1-2
 PCM4104 Product Overview

For additional information regarding the PCM4104, please refer to the product
datasheet available from the TI web site, located at www.ti.com.

Figure 1−1. PCM4104 Functional Block Diagram, Standalone Mode

VREF1+

D/A Converter VOUT1+

and
LRCK Audio Output Filter VOUT1−
BCK Serial
DATA0 Port VREF1−
DATA1 VCOM1
VREF2+

D/A Converter VOUT2+

and
RST Output Filter VOUT2−
MUTE
DEM0 Digital VREF2−
DEM1 Filtering
SUB and VREF3+
FMT0 Control Functions
FMT1
D/A Converter VOUT3+
FMT2
and
FS0
Output Filter VOUT3−
FS1
MODE VREF3−
VCOM2
VREF4+
System Clock
D/A Converter VOUT4+
SCKI and
Timing and
Output Filter VOUT4−

VREF4−

VCC1
VDD Digital Analog AGND1
DGND Power Power VCC21
AGND2

Introduction 1-3
PCM4104 Product Overview

Figure 1−2. PCM4104 Functional Block Diagram, Software Mode

VREF1+

D/A Converter VOUT1+

and
LRCK Output Filter VOUT1−
Audio
BCK Serial
DATA0 VREF1−
Port
DATA1 VCOM1
VREF2+

D/A Converter VOUT2+

and
Output Filter VOUT2−
RST
Digital VREF2−
MUTE
Filtering
SUB
Control and
CS VREF3+
and Functions
CCLK
SPI Port VOUT3+
CDIN D/A Converter
CDOUT and
MODE Output Filter VOUT3−

VREF3−
VDD
VCOM2
VREF4+
System Clock
SCKI D/A Converter VOUT4+
and
Timing and
Output Filter VOUT4−

VREF4−

VCC1
VDD Digital Analog AGND1
DGND Power Power VCC21
AGND2

1-4
 PCM4104EVM Features

1.2 PCM4104EVM Features

The PCM4104EVM provides a convenient platform for evaluating the perfor-
mance and functionality of the PCM4104 product. Key EVM features include:
- Two PCM4104 audio D/A converters, providing an eight-channel D/A con-
version system.
- Single-ended analog outputs, each with a 2nd-order analog filter and an
RCA output jack.
- A buffered audio serial port, supporting connection to DSP serial ports.

- An onboard AES3 receiver, supporting 75Ω coaxial cable input (up to

108kHz sampling rate).
- An optical receiver, supporting TOSLINKt optical input connection to the
AES3 receiver.
- A buffered host port supports connection to an external microprocessor
or DSP.
- Flexible power supply configuration using either onboard regulators or ex-
ternal supplies.

1.3 PCM4104EVM Description and Block Diagram

The block diagram for the PCM4104EVM is shown in Figure 1−3. Audio data
is input at the audio serial port, AES3 input, or the optical data input. A switch
on the EVM allows the user to select the audio clock and data source, which
is either the audio serial port or the AES3 receiver output. When using the au-
dio serial port, data for the eight audio channels can be input independently,
so that each channel can carry its own program data. When using the AES3
receiver, only two channels of data are available. The left channel data is
routed to channels 1, 3, 5, and 7, whereas the right channel data is routed to
channels 2, 4, 6, and 8.
Each PCM4104 analog output is filtered by an external 2nd-order Butterworth
low-pass active filter circuit. The active filter provides additional attenuation of
the out-of-band noise produced by the delta-sigma conversion process, while
providing band limiting suitable for high-resolution audio reproduction.
The PCM4104EVM can be configured to operate in either Standalone or Soft-
ware mode. In Standalone mode, onboard switches provide direct control of
dedicated input pins that are used to select sampling mode, audio data format,
de-emphasis filtering, and all-channel soft mute. In Software mode, the
PCM4104EVM can be controlled through the buffered host port interface,
which can be connected to a microprocessor, digital signal processor, or
another device capable of operating the PCM4104 SPI port. When the
PCM4104EVM is configured in Standalone mode, the host port interface buff-
er is disabled, with all outputs set to a high-impedance state.
Although not shown in Figure 1−3, the PCM4104EVM provides support for
various power-supply options. Power-supply configuration is discussed in
more detail in Chapter 3 of this document.

Introduction 1-5
PCM4104EVM Description and Block Diagram

Figure 1−3. Simplified Functional Block Diagram for the PCM4104EVM

Output Filter
NE5534A
Channel 1
Audio Clocks Output
Audio Tri−State and Data Output Filter
Serial HDR Buffers
NE5534A
Port and
Channel 2
Mux
PCM4104 Output
4−Channel
Output Filter
D/A Converter
NE5534A
Channel 3
Output
AES3 Input Output Filter
Accepts 75Ω NE5534A
Coaxial Cable AES3 Channel 4
with RCA Plug Receiver Output
and
Tri−State Output Filter
Buffer NE5534A
TOSLINK TOSLINK Channel 5
Optical Optical Output
Input Receiver
Output Filter
NE5534A
Channel 6
PCM4104 Output
4−Channel
Output Filter
D/A Converter
NE5534A
Host Tri−State Channel 7
HDR
Port Buffers Output
SPI Clocks
and Data Output Filter
NE5534A
Channel 8
Output

1-6
 Chapter 2

    

This chapter provides information regarding PCM4104EVM handling and

unpacking, as well as absoute maximum operating conditions.

Topic Page

2.1 Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Unpacking the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Absolute Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Getting Started 2-1

Electrostatic Discharge

2.1 Electrostatic Discharge

Electrostatic Discharge
Failure to observe proper electrostatic discharge (ESD) handling
precautions may result in damage to EVM components.

Many of the components on the PCM4104EVM are susceptible to damage by

electrostatic discharge. Customers are advised to observe proper ESD han-
dling procedure when unpacking and handling the EVM, including the use of
a grounded wrist strap at an approved ESD workstation. Failure to observe
ESD handling procedures may result in damage to EVM components.

2.2 Unpacking the EVM

Upon opening the PCM4104EVM package, please check to make sure that
the following items are included:
- One PCM4104EVM
- One printed copy of the PCM4104 datasheet
- One printed copy of the PCM4104EVM user’s guide

If any of these items are missing, please contact the Texas Instruments Prod-
uct Information Center nearest you to inquire about replacements.

2.3 Absolute Operating Conditions

Absolute Operating Conditions

Exceeding the absolute maximum operating conditions may result
in damamge to the EVM and/or the equipment connected to it.

The user should be aware of the absolute maximum operating conditions for
the PCM4104EVM. Exceeding these conditions may result in damage to the
EVM and the equipment connected to it. Table 2−1 summarizes the critical
data points.

Table 2−1. Absolute Operating Conditions

+12V +15.0VDC max
−12V −15.0VDC max
Power Supplies EXT +5VA +6.0VDC max
EXT +5VD +6.0VDC max
EXT +3.3V +3.6VDC max
VIH +3.6V max
Audio Serial Port and Host Port I/O
VIL −0.3V min
VIH +7.0V max
AES3 75Ω Coaxial Cable Input
VIL −0.5V min

2-2
 Chapter 3

          

This chapter provides the hardware description and configuration information

for the PCM4104EVM.

Topic Page

3.1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Analog Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Audio Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4 AES3 Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.5 Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.6 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Hardware Description and Configuration 3-1

Power Supplies

3.1 Power Supplies

The PCM4104EVM requires a minimum of three power supplies for operation.
For the analog section of the board, both +12V and −12V DC power supplies
are required. A +5V analog supply, along with a +5V reference supply, may be
derived from the +12V supply using onboard linear voltage regulators, or alter-
natively, may be supplied from external power supply. For the digital section
of the board, a single +5V DC power supply is required. A +3.3V digital supply
may be derived from the +5V digital supply using an onboard linear voltage
regulator, or alternatively, may be supplied from an external supply.

The analog power supplies are connected to the EVM via terminal block J9.
The digital power supplies are connected via terminal block J14. Figure 3−1
illustrates the power supply configuration options for the PCM4104EVM.

Figure 3−1. Power Supply Configuration

EXT EXT Ext
−12V +12V AGND +5VREF +5VA +5VD AGND +3.3V

J9 J14

Ext Ext
+5VA +3.3V

+5VA
JMP4 EXT
−12V +12V 1 2 +5VD +3.3V
U12 JMP5
3 4 U21 1 2
+5V 5 6
+3.3V 3 4
Regulator
Regulator

Ext +5VREF +3.3V

+5VA
JMP3
U11 1 2
+5V 3 4
Regulator

+5VA

3-2
 Analog Output Ports

3.2 Analog Output Ports

The PCM4104 includes two PCM4104 devices, providing a total of eight ana-
log output channels. Each channel includes an external active filter circuit,
which performs both low-pass filtering and differential-to-single-ended signal
conversion. The gain of the active filter stage is approximately equal to 1.6.
The −3dB corner of the filter is approximately 166kHz. The outputs of the filters
are made available at connectors J1 through J8, which correspond to chan-
nels 1 through 8, respectively. RCA jacks are used for the output connectors.

The operational amplifier IC selected for use in the active filter circuits is the
Texas Instruments NE5534A, which exhibits low input voltage noise and total
harmonic distortion. The datasheet typical dynamic performance specifica-
tions for the PCM4104 are obtainable using this device. Other bipolar input op
amps with equivalent or superior specifications should yield similar results.
Using popular FET input audio op amps, such as the TI/Burr-Brown OPA134
or OPA604, will yield dynamic range measurements that are 1dB to 2dB worse
than the datasheet typical specifications, while THD+N specifications will be
equivalent to the published typical specifications.

3.3 Audio Serial Port

The PCM4104EVM provides a buffered interface to the audio serial ports for
both PCM4104 devices. The audio serial port is comprised of headers J10 and
J11, along with buffers U13 through U15. Figure 3−2 illustrates the audio port
connections and definitions.

Figure 3−2. Audio Serial Port Interface Pin Definitions

J10
SCKI System clock input. Clock rate = 128fS, 192fS, 256fS, 384fS, 512fS, or 768fS .
BCK Bit (or Data) clock input. Clock rate = 32fS to 256fS, depending upon data format and word length.
LRCK Left/right (or word) clock input. Clock rate = fS, the input sampling frequency.
DATA12 Audio data for channels 1 and 2 (non−TDM formats) or all 8 channels (TDM formats).
DATA34 Audio data for channels 3 and 4 (non−TDM formats).

J11
DATA56 Audio data for channels 5 and 6 (non−TDM formats).
DATA78 Audio data for channels 7 and 8 (non−TDM formats).

NOTE: Refer to the PCM4104 data sheet for additional details regarding audio serial port operation.

Hardware Description and Configuration 3-3

Audio Serial Port

The audio serial port includes the system clock (SCKI), bit clock (BCK), and
left/right word clock (LRCK) inputs, which are common to both U1 and U2.
Since these clocks are common to both PCM4104 devices, they will both oper-
ate at the same input sampling frequency.

The DATA12 input provides data for channels 1 and 2 for non-TDM data for-
mats, while data for all eight channels are provided at DATA12 for TDM data
formats. The DATA34, DATA56, and DATA78 inputs carry data for the corre-
sponding channels when using non-TDM data formats.

Switch SW3 is used to enable/disable the audio serial port buffers and to select
between TDM and non-TDM modes of operation. Table 3−1 illustrates the op-
tions for switch SW3.

Table 3−1. Audio Data Source and Mode Selection Using Switch SW3

ASP Audio Data Source

LO Audio Serial Port (headers J10 and J11)
HI AES3 Receiver (input via connector J13 or TOSLINK)

TDM Audio Serial Port Mode

LO Non-TDM (left-justified, right-justified, I2S data formats)
HI TDM (TDM data formats only)

Audio data format selection for Standalone mode is detailed in section 3.5.1
of this chapter. In Software mode, audio data formats are selected using a con-
trol register, programmed through the host port interface. Refer to the
PCM4104 datasheet for control register definitions.

The audio serial port signals are compatible with +3.3V logic input/output lev-
els. The port buffers (U13 and U14) are not +5V tolerant.

3-4
 AES3 Input Ports

3.4 AES3 Input Ports

The PCM4104 includes an AES3 receiver IC (U19), which provides audio data
and clock recovery for AES3 formatted input data streams. Both professional-
and consumer-formatted AES3 data streams are supported. The coaxial cable
input at RCA jack input J13 accepts 75Ω connections, and is suitable for con-
necting to audio test equipment and consumer S/PDIF data sources, such as
CD or DVD players. The Toshiba TOSLINK optical receiver provides an inter-
face to consumer audio players that have only optical digital outputs. Jumpers
JMP1 and JMP2 are used to select between coaxial cable and optical inputs.
Table 3−2 illustrates the jumper options.

Table 3−2. AES3 Input Selection

JMP1 JMP2 AES3 Input Source

Shorted Open 75Ω Coaxial Cable Input (J13)
Open Shorted TOSLINK Optical Input

When selected as the audio data source (see Table 3−1), the AES3 receiver
will provide the system clock (SCKI), bit clock (BCK), left/right word clock
(LRCK), and I2S formatted stereo audio data required by the D/A converters.
Sampling rates up to and including 108kHz are supported. The AES3 receiver
provides a 256fS system clock output rate, along with a 64fS bit clock output
rate. The appropriate sampling mode and audio data format pins or bits must
be set for the PCM4104. For sampling mode, select either Single Rate or Dual
Rate, depending upon the sampling frequency. For data format, select the
24-Bit I2S.

When using the AES3 receiver as the data source, only linear PCM stereo au-
dio data is acceptable for use with the PCM4104. Encoded or compressed au-
dio data is not acceptable, as the PCM4104 has no decoding capabilities. The
recovered left-channel data is routed to channels 1, 3, 5, and 7, while the re-
covered right-channel data is routed to channels 2, 4, 6, and 8. The AES3 data
source is useful for testing purposes, as well as stereo playback when per-
forming listening tests.

Hardware Description and Configuration 3-5

Configuration Modes

3.5 Configuration Modes

The PCM4104EVM may be configured for either Standalone or Software con-
trol modes. The MODE element of switch SW1 is used to set the control mode.
Table 3−3 shows the MODE switch options.

Table 3−3. Selecting the Configuration Mode

MODE Configuration Mode

LO Standalone (switch SW1 used for all settings)
HI Software (external control via the host port interface)

In Standalone mode, switch SW1 is used to configure the sampling mode, au-
dio data format, digital de-emphasis filter, and all-channel soft mute functions.
Standalone mode configuration is discussed in more detail in section 3.5.1 of
this chapter.

In Software mode, the PCM4104 is configured by writing control registers

through the PCM4104 serial peripheral interface (SPI) port. The SPI port is ac-
cessed using the buffered host port interface at header J12. The host port in-
terface is discussed in more detail in section 3.5.2 of this chapter.

3-6
 Standalone Mode Configuration

3.5.1 Standalone Mode Configuration

As mentioned in the previous section of this chapter, Standalone mode allows
both PCM4104 devices to be configured using switch SW1. Standalone mode
provides access to a subset of the PCM4104 feature set, while providing a sim-
plified configuration mode requiring no external host. Table 3−4 summarizes
the options available in Standalone mode using switch SW1. Refer to the
PCM4104 datasheet for additional information regarding the functions listed
in Table 3−4.

Table 3−4. Standalone Configuration Using Switch SW1 (MODE = LO)

MUTE All-Channel Soft Mute
LO Disabled, Outputs are On
HI Enabled, Outputs are Muted

DEM1 DEM0 Digital De-Emphasis Filter

LO LO Disabled
LO HI Enabled for fS = 48kHz
HI LO Enabled for fS = 44.1kHz
HI HI Enabled for fS = 32kHz

FMT2 FMT1 FMT0 Audio Data Format

LO LO LO 24-Bit Left Justified
LO LO HI 24-Bit I2S
LO HI LO TDM with No BCK Delay
LO HI HI TDM with One BCK Delay
HI LO LO 24-Bit Right Justified
HI LO HI 20-Bit Right Justified
HI HI LO 18-Bit Right Justified
HI HI HI 16-Bit Right Justified

FS1 FS0 Sampling Mode

LO LO Single Rate
LO HI Dual Rate
HI LO Quad Rate
HI HI − Not Used −

Hardware Description and Configuration 3-7

Software Mode Configuration Using the Host Port

3.5.2 Software Mode Configuration Using the Host Port

The PCM4104 includes a buffered host port for interfacing to an external
microprocessor, DSP, or other devices that can support synchronous serial
port operation for communications with the PCM4104 serial peripheral
interface (SPI) port. Figure 3−3 illustrates the port connections and definitions.

Figure 3−3. Host Port Interface Pin Definitions

J12
RESET Active low reset and power down input for both PCM4104 devices (U1 and U2).
CS1 Active low chip select input for U1.
CS2 Active low chip select input for U2.
CCLK SPI data clock input shared by both PCM4104 devices (U1 and U2).
CDIN SPI data input shared by both PCM4104 devices (U1 and U2).
CDOUT1 SPI data output for U1.
CDOUT2 SPI data output for U2.

NOTE: Refer to the PCM4104 data sheet for additional details regarding SPI port operation.

The port signals are compatible with +3.3V logic input/output levels. The port
buffer (U16) is not +5V tolerant.

The host port interface connections include a common bit clock (CCLK), serial
data input (CDIN), and reset (RST), used by both PCM4104 devices. Separate
chip selects (CS1 and CS2) are provided to allow individual write or read
access to U1 or U2. In addition, separate serial data outputs (CDOUT1 and
CDOUT2) are provided to support individual read access for both devices.

3.6 Reset Function

The PCM4104 includes an onboard reset switch, SW2, which is a normally
open, momentary-contact pushbutton switch. The RST inputs for both U1 and
U2 are normally pulled up to the +3.3V supply by a 10kΩ resistor (R65). De-
pressing switch SW2 forces the reset signal to a low logic level and releasing
switch SW2 initiates a reset sequence.

The node controlled by switch SW2 is also connected to the RESET pin on
host port header J12. When not using the host port, the RESET pin of header
J12 should be left floating. The pull-up resistor ensures that the reset signal
to the D/A converters is normally pulled to a high logic level.

3-8
 Chapter 4

   ! "#   !  $  

This chapter provides the electrical schematic and physical layout information
for the PCM4104EVM. The bill of materials is included for component and
manufacturer reference.

Topic Page

4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 Printed Circuit Board (PCB) Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Schematic, PCB Layout, and Bill of Materials 4-1

Schematic

4.1 Schematic
The electrical schematic for the PCM4104EVM is shown in Figure 4−1 and
Figure 4−2. The analog section is shown in Figure 4−1 and the digital section
shown in Figure 4−2. Descriptions of the components shown on the schemat-
ics are listed in Table 4−1.

4-2
 NOTE: Resistors R49 to R56 are not populated.
R1 1K
R9 1K
C69 560pF
+3.3V
C77 560pF
+12V C52
RN2 4.7uF +12V C60
RN1
10K 4.7uF
10K C11
C85 C19

7
1
8
R17 R33 0.1uF C93
J1

7
1
8
U3 R25 R41 0.1uF
TP1 604 499 2 CH. 1 OUTPUT J2
R49 R57
MODE 100uF 6 604 499 2 U4 CH. 2 OUTPUT
2K C101 C109 2200pF
U1 C86 3 NE5534AP 100uF 6 R61
22pF 100 C113 2200pF
SW1 DACRST 9 2 R18 R34 C94 3 NE5534AP
RST VOUT1− 100
C12 0.1uF R26 R42

4
1 20 MODE 8 1 604 499 C105
MODE VOUT1+ C20 0.1uF
R2

4
2 19 MUTE 10 C3 100uF 604 499
MUTE 1K
3 18 DEM0 12 48 C70 C53 4.7uF 100uF R10
DEM0 VCOM1 22pF 1K
4 17 DEM1 11 560pF R53 C78 C61 4.7uF
DEM1 0.1uF
5 16 FMT0 25 46 −12V 560pF
FMT0 VOUT2− 2K
6 15 FMT1 26 47 −12V
FMT1 VOUT2+
7 14 FMT2 27
FMT2 R11 1K
8 13 FS0 28 39
FS0 VOUT3−
9 12 FS1 29 38
FS1 VOUT3+ C79 560pF
10 11 13 C4 R5 1K
SUB
37
VCOM2
DIPSWITCH−10 560pF +12V C62
SCKI 0.1uF C73
14 35 4.7uF
SCKI VOUT4−
15 36
BCK BCK VOUT4+ +12V C54
16 +5VREF C21
LRCK 4.7uF
17 5 C95
LRCK DATA0 VREF1+
7
1
8

R27 R43 0.1uF

18 4 C117 0.01uF C13 J4
DATA1 VREF1−
604 499 2 U6 CH. 4 OUTPUT
D12 C87 R62
44 100uF 6

7
1
8
R19 R37 0.1uF 2200pF
VREF2+ J3 C114
43 C118 0.01uF C96 3 NE5534AP 100
D34 VREF2− 604 499 2 U5 CH. 3 OUTPUT R28 R44
R50 R58
2K 100uF 6 C107 C22 0.1uF
2200pF
4

RN3 47 CS1 21 41 C102 C110 604 499

CS1 CS VREF3+ C88 3 NE5534AP 100
CCLK 22 42 22pF R20 R38 100uF R12
CCLK VREF3− 1K
CDIN 23 0.1uF 22pF C80 C63 4.7uF
C14

4
CDIN 604 499 R55
CDOUT1 24 32 560pF
CDOUT1 CDOUT VREF4+ 100uF R6
33 C119 0.01uF 2K −12V
VREF4− 1K C74 C55 4.7uF
+3.3V
+5VA 560pF
19 45
VDD VCC1 −12V R13 1K
C1 C46
0.1uF 4.7uF C48
C5
0.1uF C81 560pF
20 3 4.7uF
DGND AGND1

6 40 R3 1K +12V C64
N/C VCC2
7 4.7uF
N/C C49
30 C6 C71 560pF
N/C C23
31 34 4.7uF 0.1uF
N/C AGND2
C97
+12V C56
7
1
8

R29 R45 0.1uF

PCM4104PFB J6
4.7uF
604 499 2 U8 CH. 6 OUTPUT
100uF 6 R63
C15 C115 2200pF
C98 3 NE5534AP 100
U2 C89 R30 R46

7
1
8
R21 R35 0.1uF C106
DACRST 9 2 J5 C24 0.1uF
4

DACRST RST VOUT1− 604 499

MODE 8 1 604 499 2 U7 CH. 5 OUTPUT
MODE VOUT1+ R51 R59 100uF R14
MUTE 10 C7 2K 100uF 6 22pF 1K
MUTE C103 C111 2200pF C82 C65 4.7uF
DEM0 12 48 C90 3 NE5534AP 100 R54
DEM0 VCOM1 22pF R22 R36 560pF
DEM1 11
DEM1 0.1uF 0.1uF 2K −12V
C16

4
FMT0 25 46 604 499
FMT0 VOUT2−
FMT1 26 47 100uF R4 R15 1K
FMT1 VOUT2+ 1K
FMT2 27 C72 C57 4.7uF
FMT2
FS0 28 39 560pF 560pF
FS0 VOUT3− C83
FS1 29 38 −12V
Figure 4−1. PCM4104EVM Schematic Diagram: Analog Section

FS1 VOUT3+
13 C8
SUB +12V C66
37
VCOM2 4.7uF
RN4 +3.3V
0.1uF
14 35 C25
SCKI VOUT4− R7 1K
15 36
BCK VOUT4+ C99
16 +5VREF
7
1
8

R31 R47 0.1uF

LRCK C75 560pF J8
17 5
D56 DATA0 VREF1+ 604 499 2 U10 CH. 8 OUTPUT
18 4 C120 0.01uF R64
DATA1 VREF1− 100uF 6
+12V C58 C116 2200pF
D78 C100 3 NE5534AP 100
44 4.7uF R32 R48
VREF2+
43 C121 0.01uF C26 0.1uF
4

CS2 VREF2− C17 C108 604 499

100uF R16
47 CS2 21 41 C91
CCLK CS VREF3+ 1K C84 C67 4.7uF
7
1
8

R23 R39 0.1uF

CCLK 22 42 J7 22pF
CCLK VREF3− 560pF
CDIN 23 604 499 2 U9 CH. 7 OUTPUT R56
CDIN CDIN R52 R60 −12V
CDOUT2 24 32 2K 100uF 6
CDOUT VREF4+ C104 C112 2200pF 2K
33 C122 0.01uF C92 3 NE5534AP 100
CDOUT2 VREF4− 22pF R24 R40
+3.3V +5VA
C18 0.1uF
4

19 45 604 499
VDD VCC1

Schematic, PCB Layout, and Bill of Materials

C2 C47 C9 100uF R8
0.1uF 4.7uF C50 1K C59
C76 4.7uF
20 3 4.7uF 0.1uF 560pF
DGND AGND1
−12V
6 40
N/C VCC2
7
N/C C51
30 C10
N/C
31 34 4.7uF 0.1uF
N/C AGND2

PCM4104PFB
Schematic

4-3
4-4
+3.3V C31

AUDIO SERIAL PORT

U13 0.1uF
HEADER 1 1 20
DIR VCC
J10 RN5
Schematic

SCKI 2 18
1 2 A1 B1
BCK 3 17
3 4 A2 B2
LRCK 4 16
5 6 A3 B3
DATA12 5 15
7 8 A4 B4
DATA34 6 14
9 10 A5 B5
DATA56 7 13
A6 B6
DATA78 8 12 LED1
A7 B7 +5VD
9 11 LOCK
J11 A8 B8 U19
10 R68
47 GND 28 1
1 2 19 VERF C J13
OE 470 27 2
3 4 CE/F2 CD/F1 JMP1 S/PDIF COAX INPUT
26 3
5 6 SN74ALVC245PW SDATA CC/F0 1 2
25 4 +5VD
7 8 ERF CB/E2
+3.3V C32 24 5 COAX
9 10 M1 CA/E1
+5VD 23 6 C68 R70
M0 C0/E0 75
HEADER 2 22 7 4.7uF C42
0.1uF VCC VDD
C134 21 8 0.1uF
AGND DGND

20
U14A C33 +3.3V C39 4.7uF
1 0.1uF
G SN74ALVC244PW
0.1uF JMP2

VCC
C126
2 18 R69 20 9 1 2

16
A1 Y1 U15 FILT RXP
+3.3V 4 16 470 19 10
A2 Y2 2 MCK RXN 0.01uF OPTICAL
6 14 1B1 18 11
A3 Y3 3 4 C135 M2 FSYNC

VCC
8 12 1B2 1A 17 12
0.068uF

GND
A4 Y4 M3 SCK
16 13
5 SEL CS12/FCK C127
0.1uF 2B1 15 14 TOSLINK

10
6 7 CBL U 0.01uF
5
6

5
U17 C27 2B2 2A TORX173
2 4
MODE CS8414−CS
11

3
SN74LVC1G04DBV 3B1 1
10 9 OUTPUT
3B2 3A
+3.3V
14
4B1
13 12
4B2 4A
VCC
GND1
GND2

+3.3V C43
R65
10K 1
3
2
4

S +5VD
15 C44

GND
OE 0.1uF L1
SW2 C123 U20

8
SN74CBTLV3257PW 1 20 47uH 0.1uF
DIR VCC BCK
DAC RESET +3.3V C34
0.01uF
2 18
A1 B1 SCKI
3 17
0.1uF A2 B2
4 16
DACRST

20
A3 B3 LRCK
U16A 5 15
A4 B4 D12
J12 1 6 14
G A5 B5
RESET RN6 7 13

VCC
1 2 CS1 A6 B6 D34
CS1 2 18 8 12
3 4 A1 Y1 A7 B7
CS2 4 16 9 11
5 6 A2 Y2 CS2 +3.3V A8 B8 D56
CCLK 6 14 10
7 8 A3 Y3 GND
CDIN 8 12 19

GND
9 10 A4 Y4 CCLK OE
CDOUT1 D78
11 12 RN7
CDOUT2 SN74AHC245PW

10
13 14 CDIN 10K +3.3V
SN74ALVC244PW
C40
HOST PORT

47 0.1uF
U18
SW3

5
1 4 ASP 2 4
U16B
2 3 TDM
19 3
G
DIPSWITCH−2 SN74LVC1G04DBV
9 11
Y1 A1 CDOUT1
7 13
Y2 A2
5 15
Y3 A3 CDOUT2
3 17
Y4 A4
SN74ALVC244PW +3.3V
Figure 4−2. PCM4104EVM Schematic Diagram: Digital Section

U14B
19
+12V C36 EXT +5VA G
J9 EXT EXT
11 9
−12V +12V AGND AGND +5VREF +5VA JMP3 +5VA J14 EXT A1 Y1
0.1uF 13 7
EXT +5VD DGND +3.3V A2 Y2
15 5
U11 1 2 EXT +5VREF +5VREF A3 Y3
17 3
1 2 3 4 A4 Y4

6
5
4
3
2
1
R66 VIN VOUT
5 JMP4
REG SN74ALVC244PW
3
2
1

ANALOG POWER ENABLE

200K 3 1 2 EXT
GND C37 DIGITAL POWER
TAB 4 3 4 +5VA
GND NR/ADJUST 0.1uF
5 6 REG C41 C45
REG103GA
C28 C29 C30 C35 +12V C124
C38 0.1uF 0.1uF
0.01uF
C132 C133
0.1uF 0.1uF 0.1uF 0.1uF
0.1uF
C128 C129 C130 C131 U12
1 2 100uF 100uF
R67 VIN VOUT
5
ENABLE JMP5 +3.3V
100uF 100uF 100uF 100uF 200K 3 +5VD
GND +5VD U21 EXT
TAB 4
GND NR/ADJUST REG1117−3.3 1 2
REG103GA 3 2 3 4
−12V +12V C125 VIN VOUT
0.01uF REG
GND

EXT +5VREF C136

C137
4.7uF
EXT +5VA
1

4.7uF
 Printed Circuit Board (PCB) Layout

4.2 Printed Circuit Board (PCB) Layout

The PCM4104EVM is a four-layer PCB with the following layer structure:
Layer 1: Top (Component Side)
Layer 2: Ground Plane
Layer 3: Power
Layer 4: Bottom (Solder Side)

Figure 4−3 through Figure 4−8 show the top-side silk screen, along with the
top, ground plane, power, and bottom layers of the printed circuit assembly.

Figure 4−3. Top-Side Silkscreen

Schematic, PCB Layout, and Bill of Materials 4-5

Printed Circuit Board (PCB) Layout

Figure 4−4. Bottom-Side Silkscreen

Figure 4−5. Top Layer (component side)

4-6
 Printed Circuit Board (PCB) Layout

Figure 4−6. Ground Plane Layer

Figure 4−7. Power Layer

Schematic, PCB Layout, and Bill of Materials 4-7

Printed Circuit Board (PCB) Layout

Figure 4−8. Bottom Layer (solder side)

4-8
 4.3 Bill of Materials
The bill of materials, listing the components used in the assembly of the PCM4104EVM, is shown in Table 4−1.

Table 4−1. PCM4104EVM Bill of Materials

REFERENCE QTY PER
ITEM VALUE DESIGNATOR BD MFG MFG PART NUMBER DESCRIPTION
1 22pF C101−C108 8 KEMET C410C220J1G5CA7200 Capacitor, NPO/C0G ceramic, 22pF ±5%, 100V, axial lead
2 560pF C69−C84 16 Panasonic ECQ−B1H561JF Capacitor, poly film, 560pF ±5%, 50V, radial lead
3 2200pF C109−C116 8 Panasonic ECQ−B1H222JF Capacitor, poly film, 2200pF ±5%, 50V, radial lead
4 0.068µF C135 1 KEMET C0603C683K9RACTU Chip capacitor, X7R ceramic, 0.068µF ±10%, 6.3V, size = 0603
5 0.01µF C117−C127 11 KEMET C0603C103K5RACTU Chip capacitor, X7R ceramic, 0.01µF ±10%, 50V, size = 0603
6 0.1µF C1−C45 45 KEMET C0603C104K4RACTU Chip capacitor, X7R ceramic, 0.1µF ±10%, 16V, size = 0603
C46−C68, C134,
7 4.7µF 26 KEMET T494A475M016AS Chip capacitor, low ESR tantalum, 4.7µF ±20%, 16V, size = A
C136, C137
C85−C100,
8 100µF 22 Panasonic EEV−FK1C101P Capacitor, aluminum electrolytic, 100µF ±20%, 16V, surface-mount
C128−C133
9 J1−J8, J13 9 CUI Stack RCJ−041 RCA phono jack, black shell
10 J9 1 Weidmuller 9967720000 3.5mm PCB terminal block, 6 poles
11 J10, J11 2 Samtec TSW−105−07−G−D Terminal strip, 10-pin (5x2)
12 J12 1 Samtec TSW−107−07−G−D Terminal strip, 14-pin (7x2)
13 J14 1 Weidmuller 1699680000 3.5mm PCB terminal block, 3 poles
14 JMP1,JMP2 2 Samtec TSW−102−07−G−S Terminal strip, 2-pin (2x1)
15 JMP3, JMP5 2 Samtec TSW−102−07−G−D Terminal strip, 4-pin (2x2)
16 JMP4 1 Samtec TSW−103−07−G−D Terminal strip, 6-pin (3x2)
17 47µH L1 1 Panasonic ELJ−FA470KF Inductor, surface-mount 47µH ±10%, size = 1210
18 LED1 1 Lumex SML−LX1206GC−TR Green LED, SMT, size = 1206
19 75Ω R70 1 Panasonic ERJ−6ENF75R0V Resistor, thick film chip, 75Ω, 1%, 1/10W, size = 0805

Schematic, PCB Layout, and Bill of Materials

20 100Ω R57−R64 8 Vishay Dale CMF−55 1000BT−9 Resistor, metal film, axial leads, 100Ω, 0.1%, 1/4W
21 470Ω R68, R69 2 Panasonic ERJ−6GEYJ471V Resistor, thick film chip, 470Ω, 5%, 1/8W, size = 0805
22 499Ω R33−R48 16 Vishay Dale CMF−55 4990BT−9 Resistor, metal film, axial leads, 499Ω, 0.1%, 1/4W
23 604Ω R17−R32 16 Vishay Dale CMF−55 6040BT−9 Resistor, metal film, axial leads, 604Ω, 0.1%, 1/4W
Bill of Materials

4-9
 Table 4−1. PCM4104EVM Bill of Materials (continued)

4-10
REFERENCE QTY PER
ITEM VALUE DESIGNATOR BD MFG MFG PART NUMBER DESCRIPTION
24 1kΩ R1−R16 16 Vishay Dale CMF−55 1001BT−9 Resistor, metal film, axial leads, 1kΩ, 0.1%, 1/4W
Bill of Materials

25 2kΩ R49−R56 8 Vishay Dale CMF−55 2001BT−9 Resistor, metal film, axial leads, 2kΩ, 0.1%, 1/4W, not populated
26 10kΩ R65 1 Panasonic ERJ−6ENF1002V Resistor, thick film chip, 10kΩ, 1%, 1/10W, size = 0805
27 200kΩ R66, R67 2 Panasonic ERJ−6ENF2003V Resistor, thick film chip, 200kΩ, 1%, 1/10W, size = 0805
28 47Ω RN3−RN6 4 CTS 742C163470J Thick film chip resistor array, 47Ω, 16-terminal, 8 resistors, isolated
29 10kΩ RN1 1 CTS 742C163103J Thick film chip resistor array, 10kΩ, 16-terminal, 8 resistors, isolated
30 10kΩ RN2, RN7 2 CTS 742C083103J Thick film chip resistor array, 10kΩ, 8-terminal, 4 resistors, isolated
ITT Industries/
31 SW1 1 TDA10H0SK1 DIP switch, 10-element, half pitch, surface-mount, tape-sealed
C&K
32 SW2 1 OMRON B3S−1000 Momentary tact switch, surface-mount w/o ground terminal
ITT Industries/
33 SW3 1 TDA02H0SK1 DIP switch, 2-element, half-pitch, surface-mount, tape-sealed
C&K
34 TOSLINK 1 Toshiba TORX173 TOSLINK optical receiver for S/PDIF digital audio interface
35 U1, U2 2 TI PCM4104PFB Four-channel audio D/A converter
36 U3−U10 8 TI NE5534AP Low noise operational amplifier
37 U11, U12 2 TI REG103GA−5 Linear voltage regulator, +5V
38 U13 1 TI SN74ALVC245PW Octal bus transceiver
39 U14, U16 2 TI SN74ALVC244PW Octal buffer/driver
40 U15 1 TI SN74CBTLV3257PW Quad 1-of-2 FET mux/demux
41 U17, U18 2 TI SN74LVC1G04DBV Single inverter
42 U19 1 Cirrus Logic CS8414−CS 96kHz digital audio receiver
43 U20 1 TI SN74AHC245PW Octal bus transceiver, +5V tolerant inputs with +3.3V power supply
44 U21 1 TI REG1117−3.3 Linear voltage regulator, +3.3V
45 4 3M Bumpon SJ−5003 Rubber feet, adhesive-backed
46 4 Samtec SNT−100−BK−G−H Shorting blocks
47 8 MILL−MAX 111−93−308−41−001−000 8-pin DIP sockets