COUNTERS IN VERILOG

1. What is a counter ?

Counters are sequential circuits used to count events , and they are commonly used
in digital systems. Counters can be implemented in various ways in Verilog and can
be classified into different types.

Synchronous Counters :
 All flips flops are clocked simultaneously.
 Count transitions occur at the same time , making them faster.
Asynchronous Counters
 Flip flops are clocked one after another , causing a ripple effect.
 Slower than synchronous counters but easier to implement.

2. Types of counters
 Binary Counter : counts in binary numbers (e.g. 0 ,1,10,11,…)
 Up counter : counts upwards(incrementing count)
 Down Counter : counts downwards (decrementing count)
 Up/down Counter: counts both up and down , based on control input.
 Ring Counter : a type of circular shift register; only flip flop is high at any time.
 Johnson Counter: a modified ring counter ; the complemented output is fed
back to the input
 VERILOG CODES

1. Up counter Verilog code

module counter_basic(clk, rst,count); module tb;

parameter n = 4; reg clk, rst;
input clk, rst; wire [3:0] count;
output reg [n-1 :0] count;

counter_basic dut(clk,rst,count);
always@(posedge clk or posedge rst)

begin initial begin

if(rst) clk = 0;
count<=0; rst = 1;
else #5 rst =0;
count<=count+1 ; #100 $finish;
end end
endmodule

always #5 clk = ~clk;

time = 0 , count = 0000 initial begin

time = 5 , count = 0001 $monitor("time = %0d , count = %b " ,
time = 15 , count = 0010 $time,count);
time = 25 , count = 0011
time = 35 , count = 0100 end
time = 45 , count = 0101
time = 55 , count = 0110
time = 65 , count = 0111 initial begin
time = 75 , count = 1000
$dumpfile("dump.vcd");
time = 85 , count = 1001
time = 95 , count = 1010 $dumpvars(0,dut);

end

endmodule
2. Down counter
module downcounter(clk,rst,count); module tb;
parameter n = 4; reg clk, rst;
input clk , rst; 3. Up down counter wire [3:0] count;

module updown(clk,rst,up , count); module tb;

output reg [n-1 : 0] count; downcounter dut(clk,rst,count);
input clk, rst,up; reg clk , rst , up;

output reg [3:0] count; wire [3:0] count;

always @ (posedge clk or posedge rst) initial begin
begin clk = 0;
always @(posedge clk or posedge rst) updown dut(clk,rst,up,count);
if(rst) rst = 1;
begin
count <= 4'b1111; #5 rst =0;
if(rst) initial begin
else #100 $finish;
count <= 0; clk= 0;
count <= count - 1; end
else if(up) rst = 1;

count <= count + 1; up = 0;

end always #5 clk = ~clk;
else #5 rst= 0;
endmodule
count <= count-1 ;
initial begin
time = 0 , count = 1111 #50 up=1;
$monitor("time = %0d , count = %b " ,
time
end= 5 , count = 1110 $time,count);
time = 15 , count = 1101
endmodule
time = 25 , count = 1100 #100
end $finish;
time = 35 , count = 1011 end
time = 45 , count = 1010
time = 55 , count = 1001 initial begin
initial begin
time = 65 , count = 1000
time == 75
0 , ,count $dumpfile("dump.vcd");
time count== 00111
time == 85
time 5 , ,count
count==150110 $monitor("time = %0d , count = %d" ,
$dumpvars(0,dut);
time = 15 , count =
time = 95 , count = 0101 14 $time , count);
time = 25 , count = 13 end
time = 35 , count = 12
time = 45 , count = 11
end
time = 55 , count = 12 endmodule
time = 65 , count = 13
time = 75 , count = 14
always #5 clk = ~clk;
time = 85 , count = 15
time = 95 , count = 0
time = 105 , count = 1
initial begin
time = 115 , count = 2
time = 125 , count = 3 $dumpfile("dump.vcd");
time = 135 , count = 4
time = 145 , count = 5 $dumpvars(0,dut);

end

endmodule
 4. Ring counter

module ringcounter(clk,rst,count); module tb;

input clk,rst; reg clk,rst;

output reg [3:0]count; wire [3:0] count;

always@(posedge clk or posedge rst) ringcounter dut(clk,rst,count);

begin

if(rst) initial begin

count<= 4'b1000; clk=0;

else rst=1;

count <= {count[0],count[3:1]}; #5 rst = 0;

end

endmodule #40 $finish;

end

initial begin

$monitor("time=%0d , count = %b",

$time,count);

end
time=0 , count = 1000 always #5 clk = ~clk;
time=5 , count = 0100
time=15 , count = 0010
time=25 , count = 0001
initial begin
time=35 , count = 1000
$dumpfile("dump.vcd");

$dumpvars(0,dut);

end

endmodule
 5. Johnson counter

module johnsoncounter(clk,rst,count); module tb;

input clk,rst; reg clk,rst;
output reg [3:0]count; wire [3:0] count;

always@(posedge clk or posedge rst) johnsoncounter dut(clk,rst,count);

begin

if(rst) initial begin

count<= 4'b0000; clk=0;
else rst=1;
count <= {~count[0] , count[3:1]};

end #5rst=0;
endmodule

#80 $finish;

end

initial begin
time=0 , count=0000
time=5 , count=1000 $monitor("time=%0d , count=%b",
time=15 , count=1100 $time,count);
time=25 , count=1110
time=35 , count=1111 end
time=45 , count=0111
time=55 , count=0011
time=65 , count=0001 always #5 clk=~clk;
time=75 , count=0000 initial begin

$dumpfile("dump.vcd");

$dumpvars(0,dut);

end

endmodule
 6. Design a 2 bit counter which counts 0-1-2-3-2-1-0-1-2 (gradually
increment and decrement counter)

module coun(clk,up,rst,count); module tb;

input clk,rst,up; reg clk,rst,up;

output reg [1:0]count; wire [1:0]count;

always@(posedge clk or posedge rst) coun dut(clk,up,rst,count);

begin

if(rst) initial begin

count<=2'b00; clk=0;

else if(up) rst=1;

count<=count+1; up=1;

else #5rst=0;

count <=count -1 ;

end #30 up=0;

endmodule #30 up=1;

#20 $finish;

end

initial begin

time=0, count=0 $monitor("time=%0d, count=%d",

time=5, count=1 $time,count);
time=15, count=2
end
time=25, count=3
time=35, count=2 always#5 clk=~clk;
time=45, count=1
time=55, count=0
time=65, count=1 initial begin
time=75, count=2
$dumpfile("dump.vcd");

$dumpvars(0,dut);

end

endmodule
 7. Design a BCD counter

module bcd(clk,rst,count); module tb;

input clk,rst; reg clk,rst;

output reg [3:0]count; wire [3:0]count;

always@(posedge clk or posedge rst) bcd dut(clk,rst,count);

begin

if(rst) initial begin

count<=0; clk=0;

else rst=1;

count <=count+1; #5 rst=0;

end

endmodule #90 $finish;

end

initial begin
time=0,count= 0
time=5,count= 1 $monitor("time=%0d,count=%d",$time,count);
time=15,count= 2 end
time=25,count= 3
time=35,count= 4
time=45,count= 5
always #5 clk=~clk;
time=55,count= 6
time=65,count= 7 initial begin
time=75,count= 8
$dumpfile("dump.vcd");
time=85,count= 9
$dumpvars(0,dut);

end

endmodule