VLSI Design (EC 302)

Dr. Sumit Kale

Assistant Professor
Department of Electronics and Communication Engineering
DTU Delhi

VLSI Design (EC-302) 1

Course introduction

VLSI Design (EC-302) 2

UNIT TOPICS HOURS

Introduction to VLSI, Manufacturing process of CMOS integrated circuits, CMOS n-well process design rules packaging 8
integrated circuits, stick diagram, IC layout design and tools, trends in process technology,
I MOS transistor, Energy band diagram of MOS system, MOS under external bias, derivation of threshold voltage equation,
gradual channel approximation, MOS I-V characteristics, secondary effects in MOSFETS, MOSFET scaling and small
geometry effects, MOS capacitances, MOS C-V characteristics

MOS inverters: Resistive load inverter, inverter with n-type MOSFET load, CMOS inverter: Switching Threshold, Noise 8
II Margin,
Dynamic behaviour of CMOS inverter, computing capacitances, Propagation delay, Inverter Design with Delay Constraints,
Estimation of Interconnect Parasitics, Calculation of Interconnect Delay, Static and dynamic power consumption, energy,
and energy delay product calculations

Designing Combinational Logic Gates in MOS and CMOS: MOS logic circuits with depletion MOS load. 8
Static CMOS Design: Complementary CMOS, Ratioed logic, Pass transistor logic, pseudo nMOS logic, DCVSL Logic
Dynamic CMOS logic, clocked CMOS logic CMOS domino logic, NP domino logic, speed and power dissipation of Dynamic
III logic, cascading dynamic gates.
UNIT TOPICS HOURS

Designing sequential logic circuits: Timing matrices for sequential circuits, classification of memory elements, 10
static latches and registers, the bistability principle, multiplexer based latches, Master slave Edge triggered register, static SR
IV flip flops,
dynamic latches and registers, dynamic transmission gate edge triggered register, the C2MOS register, TSPC register , Pulse
registers, sense amplifier based registers, Pipelining, Latch verses Register based pipelines, NORA-CMOS. Two-phase logic
structure

V Semiconductor Memories: DRAM, SRAM , Nonvolatile memory, Flash memory, Introduction to memory peripheral circuits 8
(Added)
VLSI designing methodology –Introduction, VLSI designs flow, Computer aided design technology: Design capture and
verification tools
Design Hierarchy Concept of regularity, Modularity & Locality, VLSI design style, Design quality

Total Lecture Hours 42

Suggested Books

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What is VLSI?
• Very-large-scale integration (VLSI) is the process of creating
an integrated circuit (IC) by combining thousands of transistors into a
single chip.
• VLSI began in the 1970s when complex semiconductor and
communication technologies were being developed.
• The microprocessor is a VLSI device.
• Before the introduction of VLSI technology most ICs had a limited set
of functions they could perform.
• An electronic circuit might consist of a CPU, ROM, RAM and
other glue logic. VLSI lets IC designers add all of these into one chip.

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• Very large-scale integration (VLSI) is the process of integrating or
embedding hundreds of thousands of transistors on a single silicon
semiconductor microchip.
• VLSI technology was conceived in the late 1970s when advanced level
computer processor microchips were under development.
• VLSI is a successor to large-scale integration (LSI), medium-scale
integration (MSI) and small-scale integration (SSI) technologies.

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Integrated circuit classification
Name Signification Year Number of Number of
Transistors Logic Gates

SSI small-scale 1964 1 to 10 1 to 12

integration

MSI medium-scale 1968 10 to 500 13 to 99

integration

LSI large-scale 1971 500 to 20,000 100 to 9,999

integration

VLSI very large-scale 1980 20,000 to 10,000 to

integration 1,000,000 99,999

ULSI ultra-large-scale 1984 1,000,000 and 100,000 and

integration more more
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Why VLSI?
❑Integration improves the design

❑Lower parasitic = higher speed

❑Lower power consumption

❑Physically smaller
❑Integration reduces manufacturing cost - (almost) no manual
assembly

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VLSI advantages
❑Reduces the Size of Circuits.
❑Reduces the effective cost of the devices.
❑Increases the Operating speed of circuits
❑Requires less power than Discrete components.
❑Higher Reliability
❑Occupies a relatively smaller area.

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VLSI Applications
• VLSI is an implementation technology for electronic circuitry - analogue or
digital It is concerned with forming a pattern of interconnected switches
and gates on the surface of a crystal of semiconductor

• Microprocessors
• personal computers
• microcontrollers
• Memory - DRAM / SRAM
• Special Purpose Processors - ASICS (CD players, DSP applications)
• Optical Switches
• Has made highly sophisticated control systems mass-producable and
therefore cheap

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In today's world VLSI chips are widely used in various branches of
Engineering like:

❑ Voice and Data Communication networks

❑ Digital Signal Processing
❑ Computers
❑ Commercial Electronics
❑ Automobiles
❑ Medicine and many more.

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Top 10 VLSI Companies in India
1 | Texas Instruments
Corporate office – Dallas, United State | Establishment –1951 |
Business – Semiconductor | Website – www.ti.com |
Texas Instruments is world’s third largest semiconductor company and a chip
producer for mobile phones. The company is among the top 10 semiconductor
companies in India and its product offering includes analog electronics, calculators,
integrated circuits and radio frequency identification. It was founded in year 1951
and headquartered in Dallas, United states.
2 | Analog Device Inc.
Corporate office – Norwood, USA | Establishment – 1965 |
Business – Semiconductor | Website – www.analog.com |
Analog Device Inc is a semiconductor design and manufacturing company which is
a market leader in data conversion and signal technology. Analog device is founded
in year 1965 and its design center is located in Australia, Canada, Israel, Japan,
Scotland, Taiwan, Germany, UK, China, Scotland and India.

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3 | Cypress Semiconductor Corporation
Corporate office – San Jose, USA | Establishment – 1982 |
Business – Semiconductor | Website – www.cypress.com |
Cypress semiconductor is a semiconductor manufacturing and design
company established in year 1982. The US based company has total 14
design centers and more than 40 sales offices located all across the globe. Its
product offering includes capacitance sensing systems, Psoc, optical sensor
and wireless solution.
4 | Broadcom Corporation
Corporate office – Irvine, USA | Establishment – 1991 |
Business – Semiconductor | Website – www.broadcom.com |
Broad corporation is rated among the top 10 semiconductor manufacturers
in India; an American company which was established in 1991 by professor
and student duo Henry Samueli and Henry T Nicholas. Its product portfolio
includes Integrated circuits, cable converter boxes, wireless networks, cable
modems, professors, Bluetooth, VIOP, GPS, server farms, digital subscriber
line
.

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5 | Cisco Systems
Corporate office – San Jose, USA | Establishment – 1984 |
Business – Network Equipments | Website – www.cisco.com |
Cisco Systems is a MNC and one of the leading design and manufacturer of
networking equipment. Its major product offering includes Networking
device, Optical networking, storage area networks, wireless, VOIP, IOS and
NX OS software etc. It is headquartered in San Jose, USA and has employed
more than 75000 people all across the globe.
6 | Bit Mapper Integration Technologies Private Limited
Corporate office – Pune, Maharashtra | Establishment – 1985 |
Business – Electronic Design | Website – www.bitmapper.com |
Bit Mapper is a technology company offering electronic system design using
PCB and FPGA design. The company is offering design solution to various
sector such as defense, aerospace, telecommunication and software. It is a
leading VLSI company in India and its expertise includes PCB design, Flexible
circuits, Thermal analysis, ADC based board and many more.

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7 | Horizon Semiconductors
Corporate office – Bangalore, Karnataka | Establishment – 1815|
Business – Semiconductor | Website – www.horizonsemi.com |
Horizon Semiconductors is an integrated silicon solution provider and
its product offering includes single chip cable, Satellite set-top box, dual
channel HD channel, 2d & 3d graphics, Single chip Blu-ray, trans coder
and encoder ICs. It is one among the top semiconductor companies in
India.
8 | Einfochips limited
Corporate office – Ahmadabad, Gujarat | Establishment – 1994 |
Business – Semiconductor | Website – www.einfochips.com |
Among the top 10 VLSI companies in India, Einfochips is one of the
most trusted brands in product engineering and semiconductor service;
and serves to Aerospace & defense, energy, healthcare, retail and
software sector. It is headquartered in Ahmadabad, Gujarat.

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• 9 | Trident Tech Labs
Corporate office – New Delhi, India | Establishment – 2000 |
Business – Electronic Design | Website – www.tridenttechlabs.com |
Established in year 2000, Trident Techlabs is a knowledge based technology
organization which offers electronic design solution. The company is a
leading computer aided engineering provider and reputed name in Very
Large Scale Integration companies in India.
• 10 | HCL technologies
Corporate office – Noida, Uttar Pradesh | Establishment – 1991 |
Business – IT and Software | Website – www.hcltech.com|
HCL technologies is a software, KPO and IT service provider headquartered
in Noida, Uttar Pradesh. The company has office in 26 countries worldwide
to provide support and consultancy to industry verticals including defense
& aviation industry, energy, power, software, manufacturing,
semiconductor, retail etc. It has also well known name in VLSI companies in
India and its engineering & Research division provides support to
semiconductor industry.
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List of Experiment

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IV Characteristics of MOSFET

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VLSI Design (EC-302) 21
Manufacturing of CMOS Integrated Circuits

Cross section of an n-well CMOS process Cross section of modern dual-well CMOS process

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The Silicon Wafer
The base material for the manufacturing process comes
in the form of a single-crystalline, lightly doped wafer.
These wafers have typical diameters between 4 and 12
inches (10 and 30 cm, respectively) and a thickness of
at most 1 mm, and are obtained by cutting a single crystal ingot
into thin slices.

A starting wafer of the p--type might be doped around the

levels of 2×1021 impurities/m3.

Single-crystal ingot and sliced wafers

VLSI Design (EC-302) 23

Photolithography
In each processing step, a certain
area on the chip is masked out
using the appropriate optical
mask so that a desired processing
step can be selectively applied to
the remaining regions. The
processing step can be any of a
wide range of tasks including
oxidation, etching, metal and
polysilicon deposition, and ion
implantation. The technique to
accomplish this selective
masking, called photolithography.

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1. Oxidation layering — this optional step deposits a thin layer of SiO2 over the complete
wafer by exposing it to a mixture of high-purity oxygen and hydrogen at approximately
1000°C. The oxide is used as an insulation layer and also forms transistor gates.
2. Photoresist coating — a light-sensitive polymer is evenly applied while spinning the
wafer to a thickness of approximately 1 mm. This material is originally soluble in an
organic solvent, but has the property that the polymers cross link when exposed to
light, making the affected regions insoluble. A photoresist of this type is called
negative. A positive photoresist has the opposite properties; originally insoluble, but
soluble after exposure.
3. Stepper exposure — a glass mask (or reticle), containing the patterns that we want to
transfer to the silicon, is brought in close proximity to the wafer. The mask is
opaque in the regions that we want to process, and transparent in the others
(assuming a negative photoresist). The glass mask can be thought of as the negative of
one layer of the microcircuit. The combination of mask and wafer is now exposed to
ultra-violet light. Where the mask is transparent, the photoresist becomes insoluble.
4. Photoresist development and bake — the wafers are developed in either an acid or
base solution to remove the non-exposed areas of photoresist. Once the exposed
photoresist is removed, the wafer is “soft-baked” at a low temperature to harden the
remaining photoresist.
5. Acid Etching — material is selectively removed from areas of the wafer that are not
covered by photoresist. This is accomplished through the use of many different types
of acid, base and caustic solutions as a function of the material that is to be removed.
6.

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6. Spin, rinse, and dry — a special tool (called SRD) cleans the wafer
with deionized water and dries it with nitrogen. The microscopic scale
of modern semiconductor devices means that even the smallest
particle of dust or dirt can destroy the circuitry. To prevent this from
happening, the processing steps are performed in ultra-clean rooms
where the number of dust particles per cubic foot of air ranges
between 1 and 10.

7. Various process steps — the exposed area can now be subjected to a

wide range of process steps, such as ion implantation, plasma etching,
or metal deposition. These are the subjects of the subsequent section.

8. Photoresist removal (or ashing) — a high-temperature plasma is used

to selectively remove the remaining photoresist without damaging
device layers.

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Patterning of SiO2

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Diffusion and Ion Implantation
The creation of the source and drain regions, well and substrate contacts, the doping of the
polysilicon, and the adjustments of the device threshold are required for fabrication. There
exist two approaches for introducing these dopants—diffusion and ion implantation.

In diffusion implantation, the wafers are placed in a quartz tube embedded in a

heated furnace. A gas containing the dopant is introduced in the tube. The high
temperatures of the furnace, typically 900 to 1100 °C, cause the dopants to diffuse into the
exposed surface both vertically and horizontally.

In ion implantation, dopants are introduced as ions into the material. The ion
implantation system directs and sweeps a beam of purified ions over the semiconductor
surface. The acceleration of the ions determines how deep they will penetrate the
material, while the beam current and the exposure time determine the dosage.

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Deposition
Any CMOS process requires the repetitive deposition of layers of a material over
the complete wafer, to either act as buffers for a processing step, or as insulating or
conducting layers.

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Etching
Etching is used to selectively form patterns such as wires and contact holes.
The wet etching process was described earlier, and makes use of acid or basic solutions.
For instance, hydrofluoric acid buffered with ammonium fluoride is typically used to etch
SiO2.
In recent years, dry or plasma etching has made a lot of inroad. A wafer is placed into the
etch tool's processing chamber and given a negative electrical charge. The chamber is
heated to 100°C and brought to a vacuum level of 7.5 Pa, then filled with a positively
charged plasma (usually a mix of nitrogen, chlorine and boron trichloride). The opposing
electrical charges cause the rapidly moving plasma molecules to align themselves in a
vertical direction, forming a microscopic chemical and physical “sandblasting” action which
removes the exposed material. Plasma etching has the advantage of offering a well-defined
directionality to the etching action, creating patterns with sharp vertical contours.

VLSI Design (EC-302) 30

Planarization
To reliably deposit a layer of material onto the semiconductor surface, it is essential
that the surface is approximately flat. If no special steps were taken, this would
definitely not be the case in modern CMOS processes, where multiple patterned
metal interconnect layers are superimposed onto each other.
Chemical-mechanical planarization (CMP) step is included before the deposition of
an extra metal layer on top of the insulating SiO2 layer. This process uses a slurry
compound—a liquid carrier with a suspended abrasive component such as
aluminum oxide or silica—to microscopically plane a device layer and to reduce the
step heights.

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Process flow for the fabrication of an n-type MOSFET on p-type
silicon

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Cont..

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Cont…`

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Cont…..

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CMOS Fabrication
• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• On each step, different materials are deposited or etched
• Easiest to understand by viewing both top and cross-section of wafer
in a simplified manufacturing process

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CMOS n-well Process Inverter Cross-section
• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors

CMOS Inverter Schematic

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Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
connection (used for Schottky Diode)
• Use heavily doped well and substrate contacts / taps

A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

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Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

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Detailed Mask Views
• Six masks n well

• n-well
• Polysilicon Polysilicon

• n+ diffusion
• p+ diffusion n+ Diffusion

• Contact p+ Diffusion

• Metal Contact

Metal

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Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2

p substrate

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Oxidation
• Grow SiO2 on top of Si wafer
• 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

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Photoresist
• Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

Photoresist
SiO2

p substrate

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Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist

Photoresist
SiO2

p substrate

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Etch
• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

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Strip Photoresist
• Strip off remaining photoresist
• Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate

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n-well• n-well is formed with diffusion or ion implantation
• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si

SiO2

n well

VLSI Design (EC-302) 47

Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

n well
p substrate

VLSI Design (EC-302) 48

Polysilicon
• Deposit very thin layer of gate oxide
• < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

VLSI Design (EC-302) 49

Polysilicon Patterning
• Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

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N-diffusion
• Use oxide and masking to expose where n+ dopants should be
diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate

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N-diffusion (cont.)
• Pattern oxide and form n+ regions

n+ Diffusion

n well
p substrate

VLSI Design (EC-302) 52

N-diffusion (cont.)
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well
p substrate

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N-diffusion (cont.)
• Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

VLSI Design (EC-302) 54

P-Diffusion
• Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

VLSI Design (EC-302) 55

Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

VLSI Design (EC-302) 56

Metalization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

VLSI Design (EC-302) 57

Simplified process sequence for the fabrication of the n-well CMOS integrated
circuit with a single polysilicon layer, showing only major fabrication steps.

VLSI Design (EC-302) 58

Layout Design Rules
The physical mask layout of any circuit to be manufactured using a particular
process must conform to a set of geometric constraints or rules, which are
generally called layout design rules.

The design rules are usually described in two ways:

(i) Micron rules, in which the layout constraints such as minimum feature sizes
and minimum allowable feature separations are stated in terms of absolute
dimensions in micrometers.

(ii) Lambda rules, which specify the layout constraints in terms of a single
parameter (X) and thus allow linear, proportional scaling of all geometrical
constraints.

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Layout
• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
• Feature size f = distance between source and drain
• Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing design rules
• Express rules in terms of l = f/2
• E.g. l = 0.3 mm in 0.6 mm process

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Simplified Design Rules
• Conservative rules to get you started

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Inverter Layout
• Transistor dimensions specified as Width / Length
• Minimum size is 4l / 2l, sometimes called 1 unit
• In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long

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Stick Diagrams
VLSI design aims to translate circuit concepts onto silicon.

❑ Stick diagrams are a means of capturing topography and layer

information using simple diagrams.
❑ Stick diagrams convey layer information through color codes (or
monochrome encoding).
❑ Acts as an interface between symbolic circuit and the actual layout.

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Stick Diagram Notations

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Stick Diagram-some rules

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Stick Diagram-some rules

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Stick Diagram-some rules

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Stick Diagram-some rules

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Examples of Stick Diagrams

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Examples of Stick Diagrams

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Examples of Stick Diagrams

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Examples of Stick Diagrams

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Examples of Stick Diagrams

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Examples of Stick Diagrams

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Examples of Stick Diagrams

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IC Layout Design

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VLSI Design (EC-302) 80
Design rules

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Lambda based design rules

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Top view

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Packaging Integrated Circuit
The IC package plays a fundamental role in the operation and
performance of a component.

❑ Bringing signal and supply wires in and out of the silicon die
❑ Removes the heat generated
❑ Provides mechanical support.
❑ Protects the die against environmental conditions such as humidity.

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A good package must comply with a large variety of requirements.

Electrical requirements—
❑Pins should exhibit low capacitance (both interwire and to the substrate),
resistance, and inductance.
❑A large characteristic impedance should be tuned to optimize transmission
line behavior. Observe that intrinsic integrated-circuit impedances are high.

Mechanical and thermal properties—

❑ The heat-removal rate should be as high as possible.
❑ Mechanical reliability requires a good matching between the thermal
properties of the die and the chip carrier.
❑Long-term reliability requires a strong connection from die to package as
well as from package to board.
❑

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Low Cost—Cost is always one of the more important properties.
❑ Ceramics have a superior performance over plastic packages, they are also substantially more
expensive. Increasing the heat removal capacity of a package also tends to raise the package cost.
❑The least expensive plastic packaging can dissipate up to 1 W. Somewhat more expensive, but still
cheap, plastic packages can dissipate up to 2W. Higher dissipation requires more expensive
ceramic packaging.

Packages can be classified in many different ways —by their main material, the number of
interconnection levels, and the means used to remove heat.
1: Package materials
The most common materials used for the package body are ceramic and polymers (plastics). The
latter have the advantage of being substantially cheaper, but suffer from inferior thermal properties.
For instance, the ceramic Al2O3 (Alumina) conducts heat better than SiO2 and the Polyimide plastic,
by factors of 30 and 100 respectively.

2: Interconnect Levels
The traditional packaging approach uses a two-level interconnection strategy. The die is first
attached to an individual chip carrier or substrate. The package body contains an internal cavity
where the chip is mounted. These cavities provide ample room for many connections to the chip
leads (or pins).

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Interconnect hierarchy in traditional IC packaging.

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Interconnect Level 1 —Die-to-Package-Substrate
For a long time, wire bonding was the technique of choice to provide an electrical
connection between die and package. In this approach, the backside of the die is
attached to the substrate using glue with a good thermal conductance. Next, the
chip pads are individually connected to the lead frame with aluminum or gold
wires. The wire bonding machine use for this purpose operates much like a sewing
machine. An example of wire bonding is shown in Figure.

VLSI Design (EC-302) 100

Although the wire-bonding process is automated to a large degree,
it has some major disadvantages.
1. Wires must be attached serially, one after the other. This leads to
longer manufacturing times with increasing pin counts.
2. Larger pin counts make it substantially more challenging to find
bonding patterns that avoid shorts between the wires.
3. The exact value of the parasitics is hard to predict because of the
manufacturing approach and irregular outlay.

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Tape Automated Bonding (or TAB)
The die is attached to a metal lead frame that is printed on a polymer film (typically
polyimide) (Figure a). The connection between chip pads and polymer film wires is
made using solder bumps (Figure b). The tape can then be connected to the
package body using a number of techniques. One possible approach is to use
pressure connectors. The advantage of the TAB process is that it is highly
automated.

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Flip-chip mounting
Another approach is to flip the die upside-down and attach it directly to the
substrate using solder bumps. This technique has the advantage of a superior
electrical performance (Figure 2.13). Instead of making all the I/O connections on
the die boundary, pads can be placed at any position on the chip. This can help
address the power- and clock-distribution problems, since the interconnect
materials on the substrate (e.g., Cu or Au) are typically of a better quality than the
Al on the chip.

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Interconnect Level 2—Package Substrate to Board
When connecting the package to the PC board, through-hole mounting has been the packaging style
of choice. A PC board is manufactured by stacking layers of copper and insulating epoxy glass. In the
through-hole mounting approach, holes are drilled through the board and plated with copper. The
package pins are inserted and electrical connection is made with solder (Figure 2.14a). The favored
package in this class was the dual-in-line package or DIP (Figure 2.15a). The packaging density of the
DIP degrades rapidly when the number of pins exceeds 64. This problem can be alleviated by using
the pin-grid-array (PGA) package that has leads on the entire bottom surface instead of only on the
periphery (Figure 2.15b). PGAs can extend to large pin counts (over 400 pins are possible)

VLSI Design (EC-302) 104

VLSI Design (EC-302) 105
Thermal Considerations in Packaging
As the power consumption of integrated circuits rises, it becomes increasingly
important to efficiently remove the heat generated by the chips. A large number of
failure mechanisms in ICs are accentuated by increased temperatures. Examples
are leakage in reverse biased diodes, electromigration, and hot-electron trapping.
To prevent failure, the temperature of the die must be kept within certain ranges.
The supported temperature range for commercial devices during operation equals
0° to 70°C. Military parts are more demanding and require a temperature range
varying from –55° to 125°C.

VLSI Design (EC-302) 106

Trends in Process Technology
Modern CMOS processes pretty much track the flow described in the previous
sections although a number of the steps might be reversed, a single well approach
might be followed, a grown field oxide instead of the trench approach might be
used, or extra steps such as LDD (Lightly Doped Drain) might be introduced. Also, it
is quite common to cover the polysilicon interconnections as well as the drain and
source regions with a silicide such as TiSi2 to improve the conductivity.
Short-Term Developments
Copper and Low-k Dielectrics
Process engineers are continuously evaluating alternative options for the
traditional ‘Aluminum conductor—SiO2 insulator’ combination that has been the
norm for the last decades. In 1998, engineers at IBM introduced an approach that
finally made the use of Copper as an interconnect material in a CMOS process
viable and economical.

VLSI Design (EC-302) 107

Silicon-on-Insulator
The main difference lies in the start material: the transistors are
constructed in a very thin layer of silicon, deposited on top of a thick
layer of insulating SiO2 (Figure). The primary advantages of the SOI
process are reduced parasitics and better transistor on-off
characteristics.

Silicon-on-insulator process— schematic diagram (a) and SEM cross-section (b).

VLSI Design (EC-302) 108
In longer term
Extending the life of CMOS technology beyond the next decade, and deeply below
the 100 nm channel length region however will require re-engineering of both the
process technology and the device structure. We already are witnessing the
emergence of a wide range of new devices (such as organic transistors, molecular
switches, and quantum devices).
Three-Dimensional Integrated Circuits

VLSI Design (EC-302) 109

The Metal Oxide Semiconductor (MOS) Structure

Two-terminal MOS structure Energy band diagram of a p-type silicon substrate

VLSI Design (EC-302) 110

The Fermi potential which is a function of temperature and doping, denotes the
difference between the intrinsic Fermi level Ej, and the Fermi level EF.

For a p-type semiconductor, the Fermi potential can be approximated by

whereas for an n-type semiconductor (doped with a donor concentration ND), the
Fermi potential is given by

The energy required for an electron to move from the Fermi level into free space
is called the work function and is given by

VLSI Design (EC-302) 111

 Energy band diagram of the combined MOS system.

Energy band diagrams of the components that make up the MOS system.

VLSI Design (EC-302) 112

 The MOS System under External Bias

The cross-sectional view and the energy band diagram of the The cross-sectional view and the energy band diagram of the
MOS structure operating in accumulation region. MOS structure operating in depletion mode, under small gate
bias.

VLSI Design (EC-302) 113

The cross-sectional view and the energy band diagram of the MOS structure in
surface inversion, under larger gate bias voltage.

VLSI Design (EC-302) 114

 MOS Transistor

Circuit symbols for n-channel and p-channel

enhancement-type MOSFETs

The physical structure of an n-channel enhancement-type MOSFET

VLSI Design (EC-302) 115

Formation of a depletion region in an n-channel enhancement-
type MOSFET.

VLSI Design (EC-302) 116

 Band diagram of the MOS structure
Formation of an inversion layer (channel) in an n-channel underneath the gate, at surface inversion.
enhancement-type MOSFET. Notice the band bending by at the surface.

The value of the gate-to-source voltage VGS needed to cause surface inversion (to create the conducting channel) is
called the threshold voltage VT0.
VLSI Design (EC-302) 117
The Threshold Voltage
Four physical components of the threshold voltage:
(i) the work function difference between the gate and the channel
(ii) the gate voltage component to change the surface potential
(iii) the gate voltage component to offset the depletion region charge
(iv) the voltage component to offset the fixed charges in the gate oxide
and in the silicon-oxide interface.

VLSI Design (EC-302) 118

The work function difference between the gate and the channel reflects the
built-in potential of the MOS system, which consists of the p-type substrate, the
thin silicon dioxide layer, and the gate electrode. Depending on the gate material,
the work function difference is

This first component of the threshold voltage accounts for part of the voltage drop
across the MOS system that is built-in. Now, the externally applied gate voltage
must be changed to achieve surface inversion, i.e., to change the surface potential
by . . This will be the second component of the threshold voltage.

VLSI Design (EC-302) 119

Another component of the applied gate voltage is necessary to offset the depletion
region charge, which is due to the fixed acceptor ions located in the depletion
region near the surface. We can calculate the depletion region charge density at
surface inversion

if the substrate (body) is biased at a different voltage level than the source, which is at
ground potential (reference)

The component that offsets the depletion region charge is then equal to - QB/COX,
where COX is the gate oxide capacitance per unit area.

VLSI Design (EC-302) 120

There always exists a fixed positive charge density QOX at the interface between the gate oxide and the
silicon substrate, due to impurities and/or lattice imperfections at the interface. The gate voltage
component that is necessary to offset this positive charge at the interface is - QOX/COX. For zero substrate
bias threshold voltage VT0 expressed as

For nonzero substrate bias

VLSI Design (EC-302) 121

In generalized form threshold Voltage can be written as

In this case, the threshold voltage differs from VT0 only by an additive term. This substrate-bias term is
a simple function of the material constants and of the source-to-substrate voltage VSB.

The general expression of the threshold voltage VT

VLSI Design (EC-302) 122

• The substrate Fermi potential ϕF is negative in nMOS, positive in pMOS.
• The depletion region charge densities QB0 and QB are negative in nMOS,
positive in pMOS.
• The substrate bias coefficient γ is positive in nMOS, negative in pMOS.
• The substrate bias voltage VSB is positive in nMOS, negative in pMOS.
and

VLSI Design (EC-302) 123

Example

Fermi potentials for the p-type substrate and for the n-type polysilicon gate:

VLSI Design (EC-302) 124

VLSI Design (EC-302) 125
VLSI Design (EC-302) 126
 Gradual Channel Approximation
The boundary conditions for the channel voltage VC are:

Eq. 1

Also, it is assumed that the entire channel region between the source and
the drain is inverted, i.e.,

Eq. 2

The channel current (drain current) ID is due to the electrons in the N-channel MOSFET operating in linear region
channel region traveling from the source to the drain under the influence
of the lateral electric field component Ey.

VLSI Design (EC-302) 127

QI(y) is the total mobile electron charge in the surface inversion
layer. This charge can be expressed as

Eq. 3
Now consider the incremental resistance dR of the differential
channel segment. Assuming that all mobile electrons in the inversion
layer have a constant surface mobility µn, the incremental resistance
can be expressed as follows.
Eq. 4

Applying Ohm’s law for this segment yields the voltage drop Simplified geometry of the surface inversion layer (channel region).
along the incremental segment dy, in the y direction.

Eq. 5

This equation can now be integrated along the channel, i.e., from y = 0 to y = L, using the
boundary conditions are given in Eq. 1.

Eq. 6

VLSI Design (EC-302) 128

 Replacing Qi(y) with Eq. 3.

Eq. 7

Assuming that the channel voltage VC, is the only variable in (Eq. 7) that depends on the position y, the
drain current is found as follows.

Eq. 8

Equation 8 represents the drain current ID as a simple second-order function of the two external voltages,
VGS and VDS This current equation can also be rewritten as

Eq. 9

or
Eq. 10
VLSI Design (EC-302) 129
Where the parameter k and k’ are defined as

Eq. 11
and
Eq. 12

Now that the drain current equation (8) has been derived under the following voltage assumptions,

Eq. 13

the current equation (8) is not valid beyond the linear region/ saturation region boundary, i.e., for
Eq. 14
This saturation drain current level can be found simply by substituting Eq. 14 for VDS in Eq. 8.

Eq. 15

VLSI Design (EC-302) 130

MOSFET I-V Characteristics

Basic I-V Characteristics of n-channel MOSFET

VLSI Design (EC-302) 131
ID Vs VDS Relationship

VLSI Design (EC-302) 132

VLSI Design (EC-302) 133
VLSI Design (EC-302) 134
 MOSFET Operation: A Qualitative View

Cross-sectional view of an n-channel (nMOS) transistor, (a) operating in the linear region, (b) operating at the edge of
saturation, and (c) operating beyond saturation.
VLSI Design (EC-302) 135
Secondary Effects
Threshold Variations

Eq. states that the threshold voltage is only a function of the

manufacturing technology and the applied body bias V . As the
SB

device dimensions are reduced, this model becomes

inaccurate, and the threshold potential becomes a function of
A similar effect can be obtained by raising the
L, W, and VDS.
drain-source (bulk) voltage, as this increases the
width of the drain-junction depletion region.
Consequently, the threshold decreases with
increasing VDS. This effect, called the drain-induced
barrier lowering, or DIBL, causes the threshold
potential to be a function of the operating voltages.

DIBL VLSI Design (EC-302) 136

Punch through
For high enough values of the drain voltage, the source and drain regions can
even be shorted together, and normal transistor operation ceases to exist. The
sharp increase in current that results from this effect, which is called punch-
through, may cause permanent damage to the device and should be avoided.

VLSI Design (EC-302) 137

Narrow-channel effects
The depletion region of the channel does not stop abruptly at the edges of the transistor, but
extends somewhat under the isolating field-oxide. The gate voltage must support this extra
depletion charge to establish a conducting channel. This effect is ignorable for wide transistors, but
becomes significant for small values of W, where it results in an increase of the threshold voltage.
For small geometry transistors, with small values of L and W, the effects of short- and narrow
channels may tend to cancel each other out.

VLSI Design (EC-302) 138

Hot-Carrier Effects
Device dimensions have been scaled down continuously, while the
power supply and the operating voltages were kept constant. The
resulting increase in the electrical field strength causes an
increasing velocity of the electrons, which can leave the silicon and
tunnel into the gate oxide upon reaching a high-enough energy
level. Electrons trapped in the oxide change the threshold voltage,
typically increasing the thresholds of NMOS devices, while
decreasing the VT of PMOS transistors.
• For an electron to become hot, an electrical field of at least 104
V/cm is necessary.
• The hot-electron phenomenon can lead to a long-term reliability
problem, where a circuit might degrade or fail after being in use
for a while.

Hot-carrier effects cause the I-V characteristics of an NMOS

VLSI Design (EC-302) transistor to degrade from extensive usage 139
CMOS Latchup
The MOS technology contains a number of intrinsic bipolar transistors. These are especially
troublesome in CMOS processes, where the combination of wells and substrates results in the
formation of parasitic n-p-n-p structures. Triggering these thyristor-like devices leads to a shorting
of the VDD and VSS lines, usually resulting in a destruction of the chip, or at best a system failure that
can only be resolved by power-down.

VLSI Design (EC-302) 140

Latchup prevention
From the above analysis the message to the designer is clear—to avoid latchup, the resistances
Rnwell and Rpsubs should be minimized. This can be achieved by providing numerous well and
substrate contacts, placed close to the source connections of the NMOS/PMOS devices. Devices
carrying a lot of current (such as transistors in the I/O drivers) should be surrounded by guard rings.
These circular well/substrate contacts, positioned around the transistor, reduce the resistance even
further and reduce the gain of the parasitic bipolars.

VLSI Design (EC-302) 141

Channel Length modulation

The saturation-region relationship between gate-to-source

voltage (VGS) and drain current (ID) is expressed as follows:

This brings us to our channel-length-modulation-compliant

expression for saturation-region drain current:

VLSI Design (EC-302) 142

Velocity Saturation
Velocity saturation effect. states that the velocity of the carriers is proportional to the electrical
field, independent of the value of that field. In other words, the carrier mobility is a constant.
However, at high field strengths, the carriers fail to follow this linear model. In fact, when the
electrical field along the channel reaches a critical value xc, the velocity of the carriers tends to
saturate due to scattering effects (collisions suffered by the carriers).

VLSI Design (EC-302) 143

Subthreshold Conduction
A closer inspection of the ID-VGS curves of Figure reveals that the current does not drop abruptly to 0
at VGS = VT. It becomes apparent that the MOS transistor is already partially conducting for voltages
below the threshold voltage. This effect is called subthreshold or weak-inversion conduction.

The (inverse) rate of decline of the current with respect to VGS

below VT hence is a quality measure of a device. It is often
quantified by the slope factor S, which measures by how much
VGS has to be reduced for the drain current to drop by a factor of
10.

with S is expressed in mV/decade. For an ideal transistor with

the sharpest possible roll-off, n = 1 and (kT/q)ln(10) evaluates to
60 mV/decade at room temperature, which means that the
ID current versus VGS (on logarithmic scale), showing the subthreshold current drops by a factor of 10 for a reduction in
exponential characteristic of the subthreshold region. VGS of 60 mV.

VLSI Design (EC-302) 144

MOSFET Scaling and Small-Geometry Effects
The reduction of the size, i.e., the dimensions of MOSFETs, is commonly
referred to as scaling.

Two basic types of size-reduction strategies:

1. Full scaling (also called constant-field scaling)
2. Constant voltage scaling.

To describe device scaling, introduce a constant scaling factor S > 1. All

horizontal and vertical dimensions of the large-size transistor are then
divided by this scaling factor to obtain the scaled device.

VLSI Design (EC-302) 145

Table 1 It is seen that a new generation of manufacturing technology replaces the
previous one about every two or three years, and the down-scaling factor S of the
minimum feature size from one generation to the next is about 1.2 to 1.5.

Table 1: Reduction of the minimum feature size (minimum dimensions that can be defined and
manufactured on chip) over the years, for a typical CMOS gate-array process.

VLSI Design (EC-302) 146

We consider the proportional scaling of all three dimensions by the same scaling
factor S. Figure shows the reduction of key dimensions on a typical MOSFET,
together with the corresponding increase of the doping densities.

Scaling of a typical MOSFET by a scaling factor of S.

VLSI Design (EC-302) 147

Full Scaling (Constant-Field Scaling)
This scaling option attempts to preserve the magnitude of internal electric fields in
the MOSFET, while the dimensions are scaled down by a factor of S.
Table 2 lists the scaling factors for all significant dimensions, potentials, and doping
densities of the MOS transistor.

Full scaling of MOSFET dimensions, potentials, and doping densities.

VLSI Design (EC-302) 148
It will be assumed that the surface mobility µn is not significantly affected by the
scaled doping density. The gate oxide capacitance per unit area, on the other hand,
is changed as follows.

The transconductance parameter kn will also be scaled by a factor of S. The linear-

mode drain current of the scaled MOSFET can now be found as:

VLSI Design (EC-302) 149

Similarly, the saturation-mode drain current is also reduced by the same scaling
factor.

Now consider the power dissipation of the MOSFET. The instantaneous power
dissipated by the device (before scaling) can be found as:

The power dissipation of the transistor will be reduced by the factor S2.

VLSI Design (EC-302) 150

Since the gate oxide capacitance C is scaled down by a factor of S, we can predict
that the transient characteristics, i.e., the charge-up and charge-down times, of the
scaled device will improve accordingly.
Table 3 summarizes the changes in key device characteristics as a result of full
(constant-field) scaling.

Effects of full scaling upon key device characteristics.

VLSI Design (EC-302) 151

Constant-Voltage Scaling
In particular, the peripheral and interface circuitry may require certain voltage levels for all
input and output voltages, which in turn would necessitate multiple power supply voltages
and complicated level shifter arrangements. For these reasons, constant-voltage scaling is
usually preferred over full scaling.
In constant-voltage scaling, the power supply voltage and the terminal voltages, on the
other hand, remain unchanged. The doping densities must be increased by a factor of S2 in
order to preserve the charge-field relations.

Constant-voltage scaling of MOSFET dimensions, potentials, and doping densities.

VLSI Design (EC-302) 152

Since the terminal voltages remain unchanged, the linear mode drain current
of the scaled MOSFET can be written as:

Also, the saturation-mode drain current will be increased by a factor of S

after constant voltage scaling.

VLSI Design (EC-302) 153

VLSI Design (EC-302) 154
MOSFET Capacitances
In order to examine the transient (AC) response of MOSFETs and digital
circuits consisting of MOSFETs, we have to determine the nature and the amount of
parasitic capacitances associated with the MOS transistor.

Cross-sectional view and top view (mask view) of a typical n-channel MOSFET.
VLSI Design (EC-302) 155
In this figure, the mask length (drawn length) of the gate is indicated by LM, and the
actual channel length is indicated by L. The extent of both the gate-source and the
gate-drain overlap are LD; thus, the channel length is given by

Based on their physical origins, the parasitic device capacitances can be classified
into two major groups: oxide-related capacitances and junction capacitances.

Lumped representation of the parasitic MOSFET capacitances.

VLSI Design (EC-302) 156

The two overlap capacitances that arise as a result of this structural
arrangement are called CGD (overlap) and CGS (overlap),respectively.
Assuming that both the source and the drain diffusion regions have the same
width W, the overlap capacitances can be found as

with

both of these overlap capacitances do not depend on the bias conditions,

i.e., they are voltage-independent.

VLSI Design (EC-302) 157

The capacitances which result from the interaction between the gate voltage and the
channel charge. Since the channel region is connected to the source, the drain, and the
substrate, we can identify three capacitances between the gate and these regions, i.e., Cgs,
Cgd and Cgb respectively.

In cut-off mode (Fig. (a)), the surface is not inverted. Consequently, there is no conducting
channel that links the surface to the source and to the drain. Therefore, the gate-to-source
and the gate-to-drain capacitances are both equal to zero: Cgs = Cgd= 0. The gate-to-
substrate capacitance can be approximated by

VLSI Design (EC-302) 158

In linear-mode operation, the inverted channel extends across the MOSFET, between the source and the drain
(Fig. (b)). This conducting inversion layer on the surface effectively shields the substrate from the gate
electric field; thus, Cgb = 0.

When the MOSFET is operating in saturation mode, the inversion layer on the surface does not extend to the
drain, but it is pinched off (Fig. (c)). The gate-to-drain capacitance component is therefore equal to zero (Cgd
=0). Since the source is still linked to the conducting channel, its shielding effect also forces the gate-to-
substrate capacitance to be zero, Cgb = 0. Finally, the distributed gate-to-channel capacitance as seen
between the gate and the source can be approximated by

VLSI Design (EC-302) 159

 Approximate oxide capacitance values for three operating modes of the MOS

Variation of the distributed (gate-to-channel) oxide capacitances as functions of gate-to-source voltage VGS.
VLSI Design (EC-302) 160
Junction Capacitances
Now we consider the voltage-dependent source-substrate and drain-substrate
junction capacitances, Csb and Cdb, respectively.

Three-dimensional view of the n' diffusion region within the p-type substrate.

VLSI Design (EC-302) 161

 Types and areas of the pn-junctions shown in Figure

To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, consider first the depletion
region thickness, Xd. Assuming that the n-type and p-type doping densities are given by ND and NA,
respectively, and that the reverse bias voltage is given by V (negative), the depletion region thickness
can be found as follows:

Eq.1

Where the built in potential is calculated as

Eq. 2

VLSI Design (EC-302) 162

Note that the junction is forward-biased for a positive bias voltage V, and reverse-biased
for a negative bias voltage. The depletion-region charge stored in this area can be written
in terms of the depletion region thickness, xd.

Eq. 3

Here, A indicates the junction area. The junction capacitance associated with the depletion
region is defined as

Eq. 4

By differentiating Q j with respect to the bias voltage V, we can now obtain the
expression for the junction capacitance as follows.

Eq. 5

VLSI Design (EC-302) 163

This expression can be rewritten in a more general form, to account for the junction grading.

Eq. 6

The parameter m is called the grading coefficient. Its value is equal to 1/2 for an abrupt junction profile, and 1/3
for a linearly graded junction profile. Obviously, for an abrupt pn-junction profile, i.e., for m = 1/2, the equations
(3.103) and (3.104) become identical. The zero-bias junction capacitance per unit area Cjo is defined as

Eq. 7

The problem of estimating capacitance values under changing bias conditions can be simplified, if we
calculate a large-signal average (linear) junction capacitance instead, which, by definition, is independent of
the bias potential. This equivalent large-signal capacitance can be defined as follows:

Eq. 8

VLSI Design (EC-302) 164

Here, the reverse bias voltage across the pn-junction is assumed to change from VI to V2. Hence, the
equivalent capacitance Ceq is always calculated for a transition between two known voltage levels.
By substituting Eq. 6 into Eq. 8, we obtain

Eq. 9

Eq. 10
This equation can be rewritten in a simpler form by defining a dimensionless coefficient Keq as
follows:
Eq. 11
where

where Keq is the voltage equivalence factor(note that 0 < Keq < 1). Thus, the coefficient Keq allows us to
take into account the voltage-dependent variations of the junction capacitance.

VLSI Design (EC-302) 165