ACKNOWLEDGEMENT

We would like to present sincere thanks to our Skill Oriented Course -3 Coordinator
Dr. E. KUSUMA KUMARI, M.Tech., Ph.D. for the guidance and help throughout the
development of this Skill Oriented Course-3 on “ASIC SEMI-CUSTOM IC DESIGN AND
FPGA IMPLEMENTATION” by providing us the required information. Without his
supervision, support, and encouragement. We would not gain awareness of many new things
during this Course.
We would like to thank Dr. E. KUSUMA KUMARI, M.Tech., Ph.D. Head of the
department of Electronics & Communication Engineering for supporting us to do our Skill
Oriented Course-3 Successfully.
We would like to sincerely thank to the respected Principal of our college,
Dr.G.V.N.S.R. RATNAKARARAO, BE, ME, Ph.D. for his constant support throughout the
Skill Oriented Course-3.
An Endeavour over long period can also be successful by constant effort and
encouragement.
We wish to take this opportunity to express our deep gratitude to all the people who
have extended their cooperation in various ways during our Skill Oriented Course3. It is our
pleasure to acknowledge the help of all those respected individuals.

Page | III
 TABLE OF CONTENTS
SNO TITLE PAGENO
1 CHAPTER-1 INTRODUCTION 1
1.1 Evolution of IC’S 1
1.2 VLSI design flow overview 2
1.3Front-end and Back design 2
1.4 Basic example of 2-input NAND 4
2 CHAPTER-2 ADVANCED VLSI CONCEPTS 5
2.1 Advanced VLSI Concepts 5
2.2 Future Trends in VLSI 5
2.3 Design Styles in VLSI 6
3 CHAPTER-3 DESIGN APPROACH 7
3.1 Full-Custom Design 7
3.2 Semi-Custom Design 8
3.3 Programmable ASIC-FPGA/PLD 8
4 CHAPTER-4 PHYSICAL DESIGN 9
4.1 What is Physical Design? 9
4.2 Steps in Physical Design 9
5 CHAPTER-5 TOOLS 10
5.1 VLSI tools 10
5.2 Open-Source Tools 10
6 CHAPTER-6 UBUNTU 12
6.1 Introduction to UBUNTU 12
6.2 Basic Commands Used 13
7 CHAPTER-7 BAMBU 14
7.1 Introduction to Bambu 14
7.2 Basic commands in Bambu 14
8 CHAPTER-8 ICARUS 16
8.1 Introduction to ICARUS 16
8.2 Basic Commands in ICARUS 16
9 CHAPTER-9 YOSYS 17
9.1 Introduction in Yosys 17
9.2 Basic Commands in Yosys 17
9.3 Output of Yosys 18
10 CHAPTER-10 OpenSTA 19
10.1 Introduction to OpenSTA 19
10.2 Basic Commands in OpenSTA 20
10.3 Output of OpenSTA 21

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SNO TITLE PAGENO
11 CHAPTER-11 OpenROAD 23
11.1 Introduction to OpenROAD 23
11.2 Basic Commands in OpenROAD 23
12 CHAPTER-12 FPGA 26
12.1 FPGA Introduction 26
12.2 Implementation Steps 27
12.3 Example for FPGA implementation 28
12.4 Advantages of FPGA 31
13 CHAPTER-13 CONCLUSION 34
14 CHAPTER-14 REFERENCES 35

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 LIST OF FIGURES
FIG.NO NAME OF THE FIGURE PAGENO
1 Moore’s Law 1
2 Front-End and Back-End Design 3
3 Ubuntu interface 12
4 C-language code 13
5 Bambu interface 15
6 C-code in verilog 15
7 Yosys Interface 18
8 Yosys Output 18
9 Interface of openSTA 20
10 Output-1 of OpenSTA 21
11 Output-2 of OpenSTA 21
12 OpenROAD interface 23
13 Nand gate output in OpenROAD 24
14 outputs in OpenROAD 24
15 Output-1 in OpenROAD 25
16 Output-2 in OpenROAD 25
17 FPGA pin description 26

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 1. INTRODUCTION

1.1 Evaluation of IC’s:

Moore's Law, which predicts the doubling of transistors on integrated circuits (ICs) every two
years, has significantly shaped the evolution of semiconductor technology. This exponential growth in
transistor density has enabled smaller, faster, and more energy-efficient ICs. However, as we approach
the physical limits of silicon scaling, particularly at the 3nm and 2nm nodes, maintaining this pace of
advancement has become increasingly challenging. Despite these hurdles, advances in materials, 3D
stacking, and architectural innovations continue to drive the push toward next-generation chips.

Fig-1 Moore’s Law

From 1 transistor in 1950 to 16 transistors in 1960, and then to 4,500 transistors in 1970 with
the advent of 8-bit processors, semiconductor technology rapidly evolved, enabling more complex and
powerful computing systems.

The development of semiconductor technology began with diodes, which were used for basic
rectification and switching. This led to the creation of the BJT (Bipolar Junction Transistor),
enabling more complex amplification and switching functions. As technology advanced, SSI (Small
Scale Integration) and MSI (Medium Scale Integration) allowed for integrating more transistors
onto a single chip, improving functionality. The progression continued with LSI (Large Scale
Integration), further increasing transistor count and enabling more complex circuits. Eventually,
VLSI (Very Large-Scale Integration) and ULSI (Ultra Large-Scale Integration) technologies
emerged, dramatically increasing integration levels and enabling the development of modern
microprocessors and highly complex systems.

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 In the 2020s, semiconductor technology has advanced to 2nm and 3nm nodes, enabling
unprecedented transistor density and performance. These cutting-edge processes, leveraging
innovations like gate-all-around (GAA) transistors, are driving next-generation computing power and
energy efficiency.

1.2 VLSI Design Flow Overview:

➢ Specification – This is the initial phase where the goals and requirements of the design are
defined, such as functionality, performance, power, and area constraints.
➢ Architecture Design (RTL) – The design is translated into a high-level architecture, typically
using Register-Transfer Level (RTL) description, which outlines how data flows between
registers and functional units.
➢ Functional & Logical Design – Using logical gates, the design is further refined by creating
circuits that perform the required functions, ensuring correct operation through Boolean logic.
➢ Circuit Design (Transistor Level) – The logical gates are translated into transistor-level
implementations, optimizing for performance, power consumption, and area at the transistor
scale.
➢ Physical Design (Layout) – The circuit is mapped onto a physical layout, detailing the
placement of transistors, routing of interconnections, and optimization for manufacturing
constraints.
➢ Fabrication Design (Chip Design) – The physical design is sent for semiconductor
fabrication, where the chip is created through photolithography, etching, and deposition
processes.
➢ Testing & Packaging – After fabrication, the chip undergoes rigorous testing to ensure
functionality, followed by packaging to protect the chip and make it ready for integration into
systems.

1.3 Front & Back End Design :

1.3.1 Front End Design

1) Design Specification - Design specification defines the functional requirements, performance goals,
and constraints of the chip, serving as a detailed blueprint for the entire design process. It outlines the
system's expected behavior, power consumption, timing, and other parameters to guide the design
team.

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2) RTL Description (HDL) - In this step, the design is described at the Register-Transfer Level (RTL)
using hardware description languages (HDLs) like Verilog or VHDL. RTL captures the data flow and
control logic, defining how the system's components interact and operate at a functional level, without
focusing on physical layout.

3) Functional Verification - Functional verification ensures that the RTL design behaves as expected
through simulation and testing. Using tools like ModelSim or VCS, the design is validated by applying
test vectors to check if it meets the specification and performs the required operations correctly.

Fig -2 Front-End and Back-End Design

1.3.2 Back End Design

4) Logic Synthesis - Logic synthesis converts RTL (Register Transfer Level) descriptions into a gate-
level netlist, optimizing the design for performance, area, and power. It involves mapping high-level
design abstractions to technology-specific gates and components, ensuring correct functionality.

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5) Gate-Level Netlist - The gate-level netlist is a representation of the design in terms of logic gates
(AND, OR, NAND, etc.), flip-flops, and other standard cells. It serves as the input for the next stages
of physical design, ensuring that the design logic is mapped to the available technology libraries.

6) Logic Equivalence Check (LEC) - Logic Equivalence Check (LEC) ensures that the synthesized
gate-level netlist is functionally equivalent to the original RTL design. This step verifies that no errors
were introduced during synthesis and that the gate-level representation accurately reflects the intended
design behavior.

7) Place & Route - Place & Route is the process of physically positioning and connecting the standard
cells (gates, flip-flops, etc.) on the chip. Placement optimizes the location of cells, while routing
connects them using metal layers, ensuring that the design meets timing, power, and area constraints.

8) Physical Layout - Physical layout refers to the final arrangement of all components and
interconnections on the chip, including the placement of cells, routing of wires, and definition of metal
layers. The layout must meet design rules for manufacturing and ensure that the chip operates correctly
in real-world conditions.

9) Physical Verification - Physical verification checks the layout against design rules (DRC), ensures
the connectivity matches the schematic (LVS), and performs checks for electrical correctness (ERC).
This step ensures that the layout adheres to manufacturing constraints and functions as intended.

10) GDSII - GDSII (Graphic Data System II) is the file format used to represent the final chip layout
and is used for manufacturing. It contains detailed information about the physical design, including
the placement of cells, routing, and metal layers, and is the format sent to the foundry for chip
fabrication.

1.4 Basic Example:

2 Input NAND Gate

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 2. ADVANCED VLSI

2.1 Advanced VLSI Concepts:

1) Scaling & Power - As transistor sizes shrink, power density increases, making power management
a critical challenge in advanced VLSI design, requiring new techniques like dynamic voltage scaling
and power gating.

2) Design for Low Power - Design for low power focuses on reducing power consumption through
techniques such as clock gating, voltage scaling, and optimizing logic paths to minimize dynamic and
static power dissipation.

3) Design for Testability - Design for testability (DFT) involves incorporating features like scan
chains and built-in self-test (BIST) to ensure that ICs can be easily tested for defects and performance
issues during manufacturing.

4) ASIC vs FPGA - ASICs (Application-Specific Integrated Circuits) are custom-designed for specific
applications, offering high performance and efficiency, while FPGAs (Field-Programmable Gate
Arrays) are reconfigurable, offering flexibility but at the cost of lower performance and higher power
consumption.

5) System on Chip (SoC) - A System on Chip (SoC) integrates multiple components such as
processors, memory, I/O, and peripherals onto a single chip, providing a complete solution for
compact, high-performance, and energy-efficient systems.

2.2 Future Trends In VLSI

1) 3D ICs - 3D ICs stack multiple layers of integrated circuits vertically, improving performance,
reducing interconnect delays, and saving space. This technology allows for higher transistor density,
greater bandwidth, and energy efficiency, particularly useful for high-performance computing and
memory applications.

2) Quantum Computing (Qubits) - Quantum computing leverages quantum bits (qubits), which can
exist in multiple states simultaneously, offering exponential speedup for certain complex problems
like cryptography and simulation. Although still in early stages, quantum computing holds the potential
to revolutionize fields requiring massive parallel processing.

3) Neuromorphic Computing (AI/ML) - Neuromorphic computing mimics the structure and

functioning of the human brain to enable efficient processing of AI/ML tasks, using spiking neural

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networks. This approach promises to greatly enhance the speed, power efficiency, and scalability of
AI systems by replicating biological learning and memory processes.

2.3 Design Styles in VLSI

1) Full Custom - In full custom design, every aspect of the IC, including the transistor level layout, is
tailored to meet specific requirements, offering maximum performance but requiring significant design
time and effort.

2) Semi-Custom - Semi-custom design uses pre-designed standard cells or blocks (e.g., libraries of
logic gates) and customizes the interconnections, balancing design flexibility and development time.

3) FPGA (Field-Programmable Gate Array) - FPGAs are programmable devices that allow users to
configure the hardware logic after manufacturing, offering flexibility for prototyping and adaptable
designs but with lower performance than ASICs.

4) ASIC (Application-Specific Integrated Circuit) - ASICs are custom-designed chips optimized

for a specific application, providing high performance, low power, and small form factor, but at the
cost of higher development and manufacturing costs.

5) Structured ASIC - Structured ASICs offer a middle ground between FPGAs and full custom
designs, providing pre-designed logic blocks that can be customized for specific needs, offering faster
time-to-market than full custom designs.

6) SoC (System on Chip) - A System on Chip (SoC) integrates all the components of a complete
system, such as CPU, memory, and peripherals, into a single chip, enabling compact, power-efficient,
and cost-effective solutions for modern applications.

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 3. DESIGN APPROACH

3.1 Full-Custom Design:

Full custom design in VLSI is an approach where every aspect of an integrated circuit (IC) is
custom-designed from scratch, providing the highest level of optimization for performance, power,
and area. Unlike semi-custom or standard cell-based designs, where pre-designed components are
reused, full custom design involves designing every logic gate, transistor, and interconnection at the
transistor level. This design approach offers maximum flexibility and control, allowing designers to
optimize each aspect of the circuit, such as speed, power efficiency, and chip area, to meet specific
application requirements. It is typically used in cases where performance is critical, such as in high-
performance processors or specialized circuits.

The full custom design flow begins with the design specification, where the functional and
performance requirements of the circuit are defined. After that, the designer manually creates the
transistor-level schematic, selecting and sizing transistors to meet the desired functionality. The next
step involves custom layout design, where the physical layout of transistors, interconnections, and
components is carefully planned to minimize area and optimize performance. Once the layout is
completed, the design undergoes transistor-level simulations to ensure that the circuit functions as
intended. After simulation, Design Rule Checking (DRC) and Layout vs. Schematic (LVS) checks
are performed to ensure that the layout adheres to manufacturing constraints and matches the
schematic. The final step involves tape-out, where the design is sent to the foundry for fabrication.
Full custom design offers the highest level of performance and efficiency but comes with significant
challenges, including longer development time, higher cost, and increased complexity.

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3.2 Semi-Custom Design:

Semi-custom design in VLSI refers to a design approach that strikes a balance between full
custom design and standard cell-based design. It uses pre-designed, reusable blocks or cells (such as
logic gates, flip-flops, and memory modules) while still allowing for some level of customization. In
this approach, designers select and arrange these standard cells to create a functional circuit,
significantly reducing development time and cost compared to full custom designs. The process
typically begins by defining the design specifications and functional requirements, followed by the
selection of appropriate standard cells from a library to meet those needs.

After selecting the cells, the next step involves creating an RTL (Register Transfer Level)
description of the circuit, which is then synthesized into a gate-level netlist. The cells are placed in a
physical layout, where timing analysis and power optimization are performed. Finally, the design
undergoes simulation and design rule checking (DRC) to ensure correctness and compliance with
manufacturing constraints. Semi-custom design is widely used for applications that require a balance
of performance and time-to-market, such as mid-range processors, consumer electronics, or
communication systems. This approach offers a compromise between the flexibility of full custom
design and the time efficiency of standard cell-based design.

3.3 Programmable ASIC – FPGA/PLD

Programmable ASICs, such as FPGAs (Field-Programmable Gate Arrays) and PLDs

(Programmable Logic Devices), offer a flexible and cost-effective solution by allowing hardware to
be reconfigured after manufacturing. Unlike custom ASICs, which are hardwired for specific
functions, programmable ASICs can be reprogrammed to perform different tasks, making them ideal
for rapid prototyping, low-volume production, and applications that require evolving functionality.
FPGAs and PLDs are especially useful for applications where time-to-market is critical, providing the
ability to modify hardware behaviour even after deployment.

The design flow for programmable ASICs begins with defining functional specifications and
selecting the appropriate FPGA or PLD device based on the required resources. Designers then
describe the circuit using HDL (Hardware Description Language), such as VHDL or Verilog. The
design undergoes synthesis, where the HDL code is converted into a netlist of logic gates mapped to
the programmable elements of the device. Next, placement and routing are performed to assign
physical locations and interconnections, followed by functional verification and timing analysis.
Finally, the design is configured into the FPGA or PLD for execution.

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 4. PHYSICAL DESIGN

4.1 What is Physical Design?

Physical design is the process of converting a circuit’s logical netlist into a physical layout,
which defines the actual placement of components and routing of interconnections on the chip. The
goal is to optimize key design constraints such as performance, power consumption, and chip area
while ensuring manufacturability and meeting design rules.

4.2 Steps in Physical Design:

1. Partitioning: Dividing the IC design into smaller subblocks to make the design process more
manageable and modular.
2. Floor planning: Determining the optimal placement of subblocks, I/O pads, and power/ground
regions to ensure efficient layout and signal flow.
3. Placement: Positioning the subblocks on the chip while considering factors like power, ground
connections, and minimizing routing congestion.
4. Clock Tree Synthesis (CTS): Designing a clock distribution network to evenly distribute the
clock signal to all sequential circuits, ensuring synchronized operation.
5. Signal Routing: Connecting the submodules by routing signals between the placed blocks while
minimizing delay and congestion.
6. Timing Closure: Ensuring that all blocks meet timing constraints, such that signals propagate
through the design correctly within the required clock cycles.
7. DRC & LVS: Performing Design Rule Checking (DRC) to verify compliance with fabrication
constraints and Layout vs. Schematic (LVS) to ensure the layout matches the original
schematic design.

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 5. TOOLS

5.1 VLSI Tools:

Cadence Innovus, Synopsys IC Compiler, and Mentor Graphics Calibre are widely used in the
semiconductor industry for physical design, place and route, and physical verification of advanced
integrated circuits, with Innovus and IC Compiler being dominant for high-performance ASIC design,
while Calibre is the industry-standard tool for DRC, LVS, and parasitic extraction in the final
verification stages.

These are proprietary tools from leading EDA (Electronic Design Automation) vendors:

• Cadence Innovus: A comprehensive place and route tool used for physical design, timing
closure, and optimization in VLSI chip design.

• Synopsys IC Compiler: Another industry-standard tool for physical design (place-and-route),

timing optimization, and power optimization for digital ICs.

• Mentor Graphics Calibre: A widely used physical verification tool, which includes DRC
(Design Rule Checking), LVS (Layout vs. Schematic), and parasitic extraction.

The final outcome of using these tools is the generation of a GDSII file, which contains the
detailed physical layout of the chip, ready for manufacturing.

5.2 Open-Source Tools:

➢ Ubuntu: This is not a VLSI tool but rather an operating system (a popular Linux distribution)
on which many VLSI and EDA tools can run, including both proprietary and open-source tools.
➢ Bambu: Bambu is a relatively lesser-known open-source FPGA synthesis toolchain, focused
on high-level synthesis (HLS) for FPGA designs.
➢ Icarus Verilog: An open-source simulator for Verilog, used for simulation and verification of
digital designs. It supports compiling and simulating Verilog HDL code.
➢ Yosys: Yosys is an open-source synthesis tool primarily used for FPGA synthesis. It is capable
of optimizing and converting HDL descriptions (like Verilog) into gate-level netlists, primarily
for FPGA devices.

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➢ OpenSTA: OpenSTA (Open-Source Static Timing Analysis) is an open-source static timing
analysis tool that can be used for timing verification and optimization of digital designs. It is
often used as a free alternative to proprietary STA tools like Primetime from Synopsys.
➢ OpenROAD: OpenROAD is an open-source tool for full-chip place and route of digital VLSI
designs, providing an open alternative to proprietary tools like Cadence Innovus and Synopsys
IC Compiler. It aims to provide a complete flow for physical design, including placement,
routing, timing closure, and DRC.

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 6. UBUNTU

6.1 Introduction to UBUNTU:

Ubuntu is a popular, open-source operating system based on Linux, widely used by

developers, engineers, and researchers for its stability, security, and flexibility [1]. It provides a user-
friendly interface and robust support for software development, making it a preferred choice for
running a wide range of applications, including VLSI (Very-Large-Scale Integration) design tools.
Ubuntu’s compatibility with open-source tools and its extensive software repositories allow designers
to run various VLSI tools like Yosys, OpenROAD, and Icarus Verilog effectively, making it ideal
for chip design, simulation, and verification tasks.

Ubuntu’s open-source nature also allows for easy customization, enabling users to optimize
their environment for specific design workflows, whether for FPGA synthesis, static timing analysis,
or physical design [2]. Its stable architecture and ease of access to the terminal make it highly suitable
for running command-line-based VLSI tools and scripts, ensuring efficient handling of resource-
intensive tasks in the design process. Ubuntu’s popularity within the VLSI community further fosters
collaboration and support, as users benefit from a large base of tutorials, forums, and community
contributions [3].

Fig-3 Ubuntu interface

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6.2 Basic Commands Used:

➢ $ cd: Changes the current directory to the specified path.

Example: cd /home/user/Documents
➢ $ ls: Lists the contents of the current directory, such as files and folders.
Example: ls -l (for detailed listing)
➢ $ mkdir directory_name: Creates a new directory with the specified name.
Example: mkdir new_folder
➢ $ touch filename: Creates an empty file with the given name or updates the timestamp of an
existing file.
Example: touch newfile.txt
➢ $ cp: Copies files or directories from one location to another.
Example: cp file1.txt /home/user/
➢ $ vim filename: Opens a file for editing in the Vim text editor.
Example: vim script.sh
➢ esc & then :wq: In Vim, press Esc to exit insert mode, then type :wq to save and quit the
editor.
Example: After editing, press Esc and type :wq to save and exit.

Fig-4 C-language code

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 7. BAMBU

7.1 Introduction to BAMBU:

Bambu is an open-source, high-level synthesis (HLS) tool designed to optimize and generate
hardware implementations for FPGA and ASIC designs from high-level programming languages like
C or C++ [4]. Developed as part of the Xilinx Research Lab initiative, Bambu enables the automatic
generation of hardware descriptions (in Verilog or VHDL) by translating high-level algorithmic code
into efficient hardware structures. This tool simplifies the design process for FPGA designers by
automating many of the steps involved in hardware creation, allowing them to focus more on
algorithmic optimization rather than manual RTL (Register Transfer Level) coding [5]. It supports
parallelism, pipelining, and other performance-enhancing techniques that are essential for modern
hardware acceleration tasks.

Bambu’s ability to map complex algorithms directly to hardware accelerates development

cycles, particularly for FPGA-based applications. By leveraging high-level constructs and optimizing
them for hardware execution, Bambu allows designers to achieve high performance with fewer manual
intervention steps. It is particularly useful for applications in signal processing, machine learning,
image processing, and other domains where custom hardware solutions are necessary. While tools like
Bambu offer significant automation, they also provide flexibility for designers to adjust the hardware
generation process to meet specific application requirements, making them a powerful option for both
academic research and industrial FPGA design.

Bambu is an open-source high-level synthesis (HLS) tool that converts C or C++

programs into hardware description languages like Verilog or VHDL, enabling the automatic
generation of optimized hardware implementations for FPGA and ASIC designs [6].

7.2 Basic Commands in Bambu

➢ Bambu Installation Check Command:

After installing Bambu, you can check if the installation was successful using the following
command:

$ ./bambu – 0.9.7.AppImage

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 Fig-5 Bambu interface

➢ Running Bambu to Convert C to Verilog:

To convert a C program to Verilog code, you would use the following command structure in
Bambu:

$ ./bambu – 0.9.7.AppImage directory_name/file_name

Ex:$ ./bambu – 0.9.7.AppImage tutorial/ex1.c

Fig-6 C-code in verilog

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 8. ICARUS

8.1 Introduction to ICARUS:

Icarus Verilog is an open-source Verilog simulation and synthesis tool that is widely used for
digital design verification and simulation. It supports both Verilog-2001 and some SystemVerilog
constructs, allowing users to write and simulate hardware designs in the Verilog language [7].
Icarus Verilog is commonly used by students, hobbyists, and professionals for simulating simple
to complex digital circuits, providing an accessible and powerful solution for verifying the
functionality of Verilog designs. It is well-regarded for its ease of use, flexibility, and compatibility
with various platforms, making it a popular choice for FPGA and ASIC design workflows.

One of the key advantages of Icarus Verilog is its compatibility with other simulation and
synthesis tools, enabling users to integrate it into larger design flows. It can generate simulation
waveforms, output simulation results, and even interface with waveform viewers like GTKWave
to analyze the behavior of digital circuits [8]. Although Icarus Verilog lacks some of the advanced
features of commercial simulators, its open-source nature and ability to work with a wide range of
Verilog constructs make it an invaluable tool for educational purposes and low-cost design
projects. Additionally, it supports basic synthesis for FPGA designs and provides users with an
essential tool to verify and debug their hardware designs effectively.

Icarus Verilog is used to check for errors in Verilog programs. You can directly simulate
Verilog code with Icarus, or alternatively, you can take a C program and convert it to Verilog
using Bambu, and then use Icarus for simulation and error checking [9].

For verification with Icarus Verilog, a testbench file must also be created to provide stimulus
and observe the outputs of the design under test (DUT) during simulation.

8.2 Basic Commands in ICARUS:

➢ Compile the Verilog code (including the design and testbench files):

$ iverilog -o output_file.vvp design.v testbench.v

iverilog: The Icarus Verilog compiler., -o output_file.vvp: Specifies the output file
(output_file.vvp) that will be generated after compilation., design.v: Your Verilog design file.,
testbench.v: Your testbench file.

Ex: $ iverilog -o ha ha.v tbha.v

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 9. YOSYS

9.1 Introduction to YOSYS:

Yosys is an open-source synthesis tool primarily used for FPGA and ASIC design, aimed at
converting hardware description languages (HDLs) like Verilog into optimized gate-level
representations. It is widely recognized for its flexibility, supporting a variety of synthesis tasks,
including technology mapping, logic optimization, and decomposition [10]. Yosys can handle a
broad range of HDL constructs and can be integrated into larger toolchains for high-level synthesis
(HLS), providing a crucial step in the digital design flow. As an open-source tool, Yosys is particularly
popular in academic research and the open hardware community, providing an accessible, cost-
effective alternative to proprietary synthesis tools.

One of the key strengths of Yosys is its ability to work with various backend tools, offering
integration with other open-source projects like nextpnr (for FPGA place and route), ABC (for logic
optimization), and OpenROAD (for ASIC place and route). It also supports modern features such as
SystemVerilog and Verilog-2001 [11]. Yosys provides designers with advanced capabilities, such as
timing analysis, logic synthesis, and equivalence checking, making it an essential tool for verifying
and optimizing digital designs. Its open-source nature encourages innovation, and it has been embraced
by the hardware design community for building custom toolchains and automating synthesis tasks in
both academic and industrial settings.

To run Yosys, three essential files are typically required: a .v file (Verilog source code) that
contains the hardware description, a .lib file (library file) that defines the cell library and its
characteristics, including timing and area constraints, and a commands.tcl file (TCL script) that
contains the sequence of Yosys commands to perform synthesis, optimization, and mapping. The .v
file specifies the design logic, the .lib file provides necessary technology information for mapping the
design to actual hardware, and the commands.tcl file automates the synthesis process by defining the
steps to run within Yosys [12]. These files together enable the synthesis and optimization of the Verilog
design for various target technologies.

9.2 Basic Commands in YOSYS:

➢ Yosys Installation Check Command:

$ YOSYS

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 Fig-7 Yosys Interface

➢ Running Yosys with a TCL Script:

To run a Yosys synthesis flow using a TCL script, you can use the following command:
yosys script_commands.tcl
o yosys: This is the command to invoke the Yosys synthesis tool.
o script_commands.tcl: This is the TCL script file that contains the sequence of
commands that Yosys will execute. The script defines what steps Yosys should perform
(such as reading the Verilog file, synthesizing the design, applying optimizations, and
generating the output).
➢ Show
When you run the show command, Yosys will generate a visual representation (typically in a
graph or table format) of the design's cells, their interconnections, and the logic structure. This
is particularly useful for checking the results of synthesis, optimization, or transformations.

9.3 Output of YOSYS:

Fig-8 Yosys Output

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 10. OPENSTA

10.1 Introduction to OPENSTA:

OpenSTA (Open Static Timing Analysis) is an open-source tool designed for performing
static timing analysis (STA) on digital integrated circuits, especially in the context of ASIC design.
It is widely used for verifying the timing characteristics of a design by analyzing the propagation delays
of signals through the various paths in the circuit, ensuring that the design meets the required timing
constraints. OpenSTA can process netlists, timing libraries, and constraint files to identify timing
violations, such as setup and hold time violations, and generate reports that help designers optimize
their designs for performance, power, and area [13].

OpenSTA is designed to work in conjunction with other EDA tools in the ASIC design flow,
often being used after synthesis and place and route steps. It supports advanced features such as
multi-corner, multi-mode analysis, enabling it to handle various operating conditions (such as
voltage and temperature variations) and different modes of operation (like functional or test modes).
Being open-source, OpenSTA is highly flexible and customizable, making it a popular choice in
academic research, open hardware projects, and environments where cost-effective timing analysis is
crucial. It provides a valuable means of ensuring that timing constraints are met before tape-out and
manufacturing.

For OpenSTA (Open Static Timing Analysis) to perform timing analysis, several types of files
are required, each serving a specific purpose in the flow. The primary file is the .v file, which contains
the Verilog description of the design. This file represents the netlist of the design, including the logic
gates, connections, and other components that make up the circuit. OpenSTA uses this netlist to
perform static timing analysis by examining the signal propagation delays, path delays, and potential
timing violations in the circuit. Along with the Verilog file, OpenSTA also requires a .lib file, which
is a timing library that defines the timing characteristics of the standard cells used in the design. The
.lib file includes critical data such as cell delays, setup and hold times, slew rates, and other
parameters essential for accurate timing analysis [14].

In addition to the Verilog and timing library files, OpenSTA relies on the .sdc (Synopsys
Design Constraints) file, which defines the timing constraints for the design. The .sdc file includes
information about the clock period, input/output delays, and other relevant constraints that guide the
timing analysis process. It specifies how the design should behave under different operating conditions,
such as the clock's frequency and any additional timing constraints necessary for correct functionality.

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Finally, a .tcl file (TCL script) is typically used to automate the entire flow of OpenSTA. This script
contains a sequence of commands, such as loading the netlist, reading the timing library, setting up
constraints, performing timing analysis, and generating reports. The .tcl file allows users to run the
entire timing analysis process with a single command, improving efficiency and ensuring consistency
across multiple runs.

10.2 Basic Commands in OpenSTA:

➢ Check if OpenSTA is installed:

To check if OpenSTA is installed correctly, run the following command:
$ sta
This command starts the OpenSTA tool. If OpenSTA is installed correctly, it will launch the
OpenSTA shell. If it's not installed or not found in your PATH, you will get an error indicating
that the command is not recognized.

Fig-9 Interface of openSTA

$ cd OpenSTA

$ cd exercise ;exercise is the directory name created

➢ To run a TCL script:

source test.tcl
o source: This command is used in the OpenSTA shell to load and execute a TCL script file.
o test.tcl: This is the name of the TCL script file that contains the sequence of commands for
the timing analysis process. The script will typically include commands to read the design's
Verilog file, load the timing library, apply constraints, and perform timing analysis.

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10.3 Output of OpenSTA:

Fig-10 Output-1 of OpenSTA

Fig-11 Output-2 of OpenSTA

Path Types: MAX & MIN

• MAX (Maximum Path): This refers to the longest critical path in the circuit between two
registers or flip-flops. It is the path with the maximum propagation delay that needs to be

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 analyzed to ensure that data can propagate through the circuit within the required clock period.
A MAX path is important for ensuring that the design meets the setup time constraint; if the
maximum path delay is too long, data will not arrive on time for the next clock cycle, causing
timing violations.

• MIN (Minimum Path): This refers to the shortest path between two registers or flip-flops. It
is used to check whether the data holds long enough at the destination register to meet the hold
time requirement. The MIN path is important for ensuring that the data does not change too
soon after being captured by the register, which could cause hold-time violations. A MIN path
helps in identifying critical timing violations that might occur due to signal transitions
happening too early.

2. Slack (MET or NOT MET)

• Slack is the difference between the required time and the actual time taken for a signal to
propagate through a path. It indicates whether the timing requirement (setup or hold) has been
satisfied for a particular path.

o Slack = Required Time - Actual Time

• Slack MET: If the slack is positive or zero, the timing constraint is met. This means that the
data signal has enough time to propagate through the path and meet the timing requirements
(setup or hold time). A positive slack indicates that there is some margin, while zero slack
means the design is operating right at the limit.

• Slack NOT MET: If the slack is negative, the timing requirement is not met. A negative slack
indicates a timing violation, meaning that the data signal is arriving too late (setup violation)
or too early (hold violation), which can lead to incorrect behavior or logic failures in the design.
In this case, optimization or adjustments (such as changing the clock period or optimizing the
logic) are necessary to resolve the violation.

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 11. OPENROAD

11.1 Introduction to OpenROAD:

OpenROAD (Open Real-time Optimization and Automated Design) is an open-source, end-

to-end physical design tool for digital IC design, with a focus on automation and optimization. It
provides a comprehensive platform for placement, routing, clock tree synthesis (CTS), timing
optimization, and sign-off tasks, supporting ASIC and custom chip design [15]. OpenROAD aims
to streamline and accelerate the physical design flow by offering high-performance algorithms that
address the challenges of modern chip designs, such as power, area, and timing optimization. It is
designed to integrate well with other tools in the digital design ecosystem, enabling efficient chip
implementation from RTL (Register Transfer Level) through to the final GDSII layout for fabrication.

The key feature of OpenROAD is its focus on automated design [16]. It employs state-of-the-
art algorithms for place and route that automatically generate optimized layouts, ensuring that designs
meet performance targets while reducing manual intervention and time-to-market. As an open-source
tool, OpenROAD is highly flexible, allowing users to contribute to its development or modify it to suit
specific design needs. It has gained significant traction in both academic research and industry,
offering a cost-effective solution for digital design teams, particularly in the context of advanced node
technologies. OpenROAD has demonstrated competitive results in timing closure, power
optimization, and design rule checking (DRC), making it an invaluable resource for those working
on high-performance and low-power integrated circuits [17].

11.2 Basic Commands in OpenROAD:

➢ Check if OpenROAD is installed:

To check if OpenROAD is installed correctly, run the following command:

$ openroad

Fig -12 OpenROAD interface

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➢ To run a OpenROAD:

$ openroad -gui -log gcd_logfile_log gcd_nangate45.tcl

Fig-13 Nand gate output in OpenROAD

Fig-14 outputs in OpenROAD

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Fig-15 Output-1 in OpenROAD

Fig-16 Output-2 in OpenROAD

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 12. FPGA

12.1 FPGA Introduction:

An FPGA (Field-Programmable Gate Array) board is a type of hardware that allows users to
configure and customize the behaviour of the board’s internal circuits [18]. Unlike traditional
microcontrollers or processors, FPGAs can be reprogrammed after manufacturing, making them highly
flexible for a wide range of applications. These boards consist of an array of logic gates, memory
elements, and interconnects that can be programmed to perform specific tasks such as signal
processing, control, or data manipulation.

The key feature of FPGA boards is their parallel processing capability, where multiple tasks
can be executed simultaneously, providing a significant speed advantage over sequential processing
systems [19]. This makes them ideal for tasks that require high-performance computing, such as digital
signal processing, video encoding, cryptography, and machine learning. Users write code in hardware
description languages (HDLs) like VHDL or Verilog to define the logic and functionality of the FPGA.

FPGA boards typically include other components such as power supplies, input/output
interfaces, and memory modules, which make them versatile for various applications, from industrial
control systems to academic research. They can be connected to external devices and sensors, allowing
real-time data processing and enabling them to act as custom hardware accelerators for specific
computational tasks [20].

Fig-17 FPGA pin description

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12.2 Implementation Steps:

The basic implementation steps for VLSI (Very-Large-Scale Integration) design involve several key
stages, each focusing on different aspects of circuit design and layout. These steps typically include:

➢ Hardware Setup:

• Connect external devices to the FPGA’s I/O pins based on the interface requirements. For
example:

o For GPIO, directly connect switches or LEDs to FPGA I/O pins.

o For communication interfaces like SPI, connect the FPGA’s SPI pins to the
corresponding pins of external devices like sensors or memory chips.

o For display interfaces like VGA, connect the VGA lines (RGB, HSYNC, VSYNC) to
the FPGA's I/O pins.

➢ Software Configuration:

• In your FPGA development environment (e.g., Xilinx Vivado, Intel Quartus), configure the
I/O pins to function as input, output, or bidirectional as required by the peripheral.

• Implement the necessary protocols (SPI, I2C, UART, etc.) in the HDL code. This might involve
writing state machines or controllers to handle the data transfer.

➢ Programming and Testing:

• After writing the HDL code, synthesize, place, and route the design on the FPGA.

• Program the FPGA with the generated bitstream file and test the connections to external
hardware.

• Use debugging tools (e.g., ChipScope, SignalTap) to monitor the signals and verify that the
connections are functioning as expected.

12.3 Example for FPGA implementation:

1. Half Adder Overview

A half adder is a simple combinational circuit that adds two single-bit binary numbers. It has two
inputs and two outputs:

• Inputs: A, B (the two binary digits to be added)

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 • Outputs: Sum (S), Carry (C)

The logic is as follows:

• Sum (S) = A XOR B

• Carry (C) = A AND B

This logic is very simple, so it serves as a good starting point to implement on an FPGA.

2. FPGA Implementation Steps

Step 1: Create the Half Adder in HDL

You will write the logic for the half adder in Verilog or VHDL. Here, I'll show you the Verilog code
for the half adder.

Verilog Code for Half Adder

module half_adder(

input A, // First input bit

input B, // Second input bit

output Sum, // Sum of A and B

output Carry // Carry of A and B

);

// Sum is A XOR B

assign Sum = A ^ B;

// Carry is A AND B

assign Carry = A & B;

endmodule

In this Verilog code:

• The Sum is generated using the XOR operation.

• The Carry is generated using the AND operation.

Step 2: Define Testbench

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A testbench is essential to simulate and verify that the half adder works as expected before loading it
onto the FPGA.

Verilog Testbench for Half Adder

module test_half_adder;

// Test signals

reg A, B; // Inputs

wire Sum, Carry; // Outputs

// Instantiate the half adder module

half_adder ha(A, B, Sum, Carry);

// Test cases

initial begin

// Test all possible input combinations

$display("A B | Sum Carry");

A = 0; B = 0; #10;

$display("%b %b | %b %b", A, B, Sum, Carry);

A = 0; B = 1; #10;

$display("%b %b | %b %b", A, B, Sum, Carry);

A = 1; B = 0; #10;

$display("%b %b | %b %b", A, B, Sum, Carry);

A = 1; B = 1; #10;

$display("%b %b | %b %b", A, B, Sum, Carry);

$finish;

end

endmodule

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This testbench initializes the input signals A and B and displays the corresponding Sum and Carry
values for each input combination.

Step 3: Synthesize the Design

• Use an FPGA development environment like Xilinx Vivado or Intel Quartus to synthesize
the Verilog code.

• The FPGA synthesis tool will generate a netlist, map it to the FPGA resources, and create a
bitstream file. This file will be used to configure the FPGA.

Step 4: Program the FPGA

Once the bitstream file is ready, use the FPGA's development tool (e.g., Vivado or Quartus) to program
the FPGA.

• Connect FPGA to your computer using JTAG, USB, or other methods depending on the
FPGA board.

• Upload the bitstream generated from the synthesis tool to the FPGA.

3. FPGA Hardware Connections

Step 1: Connecting Inputs

To test the half adder on the FPGA board, you'll need to interface it with physical inputs and outputs:

• Inputs (A and B): Use switches or push buttons on the FPGA board to provide the input
values A and B. These will act as the two binary inputs for the half adder.

• Outputs (Sum and Carry): Use LEDs to display the result of the half adder. One LED will
indicate the Sum, and another will indicate the Carry.

Step 2: Configuring I/O Pins in FPGA

• Assign the switches (or buttons) on the FPGA board to the input pins A and B.

• Assign the LEDs to the output pins Sum and Carry.

In Vivado, this can be done using the I/O Planning tool to map the HDL ports (e.g., A, B, Sum, Carry)
to specific physical pins on the FPGA.

Step 3: Verifying with Real Hardware

• After programming the FPGA, toggle the switches for A and B and observe the LEDs.

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 • The LEDs will light up according to the sum and carry values:

o If A = 0, B = 0, the sum is 0, carry is 0.

o If A = 0, B = 1, the sum is 1, carry is 0.

o If A = 1, B = 0, the sum is 1, carry is 0.

o If A = 1, B = 1, the sum is 0, carry is 1.

This confirms that the half adder is working correctly in hardware.

12.4 Advantages of FPGA:

1. Flexibility and Reconfigurability

• Reprogrammable: FPGAs can be reprogrammed multiple times after manufacturing, allowing

users to change the design or functionality at any point in the development process. This makes
FPGAs ideal for iterative design, testing, and prototyping.

• Customizable Logic: You can configure the FPGA to implement a wide variety of digital
circuits and systems, tailoring the logic to the specific needs of the application.

2. Parallel Processing Capabilities

• Massive Parallelism: FPGAs allow for true parallel processing, meaning they can execute
many operations simultaneously. This makes them well-suited for tasks that require high
performance, such as signal processing, image processing, and cryptography.

• High-Speed Operations: The ability to run multiple operations in parallel drastically reduces
the time required to process data, leading to improved throughput and faster execution for
certain applications compared to traditional processors (CPUs).

3. Performance and Speed

• High-Speed Execution: FPGAs can operate at much higher clock speeds compared to general-
purpose CPUs for specific tasks. Custom-designed hardware accelerators in an FPGA can
achieve significant performance gains.

• Low Latency: FPGA boards can be designed for ultra-low latency processing by minimizing
the time it takes for data to move through the circuit. This is crucial for real-time systems like
telecommunications, radar, and high-frequency trading.

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4. Parallel I/O Handling

• Flexible I/O Configuration: FPGAs allow for the direct connection of high-speed I/O
interfaces like SPI, I2C, UART, PCIe, and more. This makes them ideal for interfacing with
sensors, cameras, or other peripheral devices in embedded systems.

• High Bandwidth: FPGAs can handle large amounts of data in parallel and provide high
bandwidth for communication with external devices, making them suitable for applications like
video streaming or large-scale data processing.

5. Cost-Effective for Low-Volume Production

• Prototyping and Development: FPGAs are often more cost-effective than custom ASICs
(Application-Specific Integrated Circuits) for low-volume production. Instead of designing a
custom chip, developers can quickly prototype their design on an FPGA and iterate as needed.

• Reduced Time-to-Market: FPGAs enable rapid development and prototyping, reducing the
time it takes to bring a new product or feature to market. Since the design is programmable,
changes can be made quickly without needing new hardware fabrication.

6. Low Power Consumption (When Optimized)

• Power Efficiency: While FPGAs can consume more power than some low-power
microcontrollers, they can be more power-efficient than traditional processors for certain types
of tasks, especially when highly parallel processing is involved.

• Power Scaling: Modern FPGAs have advanced features like power gating, which allows users
to selectively power down unused parts of the FPGA, improving energy efficiency.

7. Integration of Diverse Functions

• Multipurpose Applications: FPGAs allow designers to integrate multiple functions (e.g.,

signal processing, control systems, communication protocols) into a single chip. This can
reduce the number of components required in a system, leading to cost savings, reduced board
space, and fewer interconnections.

• Custom Accelerators: With FPGAs, you can design custom hardware accelerators to offload
specific computations from a CPU or GPU, increasing system performance for computationally
intensive tasks.

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8. Development Tools and Ecosystem

• Rich Development Tools: FPGA vendors (like Xilinx, Intel, and Lattice) provide robust
development environments such as Vivado, Quartus, and Libero. These tools offer synthesis,
simulation, debugging, and deployment capabilities to ease the design process.

• High-Level Synthesis: Some tools allow developers to use high-level languages such as
C/C++ to generate hardware designs, enabling rapid development even for those who may not
be familiar with hardware description languages (HDLs) like Verilog or VHDL.

9. High-Quality Prototyping for ASICs

• Testing for ASICs: FPGAs are commonly used to prototype ASIC designs. Since the FPGA
can implement the same logic as an ASIC, it allows engineers to test and validate the design in
real-world conditions before committing to the cost and time involved in manufacturing an
ASIC.

• Ease of Debugging: FPGAs offer tools like internal logic analyzers (e.g., Xilinx's ChipScope
or Intel's SignalTap) that allow for real-time debugging, making it easier to identify and resolve
issues during development.

10. Security and Confidentiality

• Custom Encryption: FPGAs can implement custom encryption algorithms and secure
communication protocols, which are increasingly important for secure data transmission, IoT
devices, and blockchain applications.

• Hardware Security: FPGAs can include secure boot capabilities, secure key storage, and
tamper detection features, offering a hardware-based security layer for sensitive applications.

11. Scalability and Future-Proofing

• Scalable Designs: FPGAs can be scaled to accommodate more complex designs. For instance,
an FPGA design that initially supports a basic function can be upgraded to add more features
or performance improvements without changing the physical hardware.

• Future Adaptation: Since FPGAs are reconfigurable, they allow systems to adapt to new
requirements or protocols in the future, offering a future-proof solution.

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 13. CONCLUSION
VLSI (Very-Large-Scale Integration) design is the cornerstone of modern electronics, enabling
the creation of highly integrated and compact circuits that power a wide range of devices, from
smartphones and computers to automotive systems and medical equipment. The VLSI design process
involves the integration of millions, or even billions, of transistors into a single chip, significantly
improving performance, reducing power consumption, and minimizing space requirements. This
miniaturization has led to the development of more powerful, energy-efficient, and cost-effective
devices, making VLSI design essential for the continued advancement of technology.

The VLSI design process is complex and requires a deep understanding of both digital and
analog circuits, as well as the use of specialized design tools and techniques. It involves several stages,
including architectural design, logic design, physical design, and verification. Engineers must tackle
challenges such as power management, heat dissipation, and timing optimization while ensuring that
the final design meets performance, reliability, and manufacturing requirements. The advent of tools
like Electronic Design Automation (EDA) software has revolutionized VLSI design, enabling
automation of many tasks and improving the accuracy and efficiency of the design process.

As technology continues to evolve, VLSI design plays a pivotal role in pushing the boundaries
of what is possible in electronics. The shift toward advanced semiconductor technologies, such as
FinFET and quantum computing, will continue to push VLSI design to new levels of complexity and
capability. Moreover, VLSI will remain at the heart of emerging fields such as artificial intelligence,
machine learning, and the Internet of Things (IoT), where the need for high-performance, low-power
chips is more critical than ever. The future of VLSI design promises exciting developments that will
shape the next generation of electronic devices and systems.

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