MARWADI UNIVERSITY

Subject Code:01CE0509
Subject Name: Fundamental of Processors
B.Tech. Year–III

Unit- 5
 Outline
Looping

• Syllabus
• 80286 Basic features
• 80386 Basic features
• 80486 Basic features
• Pentium Basic features
• Comparison Pentium and ARM processors
Syllabus

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80286 Basic Features
Microprocessor 80286 was introduced in 1982.
80286 microprocessor is an advanced version of the 8086
microprocessor that is designed for multi user and multitasking
environments.
It is 16 bit microprocessor and it has 24 address lines.
The 80286 addresses 16 MB of physical memory and 1G Bytes
of virtual memory by using its memory-management system.
The 80286 is basically an 8086 that is optimized to execute
instructions in fewer clocking periods than the 8086.

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80286 Architecture
The CPU, central processing unit of 80286 microprocessor,
consists of 4 functional block:
Address Unit
Bus Unit
Instruction Unit
Execution Unit

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80286 Basic Features
The 80286 operates in both the real and protected modes.
 In the real mode, the 80286 addresses a 1MB memory address
space and is virtually identical to 8086.
In the protected mode, the 80286 addresses a 16MB memory
In protected mode, it is possible to protect memory and other
system resources. Address unit becomes complete memory
management unit in protected mode.
The 80286 contains the same instructions except for a handful
of additional instructions that control the memory-management
unit
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Pin description of 80286
68 pins, PLCC package
Address bus and data bus are
not multiplexed.
Most of the pins are the same as
that of in 8086.
It has total 12 flags
6 Status flags (Same as 8086)
3 Control flags (Same as 8086)
3 Special field flags
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80386 Basic Features
 The 80386 microprocessor is an enhanced version of the 80286
microprocessor and includes a memory-management unit is enhanced
to provide memory paging.
 The 80386 also includes 32-bit extended registers and a 32-bit address
and data bus.
 The 80386 has a physical memory size of 4GB that can be addressed as
a virtual memory with up to 64TBytes.
 The 80386 is operated in the pipelined mode, it sends the address of
the next instruction or memory data to the memory system prior to
completing the execution of the current instruction

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80386 Basic Features
 This allows the memory system to begin fetching the next instruction or
data before the current is completed.
 This increases access time, thus reducing the speed of the memory.
 The I/O structure of the 80386 is almost identical to the 80286, except
that I/O can be inhibited when the 80386 is operated in the protected
mode through the I/O bit protection map.
 The register set of the 80386 contains extended versions of the
registers introduced on the 80286 microprocessor. These extended
registers include EAX, EBX, ECX, EDX, EBP, ESP, EDI, ESI, EIP and
EFLAGS.
 All 32 bit Registers and 32 bit instruction queue.
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80386 Basic Features
 The instruction set of the 80386 is enhanced to include instructions
that address the 32-bit extended register set.
 Interrupts, in the 80386 microprocessor, have been expanded to include
additional predefined interrupts in the interrupt vector table.
 The 80386 memory manager is similar to the 80286, except the physical
addresses generated by the MMU are 32 bits wide instead of 24-bits.
 The 80386 is also capable of paging. Page size is 4KB
 The 80386 is operated in the real mode (i.e. 8086 mode) when it is
reset.
 The real mode allows the microprocessor to address data in the first
1MByte of memory.
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80386 Basic Features
 In the protected mode, 80386 addresses any location in its 4G bytes of
physical address space.
 It has 32 bit address bus and 32 bit data bus which are not
multiplexed.
 We can broadly divide internal architecture into 3 sections:
1. Central processing unit
2. Memory Management unit
3. Bus Interface Unit

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80386 Block Diagram

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80386 Basic Features
 80386 Consists of
 Eight 32 bit general purpose registers
 One 32 bit Flag Register
 Six Segment Register
 Four Control Register
 Four Memory Management Registers for Protected mode
 Eight Debug Registers

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80486 Basic Features
 The 80486 is a 32 bit microprocessor.
 One of the most obvious feature included in 80486 is a built-in math
co-processor. Which is same as 80387 used with a 80386.
 80486 have 8KB code and data cache.
 80486 packaged in a 168 pin, Pin grid array package.
 80486 integrated Floating Point Unit(FPU) on chip.
 32 bit Extended general purpose register, Flag Register, address bus
and data bus.
 The Physical memory of 80486 is 32 bit wide which are set up as four 8
bit banks: bank0, bank1, bank2, bank3. and all bank contain one extra
parity bit.
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80486 Block diagram

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80486 Pin Diagram

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Pentium Processor basic features
 The Pentium microprocessor is 32 bit processor and almost identical to
the earlier 80386 and 80486 microprocessors.
 It introduces second execution pipeline to achieve superscalar
performance and execute two instruction per clock cycle using two
independent ALU named ‘U’ and ‘V’. It has Two core execution unit.
 The main difference is that the Pentium has been modified internally to
contain a dual cache of 16KB (code 8KB and data 8KB) and a dual
integer unit.
 The Pentium also operates at a higher clock speed of 66 MHz.
 The data bus on the Pentium is 64 – bits wide and contains eight
8 byte-wide memory banks selected with bank enable signals.
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Pentium Processor basic features
 Memory access time, without wait states, is only about 18 ns in the 66
MHz Pentium.
 The superscalar structure of the Pentium contains three independent
processing units: a floating point processor and two integer processing
units.
 A new mode of operation called the System Memory Management
(SMM) mode has been added to the Pentium. It is intended for high-
level system functions such as power management and security.
 The Built-in Self-test (BIST) allows the Pentium to be tested when power
is first applied to the system.
 Allows 4MByte memory pages instead of the 4KByte pages
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Pentium Processor basic features
 Pentium Processor have:
 Superscalar Architecture
 Dynamic Branch prediction
 Pipelined floating point unit
 Separate code and data caches
 64-bit data bus
 Bus cycle pipelining
 Address parity
 Internal Parity Checking

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Pentium Processor Functional Block diagram

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Pentium Processor Pin Diagram

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ARM vs. Intel Processors: Side-by-Side Comparison

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Thank You