« ] ) Darshan Unit 8- Advanced Microprocessor 80286 6. Describe the architecture of the 80286 with a neat block diagram. 1 ADORESS UNIT (AU) t Aaa-ho, VERS HE, io PROCESSOR] LL EACK INTERFACE READY, [SEoWeNT] uM JcnecKen| OER HLA Dis-Do "QUEUE J reser — ck ' [— vss INSTRUCTION : UNIT qu) EXECUTION UNIT EU) intr ERROR Figure: Architecture of Intel 80286 ‘+ The 80286 was designed for multi-user systems with multitasking applications, including communications and real-time process control. ‘* These were organized into a pipeline, significantly increasing performance. ‘© It was produced in a 68-pin package including PLCC (Plastic Leaded Chip Carrier). LCC (Leadless chip carrier) and PGA (Pin Grid Array) packages. ¢ The Intel 80286 had a 24-bit address bus and was able to address up to 16 MB of RAM, compared to 1 MB for its predecessor. 80286 Architecture contains 4 separate processing units. 1, Bus Unit (BU) 2. Instruction Unit (IU) 3. Address Unit (AU) 4, Execution Unit (EU) Bus Unit (BU It has address latches, data transceivers, bus interface and circuitry, instruction pre-fetcher, processor extension interface and 6 byte instruction queue. Functions : = To perform all memory and 1/0 read and write. - Topre-fetch the instruction bytes. Prof-SwatiR. Sharma, CE Dept. | 2150707 - Microprocessor and Interfacing 11Darshan Unit 8- Advanced Microprocessor - To control the transfer of data to and from processor extension devices like 80287 math co- processor. - Whenever BU is not using the buses for the operation, it pre-fetches the instruction bytes and put them is a 6 byte pre-fetch queue. Instruction Unit (IU): It has 3 decoded instruction queue and instruction decoder. Functions : - It fully decodes up to three prefetched instructions and holds them in a queue. - So that EU can access them. - _ Ithelps the processor to speed up, as pipelining of instruction is done. Execution Unit (El It includes ALU, registers and the Control unit. Registers are general purpose, index, pointer, flag register and 16 bit Machine Status Word (MSW), Functions - To sequentially execute the instructions received from the instruction unit. - ALU result is either stored in register bank or sent over the data bus. Address Unit (AU): It consists of segment registers, offset address and a physical address adder. Functions : - Compute the physical address that will be sent out to the memory or I/O by BU. - 80286 operate in two different modes 1. real address mode 2. Protected virtual address mode. - When used in Real address mode, AU computes the address with segment base and offset like 8086. Segment register are CS, DS, ES and SS hold base address. IP, BP, SI, DI , SP hold offset. - Maximum physical space allowed in this mode is 1MB. - When 80286 operate in protected mode, the address unit acts as MMU. ~ All 24 address lines used and can access up to 16MB of physical memory. - If descriptor table scheme is used it can address up to 1GB of virtual memory. 7. Explain Register Organization of 80286 1. Eight 16-bit general purpose registers (AX, BX, CX, DX, SP, BP, SI, Dl) 2. Four 16-bit segment registers (CS, SS, DS, ES) 3. 16-bit Instruction Pointer (IP) a 5. 16-bit Flag Register Plus ‘one new 16-bit machine status word (MSW) register Prof.swati R. Sharma, CE Dept. | 2150707 - Microprocessor and Interfacing 12© Darshan Unit 8- Advanced Microprocessor ‘Special MuLTPLYpMiDE NO INSTRUCTON LOOPISHIFTREPEAT COUNT BASE REGISTERS INDEX REGISTERS STACK POINTER, 15 ocnera 9 5 ° REGISTERS 8 ° cs| CODE SEGMENT SELECTION F STATUS WORD ps} DATASEGNENT SELECTON IP INSTRUCTION POWTER ss| STACK SEGMENT SELECTION 'STATUSAND CONTROL 5s) EXTRA SEGMENT SELECTION recrernhe SEGMENT REGISTERS. Figure: 80286 Register Set 80286 Flag Register s[fs|z]nfiofo]e]7]s]s]a]s]2[2]0 v fur] sort Jor |or| [re] se] zr] v far] u || w [er Figure: 80286 Flag Register - Flag register is of 32-bit, 15" bit undefined/reserved. - System flags: reflect the current status of machine. i, 10PL-1/0 Privilege Level flag: 2 ~bits are used in protected mode. It holds the privilege level from 0 to 3. ‘0’ assigns to highest privilege whereas ‘3’ assigns to lower privilege level. ii, NT: Nested Task flag: It is used in protected mode. Bit is set when one task invokes another task. Machine Status Word (MSW) Register 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22| 21/20) 19 ss |27 16 wp | Pe CMA Protected Mode Enable Pi ; Places 80286 in protected mode It can be only cleared by resetting CPU Prof.Swati R. Sharma, CE Dept. | 2150707 lcroprocessor and Interfacing 13Darshan Unit 8- Advanced Microprocessor Task Switch TS is automatically set whenever a task switch operation is performed. Monitor processor extension If set, this flag allows WAIT instruction to generate a processor extension not present exception EMulate processor extension flag If set, The EMulate coprocessor bit is set to cause all coprocessor opcodes to generate a Coprocessor Not Available fault. Instructions used to load and store MSW: 1. LMSW instruction (Load Machine Status Word) 2. SMSW instruction (Store Machine Status Word) 8. Differentiate between the real mode and protected mode of an 80286 microprocessor. Real Mode ‘* Address Unit computes the address with segment base and offset like 8086. ‘Maximum physical space allowed in this mode is 1MB. ‘* When 80286 get reset, it always starts execution in real mode. Task carried out in Real Mode ‘Initializes IP and other registers of 80286 Initializes the peripheral Enables interrupts Set up the descriptor table Prepares for entering in PVAM(Protected Virtual Address Mode) Protected Virtual Address Mode (PVAM) ‘© 80286 is the 1* processor to support the concept of Virtual memory and Memory management. Here, the address unit acts as MMU. ‘* All 24 address lines are used and can access up to 16MB of physical memory. © If descriptor table scheme is used it can address up to 1GB of virtual memory. Task carried out in PVAM ‘* The complete virtual memory is mapped on to the 16Mbyte physical memory. ‘* Ifa program larger than 16Mbyte is stored on the hard disk and is to be executed by swapping sequentially as per sequence of execution. ‘© The huge programs are divided in smaller segments or pages arranged in appropriate sequence. Prof Swati R. Sharma, CE Dept. | 2150707— Microprocessor and interfacing 14@ Darshan Seinen emanat Unit 8- Advanced Microprocessor Real Address Mode Protected Virtual Address Mode Can only address 1 MB of system ‘Can address til 16MB of system memory and act as fast 8086. Memory Doesn't Supports the concept of Virtual Supports the concept of Virtual Memory Memory Real mode provides no support for rotected mode provides support for memory protection, multitasking, or | memory protection, multitasking, or code privilege levels code privilege levels Initially every processor isin Real Made | Microprocessor will Switch to this mode le Misw PE=0 by setting msw Pe-bit Address Calculation: Real Mode Figure: Real Mode Addressing * Total 1MB of Memory, divided among 16-segments with each of size 64kb, + 80286 reserves two fined ates fur System Initialization IVT (Interrupt Vector Table) IVT-1KB of Starting ‘00000H ~ 003FFH address ‘System Initialization FFFFOH — FFFFFH Prof-Swati R. Sharma , CE Dept. | 2150707 ~ Microprocessor and Interfacing 15& Darshan Sofie i Unit 8- Advanced Microprocessor Address Calculation: PVAM Pointer | Selector | Onset PHYSICAL MEMORY SEGMENT MEMORY, Physical OBERRNG Adgross Adder DESCRIPTOR . SEGMENT TABLE Segment Gase |< 24-bit DESCRIPTOR ‘adress c Figure: Physical Address Calculation in PVAM 80286 uses the 16-bit content of a segmentregister as a selector to address a des in the physical memory. The descriptor is a block of contiguous memory locations containing information of a segment, like segment base address, segment limit, segment type, privilege level, segment availability in physical memory descriptor type and segment. ‘+ Hardware reset is the only way to come out of protected mode 9. Whatis a descriptor table? What GDT and LDT. Descriptor table usc? Differentiate between The descriptor is a block of contiguous memory location containing information of a segment, like Segment base address Segment limit Segment type iv. Privilege level - prevents unauthorized access v. Segment availability in physical memory vi. Descriptor type vii. Segment use by another task Prof.Swati R. Sharma , CE Dept. | 2150707 ~ Microprocessor and Interfacing 16