Digital Circuit Design

CHAPTER-3
Combinational Logic Circuits and Hazards

2.1 Motivation:
This chapter deals with combinational circuits. It also deals with combinational logic design using
MSI circuits, which is important for the design of digital digital systems considering the simplicity in
design, cost, space, power requirement and other factors.

3.2. Syllabus: -
Sr. No Topic Fine Detailing No of Week Self
Hours Study

03 Combinational Arithmetic Circuits: Adders/Subtractors:Half 12 3 25

Logic Circuits adder, Full adder, Half Subtractor, Full
and Hazards Subtractor, Ripple carry adder, Carry Look
ahead adder and BCD adder, Magnitude
Comparator
Multiplexer and De-multiplexer: Multiplexer,
cascading of Multiplexer, Boolean Function
implementation using single multiplexer and
basic gates, De-multiplexer, encoder and
decoder, Parity Circuits, ALU
Hazards: Timing hazards static and dynamic
3.3. Books Recommended:
1. Morris Mano, Digital Design, Pearson Education, Asia 2002.
2. R.P.Jain, Modern Digital Electronics, Tata McGraw Hill Education, Third Edition 2003.
3. John F. Wakerly, Digital Design Principles and Practices, Pearson Education, Fourth Edition,
2008.

3.4. Weightage in University Examination: 30-40 Marks

3.5. Objectives:
● To list the different conmbinational circuits.
● To teach the working of combinational circuits and their applications.

3.6 Key Notations:

MUX – Multiplexer

DEMUX - Demultiplexer

3.7 Key Definitions:

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Combinational Circuit - A circuit whose output depends on present input

Multiplexer: A device that selects one of several analog or digital input signals and forwards the
selected input into a single line.
Demultiplexer : A device that takes a single input line and routes it to one of several digital output
lines

3.8.1 Introduction:
Combinational logic circuits (circuits without a memory): Combinational switching networks whose
outputs depend only on the current inputs.
A combinational circuit consists of input variables, logic gates and output variables. The logic gates
accept signals from the input variables and generate output signals. This process transforms binary
information from the given input data to the required output data. Figure 3.1 shows the block
diagram of a combinational circuit. As shown in the figure the combinational circuit accepts n input
binary variables and generates m output variables depending on the logical combination of gates

Fig. 3.1 Combinational logic circuits

Most important standard combinational circuits are:
• Adders
• Subtractors
• Comparators
• Decoders
• Encoders
• Multiplexers
Available in IC’s as MSI and used as standard cells in complex VLSI (ASIC)

Classification of Combinational Logic shown in fig.3.2

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Fig.3.2 Classification of Combinational Logic

One of the most common uses of combinational logic is in Multiplexer and De-multiplexer type
circuits. Here, multiple inputs or outputs are connected to a common signal line and logic gates
are used to decode an address to select a single data input or output switch. A multiplexer
consist of two separate components, a logic decoder and some solid state switches, but before
we can discuss multiplexers, decoders and de-multiplexers in more detail we first need to
understand how these devices use these "solid state switches" in their design

DESIGN OF COMBINATIONAL LOGIC

1. From the specifications of the circuit, determine the number of inputs and outputs
2. Derive the truth table that defines the relationship between the input and the output.
3. Obtain the simplified Boolean function using x-variable K-Map.
4. Draw the logic diagram and verify the correctness of the design

Half Adder
Half adder is a combinational logic circuit which is used to add two bits at a time and gives two
Outputs sum(s) and carry (c) Let A and B are two input variables.
Half adder is a logic circuit that finds the arithmetic sum of two binary digits at a time. Its logic
circuit is shown in Figure 3.3

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Fig.3.3 Half Adder

The outputs of the XOR and AND gates produces the sum and carry respectively

Fig.3.4: (a)K Map for Sum S (b)K Map for Carry C

The input variables of half adder are augend and addend. The output variables are sum and
carry. It is necessary to specify two output variables, because the sum of 1+1=10. Let A & B
be input variables SUM and CARRY be output variables.
The output ‘CARRY’ represents an AND function. The output SUM represents exclusive OR
function. The Boolean functions of the two outputs are
SUM = and CARRY = A . B

Full Adder
When two binary numbers are added a carry may be generated onto the subsequent bit
positions. Hence, it is required to add three bits for the subsequent additions. A
combinational circuit that finds the arithmetic sum of three bits is called a Full adder. A Full
adder can be constructed using two half adders and an OR gate as shown in the Figure 3.5.

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Fig.3.5 Full Adder
Thus a full-adder is a combinational circuit that performs the arithmetic sum of three input bits.
It consists of three inputs and two outputs. Two of the input variables denoted by A, B
represents the two significant bits to be added. The third input C represents the carry from the
lower significant position. The two outputs are denoted by SUM and CARRY. The Boolean
expressions for SUM and CARRY outputs are given below

Half Subtractor:
A Half subtractor is a combinational logic circuit which is used to find the difference between
two binary digits. Its logic circuit is shown in Figure 3.6
A half-subtractor has two inputs and two outputs. Let the input variables minuend and
subtrahend be designated as A and B respectively, and output functions be designated as D for
difference and B for borrow. The truth table of the functions is as follows

Fig. 3.6 Half Subtractor & Truth Table

Map for DIFFERENCE Map for BORROW

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DIFFERENCE = A'B + AB' BORROW = A'B

=
Fig. 3.7 Half Subtractor K map for Difference &Borrow
A half subtractor consists of two input variables A and B (minuend and subtrahend) and two
output variables DIFFERENCE and BORROW. The DIFFERENCE output is obtained by a 2-input
XOR gate. The BORROW output is obtained by the expression A'B
Hence DIFFERENCE = BORROW = A'B

Full Subtractor:
A full subtractor Figure 3.8 is a combinational circuit that performs a subtraction between
two bits taking into account that a 1 may have been borrowed by a lower significant stage.
A combinational circuit of full-subtractor performs the operation of subtraction of three
bits—the minuend, subtrahend, and borrow generated from the subtraction operation of
previous significant digits and produces the outputs difference and borrow.

Fig.3.8 Full Subtractor

This circuit has three inputs and two outputs. The three inputs A, B and C denote the
minuend, subtrahend and previous borrow respectively. The two outputs DIFFERENCE and
BORROW represent the difference and borrow, respectively. The truth table for the circuit is
as follows.

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A B C D BOROUT
BORIN
0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1

Fig. 3.9 Full Subtractor Truth Table

The Boolean functions for the two outputs of the full subtractor are derived in the K-map
as shown below.

Map for BORROW Map for DIFFERENCE

BORROW = A'C + A'B + B

Fig.3.10 Full Subtractor K Map for Borrow & Difference

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The Multiplexer:
A data selector, more commonly called a Multiplexer, shortened to "Mux" or "MPX", are
combinational logic switching devices that operate like a very fast acting multiple position rotary
switch. They connect or control, multiple input lines called "channels" consisting of either 2, 4, 8
or 16 individual inputs, one at a time to an output.

Then the job of a "multiplexer" is to allow multiple signals to share a single common output. For
example, a single 8-channel multiplexer would connect one of its eight inputs to the single data
output. Multiplexers are used as one method of reducing the number of logic gates required in a
circuit or when a single data line is required to carry two or more different digital signals.

Digital Multiplexers are constructed from individual analogue switches encased in a single IC
package as opposed to the "mechanical" type selectors such as normal conventional switches
and relays. Generally, multiplexers have an even number of data inputs, usually an even power
of two, n2 , a number of "control" inputs that correspond with the number of data inputs and
according to the binary condition of these control inputs, the appropriate data input is
connected directly to the output. An example of a Multiplexer configuration is shown below.

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Fig.3.11 [a]4-to-1 Channel Multiplexer[b]4 Channel Multiplexer using Logic Gates

[c]Multiplexer Symbol

Fig.3.12 [d]4-to-2 Channel Multiplexer

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Here in this example the 4 input channels are switched to 2 individual output lines but larger
arrangements are also possible. This simple 4 to 2 configuration could be used for example, to
switch audio signals for stereo pre-amplifiers or mixers.

The Multiplexer is a very useful combinational device that has its uses in many different
applications such as signal routing, data communications and data bus control. When used with
a demultiplexer, parallel data can be transmitted in serial form via a single data link such as a
fibre-optic cable or telephone line. They can also be used to switch either analogue, digital or
video signals, with the switching current in analogue power circuits limited to below 10mA to
20mA per channel in order to reduce heat dissipation.
It is possible to make simple multiplexer circuits from standard AND and OR gates as we have
seen above, but commonly multiplexers/data selectors are available as standard I.C. packages
such as the common TTL 74LS151 8-input to 1 line multiplexer or the TTL 74LS153 Dual 4-input
to 1 line multiplexer. Multiplexer circuits with much higher number of inputs can be obtained by
cascading together two or more smaller devices.

Digital multiplexers are sometimes also referred to as "Data Selectors" as they select the data to
be sent to the output line and are commonly used in communications or high speed network
switching circuits such as LAN´s and Ethernet applications. Some multiplexer IC´s have a single
inverting buffer (NOT Gate) connected to the output to give a positive logic output (logic "1",
HIGH) on one terminal and a complimentary negative logic output (logic "0", LOW) on another
different terminal.
MUX IC:

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Fig.3.13: MSI -IC-74151(8:1)MUX

A strobe control ‘ E’ ’ acts as an enable signal. The function table specifies the value of output ‘Y’
as function of the selection lines. Output ‘ Y’ ’ is the complement of ‘Y’. for proper operation, the
strobe input ‘ E’ ’ must be connected to ground.

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.
Fig.3.14:MSI -IC-74151(8:1)MUX-Functional Table

Multiplexer is a combinational ckt. that is one of the most widely used in digital design. The
multiplexer is a data selector which gates one out of several i/ps to a single o/p. It has n data
i/ps & one o/p line & m select lines where 2m = n. Depending upon the digital code applied
at the select inputs one out of n data input is selected & transmitted to a single o/p channel.
Normally strobe(G) input is incorporated which is generally active low which enables the
multiplexer when it is LOW. Strobe i/p helps in cascading no. of ICs that are available such as
74157, 74158(Quad 2:1 mux), 74352, 74153 (dual 4:1 Mux.), 74151A, 74152 (8:1 Mux.),
74150 (16:1 Mux). IC 74151A is a 8 : 1 multiplexer which provides two complementary o/ps
Y & Y´. The o/p Y is same as the selected i/p & Y´ is its complement. Then any multiplexer
can be used to realize any m variable function. (2m= n, m is no. of select inputs).

The Demultiplexer:

The data distributor, known more commonly as a Demultiplexer or "Demux", is the exact
opposite of the Multiplexer. The demultiplexer takes one single input data line and then
switches it to any one of a number of individual output lines one at a time. The
demultiplexer converts a serial data signal at the input to a parallel data at its output lines as
shown below.

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Fig.3.15: [a]1-to-4 Channel De-multiplexer[b] 4 Channel Demultiplexer using Logic Gate [c]
Demultiplexer Symbol

Standard Demultiplexer IC packages available are the TTL 74LS138 1 to 8-output demultiplexer,
the TTL 74LS139 Dual 1-to-4 output demultiplexer or the CMOS CD4514 1-to-16 output
demultiplexer. Another type of demultiplexer is the 24-pin, 74LS154 which is a 4-bit to 16-line
demultiplexer/decoder. Here the individual output positions are selected using a 4-bit binary
coded input. Like multiplexers, demultiplexers can also be cascaded together to form higher
order demultiplexers.

Unlike multiplexers which convert data from a single data line to multiple lines and
demultiplexers which convert multiple lines to a single data line, there are devices available
which convert data to and from multiple lines and in the next tutorial about combinational logic
devices, we will look at Encoders which convert multiple input lines into multiple output lines,
converting the data from one form to another.

Demultiplex means one into many. Input and many outputs. By applying control signals, we can steer
the input signal to one of the output lines. The block diagram of a simple is as shown below:

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A0–A2 Address Inputs, E1–E2 Enable Inputs,E3 Enable Input,O0–O7(Y0-Y-7) Outputs

Fig.3.16:MSI -IC-74138(1:8)DE-MUX

Functional Table:

Fig.3.17:MSI -IC-74138(1:8)DE-MUX-Functional Table

Demux takes single i/p & distributes it over several o/ps. It has one data line, n o/p lines & m
select lines where 2 m = n. MSI ICs available in TTL family for demux. are 74138(3 line to 8 line
decoder/demux.), 74139(dual 2 to 4 line decoder/driver.), 74154(4 to 16 line decoder/
demux), 74155(dual 2 to 4 line decoder) etc. IC 74155 is a dual 2 to 4 line decoder. It has two
sets of active low outputs1Y0 to 1Y3 & 2Y0 to 2Y3. A & B are the select terminals common
for both the demux. C1, C2 & G1, G2 are the data lines& strobe (enable) inputs for the two
demux. C1 is active high, C2,G1, G2 are active low. The two 2 line to 4 line demux. can be
combined to implement 3 line to 8 line demux.

The Magnitude Comparator:

Magnitude Comparator compares two binary data signals A & B and generates the results of
comparison in form of three output signals A>B, A=B, A<B. IC 7485 is a 4-bit comparator. The
cascade inputs A>B, A=B, A<B can be used to construct a comparator comparing more than 4
bits. The compare outputs depend on both compare i/ps as well as cascade i/ps.

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Fig.3.18 : (a)Comparator using Ex-OR gate(b)7485 TTL 4-bit comparator Pin Diagram

Fig.3.19: IC7485 TTL 4-bit comparator logic symbols

The truth table :- The action of the entries A > B, A < B and A = B.

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Fig.3.20: IC7485 TTL 4-bit comparator truth table

1. If it is wished that the exit A = B pass to state 1 each time the two binary numbers are
equal, it is enough to carry the entry A = B to state 1, the state of entries A < B and A > B
not having then importance.
2. If it is wished that the exit A > B also pass to state 1 if the two binary numbers are equal,
it is enough to carry the entry A > B to state 1 and to carry the entries A < B and A = B to
state 0.
3. In this configuration of the state of the entries A > B, A < B and A = B, exit A > B is with
state 1 when binary number A is higher than the binary number B or when these two
numbers are equal. It thus indicates if A > B.
4. In the same way, while carrying entry A < B with state 1 and entries A > B and A = B with
state 0, the exit A < B indicates binary number A is lower or equal to the binary number
B.

Decoders:
A decoder is a logic circuit that reads a binary value represented on a set of inputs and
activates one of the outputs that corresponds to the binary value. For N inputs there will be
2N outputs. Only one output can be active at any given time
Decoder vs. DEMUX
3-8 decoder: 3 data inputs, 8 outputs
1-8 DEMUX: 1 data input, 3 control inputs, 8 outputs
Add enable control bit to decoder:
e = 0: all outputs are 0
e = 1: behaves like regular decoder

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Data inputs of a decoder correspond to the control bits of a DEMUX
Enable input of a decoder corresponds to the data bit of a DEMUX

Fig.3.21: IC74138 as Decoder

Fig.3.22: IC74138 as Decoder- Internal Diagram &Truth Table

Features:

1. Demultiplexing capability
2. Multiple input enable for easy expansion
3. Complies with JEDEC standard no. 7A
4. ideal for memory chip select decoding
5. Active LOW mutually exclusive outputs
6. ESD protection:
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
7. Multiple package options
8. Specified from −40 C to +85 C and from −40 C to +125 C

Encoders:
An encoder is a logic circuit that produces a binary value output based upon the active input
(s). For 2N inputs there will be N outputs. A standard encoder circuit allows one input to be
active at a time. Priority encoders allow multiple inputs to be activated and will generate an
output code based upon the highest numbered input.

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for example. Here, we could use an 8-to-3 Encoder. The 74HC148 encoder is one chip that will do
the trick

Fig.3.23:IC74148 as Encoder
Here, inputs 0-7 are the input signals -- again, these are Active-LOW. The chip encodes the input
into a 3digit output, A0 (1's bit), A1 (2's bit), and A3 (4's bit).
EI enables the inputs. When it is LOW, the chip works properly. When it's HIGH, all outputs
are set to HIGH regardless of the input. EO and GS are outputs that we can ignore for now.
The encoder and decoder chips allow us to maximize the use of inputs and outputs. Since
the RCX has only 3 of each, it's handy to be able to get more than 3 pieces of information
back and forth at any one time.

3.9 Objective Questions

Q.1] Implement following function using 4:1MUX with active low strobe (E=0) in put
F(A,B,C,D)=∑M(2,3,5,7,9,12,13,14,15)
Q.2 ] Implement Full Subtractor using decoder IC 74138 and 2 input NAND gate IC7400
Q.3] Compare MUX and DEMUX w.r.to parameters ;write applications of MUX and DEMUX
Q.4] Design 8 bit comparator using IC 7485
Q.5] Implement Full Adder using IC74151(8:1MUX)
Q.6] Compare Encoder and Decoder w.r.to parameters ;write applications of Encoder and Decoder
3.10 Short Questions
Q.1] What is the difference between a Half Adder & a Full Adder? Implement Full Adder using
Half Adder
Q.2] Implement the following function Using 4:1MUX with active low strobe in put
[1]F(A,B,C,D)=∑(2,3,5,7,8,9,12,13,14,15) [2]implement Full Adder using two 4:1 MUX
Q.3] What is the difference between Half Subtractor &Full Subtractor? Implement Full Subtractor
using Half Subtractor
Q.4] Design the circuit for 4 bit combinational incrementer [circuit adds 4 one to 4 bit binary
number) using 4 Half Adders
Q.5] Design &Explain 8 bit binary Adder Using IC 7483
Q.6] Explain comparator chip IC7485 &working of IC 7485
Q.7] Explain the feature of IC 74138(1:8DE-MUX); Implement the full subtractor using 1:8
DEMUX

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3.11 Long Questions

Q.1] What is the difference between Half Adder & A Full Adder? Implement Full Adder using Half
Adder
Q.2] Implement the following function Using 4:1MUX with active low strobe in put
[1]F(A,B,C,D)=∑(2,3,5,7,8,9,12,13,14,15) [2]implement Full Adder using two 4:1 MUX
Q.3] What is the difference between Half Subtractor &Full Subtractor? Implement Full Subtractor
using Half Subtractor
Q.4] Design the circuit for 4 bit combinational incrementer [circuit adds 4 one to 4 bit binary
number) using 4 Half Adders
Q.5] Design &Explain 8 bit binary Adder Using IC 7483
Q.6] Explain comparator chip IC7485 &working of IC 7485
Q.11] Explain the feature of IC 74138(1:8DE-MUX);Implement the full subtractor using 1:8
DEMUX

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