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Digital Switching Principles

Article · November 2000

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 Digital Switching
Principles

Dr. Luis Orozco-Barbosa

University of Ottawa

What is it all about?

• How do we move traffic from one part of the network to
another?
• Connect end-systems to switches, and switches to each
other
• Data arriving to an input port of a switch have to be moved
to one or more of the output ports

Sw/2

1
 Switching
• Definition:
Switching is the property of varying the path followed by
the information being transferred through a network.
C
B

A 3

1 2

5
D
4

Sw/3

Types of switching elements

• Telephone switches
– switch samples
• Datagram routers
– switch datagrams
• ATM switches
– switch ATM cells

Sw/4

2
 Classification
• Packet vs. circuit switches
– packets have headers and samples don’t
• Connectionless vs. connection oriented
– connection oriented switches need a call setup
– setup is handled in control plane by switch controller
– connectionless switches deal with self-contained
datagrams
Conne ctionle s s Conne ction-orie nte d
(route r) (s witching s yste m )
P a cke t Inte rne t route r ATM s witching s yste m
s witch
Circuit Te le phone switching
s witch s ys te m
Sw/5

Other switching element functions

• Participate in routing algorithms
– to build routing tables
• Resolve contention for output trunks
– scheduling
• Admission control
– to guarantee resources to certain streams
• Here we focus on pure data movement

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3
 Requirements
• Capacity of switch is the maximum rate at which it can
move information, assuming all data paths are
simultaneously active
• Primary goal: maximize capacity
– subject to cost and reliability constraints
• Circuit switch must reject call if can’t find a path for
samples from input to output
– goal: minimize call blocking
• Packet switch must reject a packet if it can’t find a buffer
to store it awaiting access to output trunk
– goal: minimize packet loss
• Don’t reorder packets
Sw/7

A Generic Switch

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4
Space vs. Time Division Switching
• Modern digital switching systems rely on
intelligent control of space and time-division
elements.
• Space Division Switching
• Time Division Switching

Sw/9

Space Division Switching

• Each connection requires the establishment of physical path
through the switch that is dedicated solely to the transfer of
signals between the endpoints.

• Crossbar switch is the simplest space switch configuration:

– The crossbar is said to perform concentration,
distribution, or expansion according as n > m, n = m,
or n < m.

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5
 Crossbar Switch
• Simplest possible space-division switch

Sw/11

Crossbar Switch
• The crossbar switch has a number of limitations or
disadvantages:
– The number of crosspoints grows with n2. This is costly for
large n, and results in high capacitive loading on any
message path.
– The loss of crosspointd prevents connection between the
two points involved.
• The crosspoints are inefficiently utilized (at most n out of n2)

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6
 Time-division Switching
• Time-division switching involves the partitioning of a lower
speed data stream into pieces that share a higher speed data
stream with other data pieces.
• The individual pieces or slots are manipulated by the control
logic to route data from input to output.
• Three concepts are essential to the technique of time-division
switching:
• TDM bus switching
• Time-slot interchange (TSI)
• Time-multiplex switching (TMS)

Sw/13

TDM Bus Switching

• TDM is a technique that allows multiple signals to share a
single transmission line by separating them in time.
• Synchronous TDM is a technique in which time slots are
preassigned so that few or no overhead bits are required.

frame
1 n 1

n inlets n outlets

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7
 TDM Bus Switching (cont’d)
• Main design objective:
– to permit multiple low-speed streams to share a high-
speed line.
• Advantage:
– this technique permits multiple channels of data to be
handled efficiently within switching systems.

Sw/15

TDM Bus Switching (cont’d)

• Implementation:
– For n devices, the TDM
bus switch requires 2n n inlets
gates or switch points.
• Operation:
– Step 1. A set of inputs are
sampled in turn.
– Step 2. The samples are
n outlets
organized serially into
slots (channels) to form a
recurring frame of n slots.
• A Slot may be a bit, a byte,
or some longer block.
TDM bus switching
Sw/16

8
 Synchronous TDM
• Implementation Issue:
This logic can be simplified if the input information into a
time slot contains destination address information. All
outputs devices can then always connect to the bus and
copy the information from time slots with their address.
• This latter mechanism can be implemented by:
– Time-slot interchange (TSI)

Sw/17

Time-slot Interchange
• A time-slot interchange (TSI) operates on a synchronous
TDM stream of time slots, or channels, by interchanging pairs
of slots to achieve full-duplex operation.

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9
 Time-slot Interchange (cont’d)
• Step 1: The input lines of n devices are passed through a
synchronous multiplexer to produce a TDM stream with n
slots.
• Step 2. An incoming TDM frame is written sequentially,
slot by slot, into the data store.
• Step 3. An outgoing TDM frame is created by reading
slots from memory in an order dictated by an address store
that reflects the existing connections.

Sw/19

Time-slot Interchange (cont’d)

• Implementation Issues:
– A TSI can be integrated as part of a switch, or it may be
implemented remotely, as a device clustering
mechanism.

– A random-access data store whose width equal one

time slot of data and whose length equals the number of
slots in a frame is used.

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10
 Operation of TSI store
Example:
Assuming that the
following connections
exist: 1-2, 3-7 and 5-8.

Read/write process:
During the first time slot,
data are stored in location
1 and read from location
2. During the second time
slot, data are stored in
location 2 and read from
location 1. And so on.
Sw/21

TSI operation - variable-rate input

Implementation: 1 1
Use a selector 2
. .
2
. SEL SEL ..
device. This device .
will select an input M M

based on a channel
assignment provided
by a control memory.
In this way, more Data Store
slots can be assigned Address
Time-slot
to some inputs. Channel Counter Store
Assignment
Store

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11
 Time-slot Interchange
• Drawbacks:
– TSI can support only a limited number of connections.
• Example: For 24 sources operating at 64 kbps each, and a slot size
of 8 bits, we have an arrival rate of 192000 slots per second. For
each time slot, both a read and write are required, Thus memory
access time would need to be 1/(192000 x 2), or about 2.6 µs.
– The delay at the TSI grows as the size of the unit grows for
a fixed access speed.
• Solution:
– use multiple TSI units interconnected by a space switch.
This architecture is known as time-multiplexed switching
(TMS)

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Time-Multiplexed Switching
Example : A two-stage switch.

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12
 Multiple-stage Switches
• This type of arrangements has several advantages over the
simple crossbar switch:
– the number of crosspoint is reduced, increasing crossbar
utilization
– there is more than one path through the network to connect
two endpoints, increasing reliability.
• Drawback:
– a multistage network requires a more complex control
scheme, i.e., a free path through the stages must be
determined and the appropriate gates opened.

Sw/25

Clos Switch
1.The input lines are broken up into N/n groups of n lines.
2.Each group of lines goes into a first-stage matrix.
3.The outputs of the first stage matrices become inputs to a group
of second stage matrices, and so on.

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13
 Paull’s Matrix
Columns
1 2 · · · b · · · n
1

2
Rows .
.
.

.
.
.

Sw/27

Paull’s Matrix (cont’d)

1. Each row can have at most n symbols, since there can be at most as
many paths through a first stage array as there are inputs to that array.
2. Each column can have at most n symbols, since there can be at most as
many paths through a third stage array as there are outputs to that array
3. The sysmbols in each row must be distinct, since we have only 1 edge
from the first stage array to any second array, and we do not allow
multi-casting to different third stage arrays from a second stage array.
Therefore, there can be at most k symbols.
4. The symbols in each column must be distinct, since we have only 1
edge between a second stage array and a third stage array and an edge
cannot carry signals from two different inputs. Therefore, there can be
at most k symbols.

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14
 Blocking
Blocking occurs when thje network is unable to connect two
stations because all possible paths between them are already in
use.
Exemple: Try to connect input 9 to either output 4 or 6

Sw/29

Non-blocking configuration
Clos Theorem (symmetric switch):
A Clos network is strict -sense non-blocking if and only if the number of
second stage arrays k ≥ 2n-1
Proof:
• Suppose we want to establish a connection from a vacant input of a first stage
array a and a vacant output of a third stage array b. We do so by putting a
symbol in the (a,b) entry in Paull’s connection matrix. Now there can be at
most n-1 distinct symbols in row a, because there are only n inputs to array a,
less one input which wants to make a new connection. For similar reason,
there can be at most n-1 distinct symbols in column b. Consider the worst case
when (n-1)+(n-1) symbols are all distinct. If we have 1 more second stage
array, in other words a total of 2n-1 second stage arrays, then we enter a
symbol in (a,b) while keeping all symbols in row a distinct, and all symbols in
column b distinct as well.
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15
Non-blocking configuration (cont’d)

Sw/31

Non-blocking configuration (cont’d)

Number of crosspoints, Nx, for a non blocking three stages switch:

Nx = 2N (2n -1) + (2n-1)(N/n)2

where:
N = total number of input lines (inlets)
n = number of lines per first-stage switch
k = number of second stage switches

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16
 Clos Switch
To optimize Nx, differentiate Nx wrt n and set the result to 0.
For large N, n → √N/2

Number Number of Crosspoints Number of Crosspoints

of Lines for Three-stage Switch Single-stage Switch

128 7680 16384

512 63488 262144
2048 516096 4.2 x 106
8192 4.2 x 106 6.7 x 107
32768 3.3 x 107 1 x 109
131072 2.6 x 108 1.7 x 1010

Sw/33

Rearrangeable Configuration
The Slepian-Duguid Theorem (symmetric case)
A three stage Clos network is rearrangeable non-blocking
if and only if k ≥ n.
Proof:
Suppose we want to establish a connection between arrays
and b. We shall first prove that if k ≥ n we must either
have:
1. A symbol which is not found in both row a and column b; or
2. There exists a symbol c in row a which is not found in column b,
and a symbol d in column b which is not found in row a .

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17
 Rearrangeable Configuration (cont’d)
If case 1 is not true, the k symbols must be found either in the row or the
column or both. Using the assumed condition on k, we have k > n-1. Now there
are at most n-1 symbols in row a. Hence there must be a symbol d in column b
not found in a. Using a symmetrical argument, there must be a symbol c in row
a not found in b.

If case 1 is true, then we place the unfound symbol in (a,b), thus completing the
connection without any rearrangements. Otherwise, we look at the row where d
appears in column b to see if the symbol c appears in that row.

If such symbol c is found, we check that column to see if a symbol d appears.

We continue the process alternately until we do not find a symbol c or d. The
rearrangement is facilitated by putting a symbol d in (a,b), an replacing all c
with d as well as all d with c in the chain. Obvioulsy, the four conditions for a
legitimate connection matrix is satisfied with such rearrangements.

Sw/35

Rearrangeable Configuration (cont’d)

Paull’s Theorem: (symmetric case)
The number of circuits that need to be rearranged is at most N/n.

Proof:
We look for a symbol c in the row for the symbol d that appears in column b.
Next, we start the chain from c in row a, instead of extending the chain from d
in column b. We now extend the two chains alternately, so that at each step,
the chains have lengths differing by at most one. When either one of the chain
cannot be grown further, we choose that chain for rearrangement.

In each step for which the length of both chains are increased by one, we visit
one new column. Hence there are at most n-2 steps in extending the chains.
(We subtract two because the initial c and d occupy two columns). Hence we
need at most n-1 rearrangements. (The initial c or d also has to be rearranged.)

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18
Rearrangeable Configuration (cont’d)
Example:
Process of rearrangement:

1 2 b n 1 2 b n
1 1
2 d c 2 c d

a c a c d
c d d c
n n

(a) Before (b) After

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Multiple-stage Time/Space Switches

Multiple-stage networks can be built up by concatenating TMS
and TSI stages. TMS stages, which move slots from one stream to
another, are referred to as S and TSI stages are referred to as T.
Systems are described by an enumeration of their stages.

Space-Time-Space Switch (STS) Sw/38

19
 Multiple-stage Time/Space Switches

Time-Space-Time Switch (TST)

Sw/39

References
• Joseph Hui, Switching and Traffic Theory for Integrated
Broadband Networks, Kluwer Academic Publishers,
Norwell, MA, 1990.
• Mischa Schwartz, Broadband Integrated Networks,
Prentice Hall, New Jersey, 1996.
• William Stallings, Data and Computer Communications,
Third Edition, Macmillan, New York , 1991.

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20

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