3.1.

8259 – PIC Intialization

–ICW and OCW
 Initialization of 8259
Before the 8259 accepts interrupts for 8086, 8259 must be initialized

Initialization of 8259 is compulsory

These commands are formed and put into a register like AL

Then using OUT instruction we send these commands from 8086 to 8259 through data bus
Commands: ICWs (initialization command words) and OCWs (operational command words)

Using these commands several properties such as Priority, Masking. Trigger Modes and most
importantly we inform the Vector numbers of all interrupts to 8259
Initialization of 8259
ICW1
● ICW1 is compulsory.

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 A7 A6 A5 1 LTIM ADI SNGL IC4

● The address bit A0 must be ‘0’ while giving the initialization control word 1 to the 8259 chip

● A7 to A5 (D7 to D5): the three MSBs ie D7 to D5 are required when interfaced with 8085. In case of 8086 these bits are not required for 8259
interfacing with 8086

● D4: This bit should always be kept at logic ‘1’

Initialization of 8259
ICW1:

LTIM (D3) : This bit is used to indicated the interrupts are to be level triggered or
edge triggered.
if D3 = 1 then IR0-IR7 are level triggered else they are edge triggered

ADI(D2) : This bit is again required for 8085 and not for 8086

SNGL (D1): This bit is used to indicate the 8259 is in single mode or cascaded
mode. If this bit is ‘1’, then 8259 is in single mode else it is in cascaded mode.
If in cascaded mode then ICW3 will be required

IC4 (D0): This bit indicates the requirement of ICW4

Initialization of 8259
ICW2
● ICW2 is compulsory
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 T7 T6 T5 T4 T3 A10 A9 A8

the address bit A0 must be 1 while giving the Initialization control word 2 to the 8259 chip4

T7 to T3 (D7 - D3): the five bits of ICW2 are used to indicate the interrupt type to be given to 8086 when an
interrupt occurs on a pin of 8259.
The last three bits to make the interrupt type 3 bits are taken as 000 for IR0 and 111 for IR7
Hence the interrupt type corresponding to a particular interrupt on 8259 pin is generated by taking the five bits
T7 to T3 and concatenated with the three bits 000 to 111

D2 to D0: These bits are not required when interfaced with 8086
Initialization of 8259
ICW3
Master Mode ICW3

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 S7 S6 S5 S4 S3 S2 S1 S0

Slave Mode ICW3

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 ID2 ID1 ID0

The Address bit A0 must be ‘1’ while giving the Initialization control word 3 to 8259 chip
ICW3 has a different structure for both master 8259 as well as slave 8259
Initialization of 8259
ICW3
for master, each of the bit is used to indicate whether a slave is
connected of the corresponding interrupt request (IR) pin or not.

A ‘1’ indicates that a slave is connected to the corresponding interrupt request pin, while
a ‘0’ indicates no slave is connected

For slave, the ICW3 contains the ID of the device. This is required for the slave to
compare when the acknowledgement is given by the processor, to realize whether the
acknowledgement is meant for the same slave or another slave.

The ID is provided by the master 8259 on receipt to acknowledgement from the

microprocessor on the cascaded pins
Initialization of 8259
ICW4
ICW4 is required when IC4 bit of ICW1 was made ‘1’
The address bit A0 must be ‘1’ while giving the initialization control word 4 to
8259 chip

D7-D5: the three MSB’s ie D7-D5 are not required for 8259 interfaced with 8086

SFNM(D4): This bit indicates whether the 8259 has to operate in SFNM mode or FNM mode.
If this bit is ‘1’, then 8259 has to operate in SFNM mode else FNM mode

BUF and M/S (D3): These bits are used to indicate whether 8259 is in buffered mode or not.
In case of buffered mode M/S indicate it’s a master or slave.
If Buf bit is ‘1’ and if M/S bit is 1, it indicates buffered master else buffered slave
Initialization of 8259

AEOI(D1): this bit indicates whether Automatic end of interrupt or normal end of
interrupt

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 SFNM BUF M/S AEOI Microprocessor

Microprocessor: This bit is used to indicated the 8259 is connected to 8085 or 8086.
If this bit is 1 then it is connected to 8086 else connected to 8085
Initialization of 8259
OCW1
A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0

The address bit A0 must be 1 while giving the operational control word 1 to 8259 chip
M7 to M0 (D7-D0): These bits indicate masking or unmasking of a particular interrupt
request IR0 - IR7 to 8259.

If a bit is set to 1, the corresponding interrupt is disabled or masked, else its enabled or
unmasked
 Initialization of 8259
OCW2

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 R SL EOI 0 0 L2 L1 L0

The address bit A0 must be 1 while giving the operational control word 2 to the 8259 chip

R, SL, EOI : These bits indicate different commands programming for 8259.
A Write command with A0 = 1 and D4 D3 = 00 is interpreted as OCW2. The R (Rotate),
SL (Select-Level), EOI bits control the Rotate and End Of Interrupt Modes and combinations of the
two.

L2 to L0 : these bits are used to indicate the level or the interrupt request IR0-IR7, when
selecting a particular command using the bits D7-D0.

Example: If the command is specific EOI command, then I2-I0 specify the interrupt level
for which it is specific EOI.
For certain commands like non-specific EOI, the bit D2 to D0 are not required
Initialization of 8259
OCW2
Initialization of 8259
OCW3
Initialization of 8259
OCW3

A0 must be 0

D7-D4: always 0

ESMM and SMM (D6 and D5): used to enable or disable the Special Mask Mode

D3: always 1

P(D2): This bit is used to indicate giving of poll command from 8259

RR and RIS (D1-D0): these bits are used to indicate 8259 that the processor wants to read the register IRR or InSR