CS49400 Family DSP

Multi-Standard Audio Decoder

Features Description

CS49300 Legacy Audio Decoder Support The CS49400 Audio Decoder DSP is targeted as a market-

Dolby Digital EXTM, Dolby Pro Logic IITM specific consumer entertainment processor for AV Receivers

DTS-ES 96/24TM
TM, DTS 96/24TM, DTS-ES
TM
and DVD Audio/Video Players. The device is constructed using
an enhanced version of the CS49300 Family DSP audio
Discrete 6.1 , DTS-ES Matrix 6.1 , DTS decoder followed by a 32-bit programmable post-processor
Digital SurroundTM and DTS Virtual 5.1TM DSP, which gives the designer the ability to add product

MPEG-2: AAC Multichannel 5.1 differentiation through the Cirrus FrameworkTM programming

MPEG Multichannel and Musicam structure and Framework module library. Dolby Digital Pro

MPEG-1/2, Layer III (MP3) Logic II, DTS Digital Surround, MPEG Multichannel, and Cirrus

DTS Neo:6TM, LOGIC7®, SRS Circle Original Surround 6.1 PCM Effects Processor (capable of
generating such DSP audio modes as: Hall, Theater, Church)
Surround IITM are included in the cost of the CS49400 Family DSP. Additional

Cirrus Extra SurroundTM, Cirrus Original algorithms available through the Crystal WareTM Software
Surround 6.1 (C.O.S. 6.1)TM Licensing Program, give the designer the ability to further

THX Surround EXTM, THX Ultra2 CinemaTM deliver end-product differentiation.

12-Channel Serial Audio Inputs The CS49400 contains sufficient on-chip SRAM to support

Integrated 8K Byte Input Buffer decoding all major audio decoding algorithms available today

Powerful 32-bit Audio DSP including: AAC Multichannel, DTS 96/24, DTS-ES 96/24. The

Customer Software Security Keys CS49400 also supports a glueless SDRAM/SRAM for

Large On-chip X,Y, and Program RAM increased all-channel delays. The SRAM interface also

Supports SDRAM, SRAM, FLASH
supports connection to an external byte-wide EPROM for code
storage or Flash memory thus allowing products to be field-
memories upgradable as new audio algorithms are developed.

16-channel PCM output

Dual S/PDIF Transmitters This chip, teamed with Crystal WareTM certified decoder

SPI Serial, and Motorola® and Intel® Parallel

library, Cirrus digital interface products and mixed signal data
converters, enables the conception and design of next
Host Control Interfaces generation digital entertainment products.

GPIO support for all common sub-circuits
Ordering Information: See page 98

SAI 0
Serial External Memory
SAI 1
SAI 2
Audio Interface
SAI 3 Interface
Compressed
Digital
DSP C
Internal Bus

Digital DAO 0
Interface Frame Programmable Audio
Shifter Multi-Standard
Shared Memory

Digital 32-Bit DSP Output DAO 1

Audio Audio Decoder
Input GPIO and I/O
Controller
DSP AB DSP DSP
Input RAM ROM
PLL Clock Parallel or Serial Parallel or Serial
Buffer
Manager Host Interface Host Interface
RAM

This document contains information for a new product.

Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2002 JUL ‘02

P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
(512) 445 7222 FAX: (512) 445 7581
DS536PP2
http://www.cirrus.com
1
TABLE OF CONTENTS
1.0 CHARACTERISTICS AND SPECIFICATIONS ...................................................................... 8
1.1 Absolute Maximum Ratings ............................................................................................... 8
1.2 Recommended Operating Conditions ................................................................................ 8
1.3 Digital D.C. Characteristics for VDD Level I/O ................................................................... 8
1.4 Digital D.C. Characteristics for VDDSD Level I/O .............................................................. 9
1.5 Power Supply Characteristics ............................................................................................ 9
1.6 Switching Characteristics— RESET .................................................................................. 9
1.7 Switching Characteristics — CLKIN ................................................................................. 10
1.8 Switching Characteristics — Intel® Host Slave Mode (DSPAB) ...................................... 11
1.9 Switching Characteristics — Intel® Host Slave Mode (DSPC) ........................................ 13
1.10 Switching Characteristics — Motorola® Host Slave Mode (DSPAB) ............................ 15
1.11 Switching Characteristics — Motorola® Host Slave Mode (DSPC) .............................. 17
1.12 Switching Characteristics — SPI Control Port Slave Mode (DSPAB) ............................ 19
1.13 Switching Characteristics — SPI Control Port Slave Mode (DSPC) .............................. 21
1.14 Switching Characteristics — Digital Audio Input (DSPAB) ............................................ 23
1.15 Switching Characteristics — Serial Audio Input (DSPC) ............................................... 24
1.16 Switching Characteristics — CMPDAT, CMPCLK (DSPAB) ......................................... 25
1.17 Switching Characteristics — Parallel Data Input (DSPAB) ............................................ 26
1.18 Switching Characteristics — Digital Audio Output ......................................................... 27
1.19 Switching Characteristics — SRAM/FLASH Interface ................................................... 29
1.20 Switching Characteristics — SDRAM Interface ............................................................. 31
2. OVERVIEW ............................................................................................................................. 35

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm

Dolby Digital, Dolby Digital EX, AC-3, Dolby Pro Logic, Dolby Pro Logic II, Dolby Digital EX Pro Logic II, Dolby Surround, Dolby Surround Pro Logic
II, Surround EX, Virtual Dolby Digital and the “AAC” logo are trademarks and the “Dolby” and the double-”D” symbol are registered trademarks of
Dolby Laboratories Licensing Corporation. DTS, DTS Digital Surround, DTS-ES Extended Surround, DTS 96/24, DTS-ES 96/24, DTS Neo:6, and
DTS Virtual 5.1 are trademarks and the “DTS”, “DTS Digital Surround”, “DTS-ES”, “DTS 96/24”, “DTS-ES 96/24”, “DTS Neo:6”, “DTS Virtual 5.1” logos
are registered trademarks of the Digital Theater Systems Corporation. The “MPEG Logo” is a registered trademark of Philips Electronics N.V. THX
Ultra2 Cinema, Timbre-Matching, Re-EQ, Adapative Decorrelation and THX are trademarks or registered trademarks of Lucasfilm, Ltd. Surround EX
is a jointly developed technology of THX and Dolby Labs, Inc. AAC (Advanced Audio Coding) is an “MPEG-2-standard-based” digital audio
compression algorithm (offering up 5.1 discrete decoded channels for this implementation) collaboratively developed by AT&T, the Fraunhofer
Institute, Dolby Laboratories, and the Sony Corporation. In regards to the MP3 capable functionality of the CS494XX Family DSP (via downloading
of mp3_ab_494xxx_vv.uld application code) the following statements are applicable: “Supply of this product conveys a license for personal, private
and non-commercial use. MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and THOMSON Multimedia.” VMAx is a registered
trademark of Harman International. The LOGIC7 logo and LOGIC7 are registered trademarks of Lexicon. SRS CircleSurround, SRS Circle Suround
II, SRS TruSurround, and SRS TruSurround XT are trademarks of SRS Labs, Inc. The HDCD logo, HDCD, High Definition Compatible Digital and
Pacific Microsonics are either registered trademarks or trademarks of Pacific Microsonics, Inc. in the United States and/or other countries. HDCD
technology provided under license from Pacific Microsonics, Inc. This product’s software is covered by one or more of the following in the United
States: 5,479,168; 5,638,074; 5,640,161; 5,872,531; 5,808,574; 5,838,274; 5,854,600; 5,864,311; and in Australia: 669114; with other patents
pending. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc. I2C is a registered trademark of Philips
Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use those components in a standard I2C system. “Crystal Ware”, “Cirrus Framework”, “Cirrus Extra Surround”, “Cirrus
Triple Crossover Bass Management”, “Cirrus Quadruple Crossover Bass Management” and “Cirrus Original Surround 6.1” are trademarks and “Cirrus
Logic” is a registered trademarks of Cirrus Logic, Inc. All other names are trademarks, registered trademarks, or service marks of their respective
companies.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance
product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to
ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is
provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information,
nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents,
copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any
form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus
Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a
retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of
Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent
of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or
service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can
be found at http://www.cirrus.com.

2
 2.1 DSPAB ............................................................................................................................ 36
2.2 DSPC ............................................................................................................................... 36
3. TYPICAL CONNECTION DIAGRAMS ................................................................................... 37
3.1 Multiplexed Pins .............................................................................................................. 37
3.2 Termination Requirements .............................................................................................. 37
3.3 Phase Locked Loop Filter ................................................................................................ 37
4. POWER .............................................................................................................................. 38
4.1 Decoupling ....................................................................................................................... 38
4.2 Analog Power Conditioning ............................................................................................. 38
4.3 Ground ............................................................................................................................. 38
4.4 Pads ................................................................................................................................ 38
5. CLOCKING ............................................................................................................................. 42
6. CONTROL .............................................................................................................................. 42
6.1 Serial Communication ..................................................................................................... 42
6.1.1 SPI Communication for DSPAB .......................................................................... 42
6.1.2 SPI Communication for DSPC ............................................................................ 46
6.1.3 FINTREQ Behavior: A Special Case .................................................................. 49
6.2 Parallel Host Communication for DSPAB ........................................................................ 51
6.2.5 Intel Parallel Host Communication Mode for DSPAB ......................................... 51
6.2.6 Motorola Parallel Communication Mode for DSPAB ........................................... 54
6.2.7 Procedures for Parallel Host Mode Communication for DSPAB ......................... 56
6.3 Parallel Host Communication for DSPC .......................................................................... 58
6.3.5 Intel Parallel Host Communication Mode for DSPC ............................................ 60
6.3.6 Motorola Parallel Host Communication Mode for DSPC .................................... 64
6.3.7 Procedures for Parallel Host Mode Communication for DSPC ........................... 68
7. EXTERNAL MEMORY ............................................................................................................ 70
7.1 Configuring SRAM Timing Parameters ........................................................................... 71
8. BOOT PROCEDURE .............................................................................................................. 72
8.1 Host Controlled Master Boot ........................................................................................... 72
8.2 Host Boot Via DSPC ........................................................................................................ 75
9. SOFT RESETTING THE CS49400 ......................................................................................... 77
9.1 Host Controlled Master Soft Reset .................................................................................. 77
10. HARDWARE CONFIGURATION ......................................................................................... 79
11. DIGITAL INPUT AND OUTPUT DATA FORMATS .............................................................. 79
11.1 Digital Audio Formats .................................................................................................... 79
11.1.1 I2S ..................................................................................................................... 79
11.1.2 Left Justified ...................................................................................................... 79
11.2 Digital Audio Input Port .................................................................................................. 79
11.3 Compressed Data Input Port ......................................................................................... 80
11.4 Input Data Hardware Configuration for CDI and DAI on DSPAB ................................. 80
11.4.1 Input Configuration Considerations ................................................................ 81
11.5 Serial Audio Input .......................................................................................................... 82
11.6 Digital Audio Output Port ............................................................................................... 82
11.6.1 S/PDIF Outputs ................................................................................................. 83
11.7 Output Data Hardware Configuration ............................................................................ 84
11.8 Creating Hardware Configuration Messages ................................................................. 85
12.0 PIN DESCRIPTION ............................................................................................................. 87
12.1 144-Pin LQFP Package Pin Layout ............................................................................... 87
12.2 100-Pin LQFP Package Pin Layout ............................................................................... 88
12.3 Pin Definitions ................................................................................................................ 89
13. ORDERING INFORMATION ................................................................................................ 99
14. PACKAGE DIMENSIONS .................................................................................................. 100
14.1 144-Pin LQFP Package ............................................................................................... 100

3
LIST OF FIGURES
Figure 1. RESET Timing ..................................................................................................................... 9
Figure 2. CLKIN with CLKSEL = VSS = PLL Enable ........................................................................ 10
Figure 3. Intel® Parallel Host Mode Slave Read Cycle for DSPAB .................................................. 12
Figure 4. Intel® Parallel Host Mode Slave Write Cycle for DSPAB ................................................... 12
Figure 5. Intel® Parallel Host Slave Mode Read Cycle for DSPC ..................................................... 14
Figure 6. Intel® Parallel Host Slave Mode Write Cycle for DSPC ..................................................... 14
Figure 7. Motorola® Parallel Host Slave Mode Read Cycle for DSPAB ........................................... 16
Figure 8. Motorola® Parallel Host Slave Mode Write Cycle for DSPAB ........................................... 16
Figure 9. Motorola® Parallel Host Slave Mode Read Cycle for DSPC ............................................. 18
Figure 10. Motorola® Parallel Host Slave Mode Write Cycle for DSPC ............................................ 18
Figure 11. SPI Control Port Slave Mode Timing (DSPAB) ............................................................... 20
Figure 12. SPI Control Port Slave Mode Timing (DSPC) ................................................................. 22
Figure 13. Digital Audio Input Data, Slave Clock Timing .................................................................. 23
Figure 14. Serial Audio Input Data, Slave Clock Timing ................................................................... 24
Figure 15. Serial Compressed Data Timing ...................................................................................... 25
Figure 16. Parallel Data Timing ........................................................................................................ 26
Figure 17. Digital Audio Output Data, Input and Output Clock Timing ............................................. 28
Figure 18. Digital Audio Output Data, Input and Output Clock Timing ............................................. 28
Figure 19. SRAM/Flash Controller Timing Diagram - Write Cycle .................................................... 29
Figure 20. SRAM/Flash Controller Timing Diagram - Read Cycle .................................................... 29
Figure 21. SRAM/Flash Controller Timing Diagram - Single Byte Write Cycle ................................. 30
Figure 22. SRAM/Flash Controller Timing Diagram - Single Byte Read Cycle ................................ 30
Figure 23. SDRAM Controller Timing Diagram - Load Mode Register Cycle ................................... 31
Figure 24. SDRAM Controller Timing Diagram - Burst Write Cycle .................................................. 32
Figure 25. SDRAM Controller Timing Diagram - Burst Read Cycle ................................................. 33
Figure 26. SDRAM Controller Timing Diagram - Auto Refresh Cycle .............................................. 34
Figure 27. SPI Control with External Memory - 144 Pin Package .................................................... 39
Figure 28. Intel® Parallel Control Mode - 144 Pin Package .............................................................. 40
Figure 29. Motorola® Parallel Control Mode - 144 Pin Package ....................................................... 41
Figure 30. SPI Write Flow Diagram for DSPAB ................................................................................ 43
Figure 31. SPI Timing for DSPAB ..................................................................................................... 44
Figure 32. SPI Read Flow Diagram for DSPAB ................................................................................ 45
Figure 33. SPI Write Flow Diagram for DSPC .................................................................................. 46
Figure 34. SPI Timing for DSPC ....................................................................................................... 47
Figure 35. SPI Read Flow Diagram for DSPC .................................................................................. 48
Figure 36. Intel Mode, One-Byte Write Flow Diagram for DSPAB .................................................... 53
Figure 37. Intel Mode, One-Byte Read Flow Diagram for DSPAB ................................................... 54
Figure 38. Motorola Mode, One-Byte Write Flow Diagram for DSPAB ............................................ 55
Figure 39. Motorola Mode, One-Byte Read Flow Diagram for DSPAB ............................................ 55
Figure 40. Typical Parallel Host Mode Control Write Sequence Flow Diagram for DSPAB ............. 56
Figure 41. Typical Parallel Host Mode Control Read Sequence Flow Diagram for DSPAB ............. 57

4
Figure 42. Intel Mode, One-Byte Write Flow Diagram for DSPC .......................................................60
Figure 44. Intel Mode, One-Byte Read Flow Diagram for DSPC ......................................................61
Figure 43. Intel Mode, 32-bit (4-byte) Write Flow
Diagram for DSPC .............................................................................................................................62
Figure 45. Intel Mode, 32-Bit (4-Byte) Read Flow
Diagram for DSPC .............................................................................................................................63
Figure 46. Motorola Mode, One-Byte Write Flow
Diagram for DSPC .............................................................................................................................64
Figure 47. Motorola Mode, 32-bit (4-byte) Write Flow Diagram for DSPC ........................................65
Figure 48. Motorola Mode, One-Byte Read Flow
Diagram for DSPC .............................................................................................................................66
Figure 49. Motorola Mode, 32-Bit (4-Byte) Read Flow Diagram for DSPC .......................................67
Figure 50. Typical Parallel Host Mode Control Write Sequence Flow Diagram for DSPC ................68
Figure 51. Typical Parallel Host Mode Control Read Sequence Flow Diagram for DSPC ................69
Figure 52. Host Controlled Master Boot
(Downloading both a DSPAB Application Code and a DSPC Application Code) ..............................73
Figure 53. Host Boot Via DSPC .......................................................................................................76
Figure 54. Host Controlled Master Softreset .....................................................................................78
Figure 55. I2S Format ........................................................................................................................80
Figure 56. Left Justified Format (Rising Edge Valid SCLK) ...............................................................80
Figure 57. Pin Layout (144-Pin LQFP Package) ...............................................................................87
Figure 58. Pin Layout (100-Pin LQFP Package) ...............................................................................88
Figure 59. 144-Pin LQFP Package Drawing ...................................................................................100

5
LIST OF TABLES
Table 1. PLL Filter Component Values ...............................................................................................37
Table 2. Host Modes for DSPAB ........................................................................................................42
Table 3. Host Modes for DSPC ..........................................................................................................42
Table 4. SPI Communication Signals for DSPAB ...............................................................................43
Table 5. SPI Communication Signals for DSPC .................................................................................46
Table 6. Intel Mode Communication Signals for DSPAB ....................................................................51
Table 6. Parallel Input/Output Registers for DSPAB ..........................................................................52
Table 7. Motorola Mode Communication Signals for DSPAB.............................................................54
Table 8. Parallel Input/Output Registers for DSPC.............................................................................59
Table 9. Intel Mode Communication Signals for DSPC ......................................................................60
Table 10. Motorola Mode Communication Signals for DSPC .............................................................64
Table 11. SRAM Interface Pins ..........................................................................................................70
Table 12. SDRAM Interface Pins ........................................................................................................70
Table 13. SRAM Controller Timing .....................................................................................................71
Table 14. SDRAM Config Register .....................................................................................................71
Table 15. Application Messages from DSPAB ...................................................................................72
Table 16. Boot Write Messages for DSPC .........................................................................................72
Table 17. Boot Read Messages from DSPC ......................................................................................72
Table 18. Digital Audio Input Port .......................................................................................................80
Table 19. Compressed Data Input Port ..............................................................................................80
Table 20. Input Data Type Configuration
(Input Parameter A).............................................................................................................81
Table 21. Input Data Format Configuration
(Input Parameter B).............................................................................................................81
Table 22. Input SCLK Polarity Configuration
(Input Parameter C) ............................................................................................................81
Table 23. Serial Audio Input Port ........................................................................................................82
Table 24. SAI Data Type Configuration
(Input Parameter D) ............................................................................................................82
Table 25. Digital Audio Output Port ....................................................................................................82
Table 26. MCLK/SCLK Master Mode Ratios ......................................................................................83
Table 27. Output Clock Configuration
(Parameter A)......................................................................................................................84
Table 28. Output Data Configuration Parameter B)...........................................................................84
Table 29. Output SCLK/LRCLK Configuration
(Parameter C) .....................................................................................................................84
Table 30. Output SCLK Polarity Configuration
(Parameter D) .....................................................................................................................85
Table 31. Example Values to be Sent to DSPAB After Download or Soft Reset................................86
Table 32. Example Values to be Sent to DSPC After Download or Soft Reset ..................................86

6
1.0 CHARACTERISTICS AND SPECIFICATIONS
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and
temperature. Actual production testing is performed at TA = 25 °C with an appropriate guardband to
guarantee minimum and maximum timing specifications over rated voltage and temperature.

1.1 Absolute Maximum Ratings

(VSS, VSSSD, PLLVSS = 0 V; all voltages with respect to 0 V)
Parameter Symbol Min Max Unit
DC power supplies: Core supply VDD –0.3 2.7 V
PLL supply PLLVSS –0.3 2.7 V
Memory supply VDDSD –0.3 3.6 V
||PLLVDD| – |VDD|| - 0.3 V
Input current, any pin except supplies Iin - ± 10 mA
Digital input voltage on I/O pins powered from VDD Vind - 3.6 V
Digital input voltage on I/O pins powered from VDDSD Vinsd - 3.6 V
Storage temperature Tstg –65 150 °C

Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.

1.2 Recommended Operating Conditions

(VSS, VSSSD, PLLVSS = 0 V; all voltages with respect to 0 V)
Parameter Symbol Min Typ Max Unit
DC power supplies: Core supply VDD 2.37 2.5 2.63 V
PLL supply PLLVSS 2.37 2.5 2.63 V
Memory supply VDDSD 3.15 3.3 3.45 V
||PLLVDD| – |VDD|| 0.3 V
Ambient operating temperature TA 0 - 70 °C

1.3 Digital D.C. Characteristics for VDD Level I/O

(TA = 25 °C;VDD = 2.5 V; measurements performed under static conditions.)
Parameter Symbol Min Typ Max Unit
High-level input voltage VIH 2.0 - - V
Low-level input voltage VIL - - 0.8 V
High-level output voltage at IO = –2.0 mA VOH VDD × 0.9 - - V
Low-level output voltage at IO = 2.0 mA VOL - - VDD × 0.1 V
Input leakage current (all pins without internal pull- Iin - - 10 µA
up resistors except CLKIN)
Input leakage current (pins with internal pull-up 50 µA
resistors, CLKIN)

7
1.4 Digital D.C. Characteristics for VDDSD Level I/O
(TA = 25 °C;VDDSD = 3.3 V±; measurements performed under static conditions.)
Parameter Symbol Min Typ Max Unit
High-level input voltage VIH 0.65xVDDSD V
Low-level input voltage VIL 0.35xVDDSD V
High-level output voltage at IO = –2.0 mA VOH 0.9xVDDSD V
Low-level output voltage at IO = 2.0 mA VOL 0.1xVDDSD V
Input leakage current (except all pins with internal pull- Iin 10 µA
up)
Input leakage current (all pins with internal pull-up) 50 µA

1.5 Power Supply Characteristics

(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V;measurements performed under operating conditions)
Parameter Symbol Min Typ Max Unit
Power supply current: Core and I/O operating: VSS 400 mA
PLL operating: PLLVSS 6 mA
Memory operating: VSSSD 25 mA

1.6 Switching Characteristics— RESET

(TA = 25 °C; VDD, PLLVDD= 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
RESET minimum pulse width low Trstl 10 - µs
All bidirectional pins high-Z after RESET low Trst2z 50 ns
Configuration bits setup before RESET high Trstsu 50 - ns
Configuration bits hold after RESET high Trsthld 15 - ns

RESET

FHS0,1,2
UHS0,1,2

All Bidirectional
Pins T rstsu Trsthld
Trst2z
Trstl

Figure 1. RESET Timing

8
1.7 Switching Characteristics — CLKIN
(TA = 25 °C; VDD, PLLVDD = 2.5; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
CLKIN period for internal DSP clock mode Tclki 35 100 ns
CLKIN high time for internal DSP clock mode Tclkih 18 ns
CLKIN low time for internal DSP clock mode Tclkil 18 ns
External Crystal operating frequency Fxtal 10 14 MHz

CLKIN

Tclkih Tclkil
Tclki

Figure 2. CLKIN with CLKSEL = VSS = PLL Enable

9
1.8 Switching Characteristics — Intel® Host Slave Mode (DSPAB)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
Address setup before FCS and FRD low or FCS and FWR low Tias 5 - ns
Address hold time after FCS and FRD low or FCS and FWR Tiah 5 - ns
high
Read
Delay between FRD then FCS low or FCS then FRD low Ticdr 0 - ns
Data valid after FCS and FRD low Tidd - 21 ns
FCS and FRD low for read (Note 1) Tirpw DCLKP + 10 - ns
Data hold time after FCS or FRD high Tidhr 5 - ns
Data high-Z after FCS or FRD high Tidis - 22 ns
FCS or FRD high to FCS and FRD low for next read (Note 1) Tird 2*DCLKP + 10 - ns
FCS or FRD high to FCS and FWR low for next write (Note 1) Tirdtw 2*DCLKP + 10 - ns
Write
Delay between FWR then FCS low or FCS then FWR low Ticdw 0 - ns
Data setup before FCS or FWR high Tidsu 20 - ns
FCS and FWR low for write (Note 1) Tiwpw DCLKP + 10 - ns
Data hold after FCS or FWR high Tidhw 5 - ns
FCS or FWR high to FCS and FRD low for next read (Note 1) Tiwtrd 2*DCLKP + 10 - ns
FCS or FWR high to FCS and FWR low for next write (Note 1) Tiwd 2*DCLKP + 10 - ns
Notes: 1. Certain timing parameters are normalized to the DSP clock period, DCLKP. DCLKP = 1/DCLK. The
DSP clock can be defined as follows:

Internal Clock Mode:

DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns
DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns

It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.

10
 F A1:0
T ia h
F DAT A7:0
Tias
Tidhr
Tidd
F CS
T icdr Tidis
FWR
T irpw Tird T irdtw

F RD

Figure 3. Intel® Parallel Host Mode Slave Read Cycle for DSPAB

F A1:0
T iah
F DATA7:0
T ias
Tid hw
F CS
Ticdw Tidsu
F RD
T iw pw Tiw d Tiw trd

F WR

Figure 4. Intel® Parallel Host Mode Slave Write Cycle for DSPAB

11
1.9 Switching Characteristics — Intel® Host Slave Mode (DSPC)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
Address setup before CS and RD low or CS and WR low Tias DCLKP - ns
Address hold time after CS and RD low or CS and WR low Tiah DCLKP+15 - ns
Read
Delay between RD then CS low or CS then RD low Ticdr 0 - ns
Data valid after CS and RD low Tidd - 2*DCLKP+ ns
25
CS and RD low for read (Note 1) Tirpw 2*DCLKP - ns
Data hold time after CS or RD high Tidhr DCLKP+10 - ns
Data high-Z after CS or RD high Tidis - 2*DCLKP+ ns
10
CS or RD high to CS and RD low for next read (Note 1) Tird 2*DCLKP+10 - ns
CS or RD high to CS and WR low for next write (Note 1) Tirdtw 2*DCLKP+10 - ns
Write
Delay between WR then CS low or CS then WR low Ticdw 0 - ns
Data setup before CS or WR high Tidsu 2*DCLKP+10 - ns
CS and WR low for write (Note 1) Tiwpw 2*DCLKP - ns
Data hold after CS or WR high Tidhw DCLKP - ns
CS or WR high to CS and RD low for next read (Note 1) Tiwtrd 2*DCLKP+10 - ns
CS or WR high to CS and WR low for next write (Note 1) Tiwd 2*DCLKP+10 - ns
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =
1/DCLK. The DSP clock can be defined as follows:

Internal Clock Mode:

DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns
DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns

It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.

12
 A1:0
Tiah
DATA7:0
Tias
Tidhr
Tidd
CS
Ticdr Tidis
WR
Tirpw Tird Tirdtw

RD

Figure 5. Intel® Parallel Host Slave Mode Read Cycle for DSPC

A1:0
Tiah
DATA7:0
Tias
Tidhw
CS
Ticdw Tidsu
RD
Tiwpw Tiwd Tiwtrd

WR

Figure 6. Intel® Parallel Host Slave Mode Write Cycle for DSPC

13
1.10 Switching Characteristics — Motorola® Host Slave Mode (DSPAB)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
Address setup before FCS and FDS low Tmas 5 - ns
Address hold time after FCS and FDS low Tmah 5 - ns
Read
Delay between FDS then FCS low or FCS then FDS low Tmcdr 0 - ns
Data valid after FCS and FRD low with R/W high) Tmdd - 21 ns

FCS and FDS low for read (Note 1) Tmrpw DCLKP + 10 - ns

Data hold time after FCS or FDS high after read Tmdhr 5 - ns
Data high-Z after FCS or FDS high after read Tmdis - 22 ns
FCS or FDS high to FCS and FDS low for next read (Note 1) Tmrd 2*DCLKP + 10 - ns
FCS or FDS high to FCS and FDS low for next write(Note 1) Tmrdtw 2*DCLKP + 10 - ns
Write
Delay between FDS then FCS low or FCS then FDS low Tmcdw 0 - ns
Data setup before FCS or FDS high Tmdsu 20 - ns
FCS and FDS low for write (Note 1) Tmwpw DCLKP + 10 - ns
R/W setup before FCS AND FDS low Tmrwsu 5 - ns
R/W hold time after FCS or FDS high Tmrwhld 5 - ns
Data hold after FCS or FDS high Tmdhw 5 - ns
FCS or FDS high to FCS and FDS low with R/W high for Tmwtrd 2*DCLKP + 10 - ns
next read (Note 1)
FCS or FDS high to FCS and FDS low for next write(Note 1) Tmwd 2*DCLKP + 10 - ns
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =
1/DCLK. The DSP clock can be defined as follows:

Internal Clock Mode:

DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns
DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns

It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.

14
 F A1:0
Tmah
F DATA7:0
Tmas
Tmdhr
Tmdd
FCS
Tmrwsu
Tmcdr Tmdis Tmrwhld
FR/W
Tmrpw Tmrd Tmrdtw

F DS

Figure 7. Motorola® Parallel Host Slave Mode Read Cycle for DSPAB

F A1:0
Tmas Tmah
F DATA7:0
Tmdsu Tmdhw
F CS F
Tmcdw Tmwpw Tmrwhld
F R/W
Tmrwsu Tmwd Tmwtrd
F DS

Figure 8. Motorola® Parallel Host Slave Mode Write Cycle for DSPAB

15
1.11 Switching Characteristics — Motorola® Host Slave Mode (DSPC)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
Address setup before CS and DS low Tmas DCLKP - ns
Address hold time after CS and DS low Tmah DCLKP+15 - ns
Read
Delay between DS then CS low or CS then DS low Tmcdr 0 - ns
Data valid after CS and RD low with R/W high Tmdd - 2*DCLKP+ ns
25
CS and DS low for read (Note 1) Tmrpw 2*DCLKP - ns
Data hold time after CS or DS high after read Tmdhr DCLKP+ 10 - ns
Data high-Z after CS or DS high low after read Tmdis - 2*DCLKP+ ns
10
CS or DS high to CS and DS low for next read (Note 1) Tmrd 2*DCLKP+10 - ns
CS or DS high to CS and DS low for next write (Note 1) Tmrdtw 2*DCLKP+10 - ns
Write
Delay between DS then CS low or CS then DS low Tmcdw 0 - ns
Data setup before CS or DS high Tmdsu 2*DCLKP+10 - ns
CS and DS low for write (Note 1) Tmwpw 2*DCLKP - ns
R/W setup before CS AND DS low Tmrwsu DCLKP - ns
R/W hold time after CS or DS high Tmrwhld 5 - ns
Data hold after CS or DS high Tmdhw DCLKP - ns
CS or DS high to CS and DS low with R/W high for next read Tmwtrd 2*DCLKP+10 - ns
(Note 1)
CS or DS high to CS and DS low for next write (Note 1) Tmwd 2*DCLKP+10 - ns
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =
1/DCLK. The DSP clock can be defined as follows:

Internal Clock Mode:

DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns
DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns

It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.

16
 A1:0
Tmah
DATA7:0
Tmas
Tmdhr
Tmdd
CS
Tmrwsu
Tmcdr Tmdis Tmrwhld
R/W
Tmrpw Tmrd Tmrdtw

DS

Figure 9. Motorola® Parallel Host Slave Mode Read Cycle for DSPC

A1:0
Tmas Tmah
DATA7:0
Tmdsu Tmdhw
CS
Tmcdw Tmwpw Tmrwhld
R/W
Tmrwsu Tmwd Tmwtrd
DS

Figure 10. Motorola® Parallel Host Slave Mode Write Cycle for DSPC

17
1.12 Switching Characteristics — SPI Control Port Slave Mode (DSPAB)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Units
FSCCLK clock frequency (Note 1) fsck - 2 MHz
FCS falling to FSCCLK rising tcss 20 - ns
FSCCLK low time tscl 150 - ns
FSCCLK high time tsch 150 - ns
Setup time FSCDIN to FSCCLK rising tcdisu 50 - ns
Hold time FSCCLK rising to FSCDIN (Note 2) tcdih 50 - ns
Transition time from FSCCLK to FSCDOUT valid tscdov - 40 ns
Time from FSCCLK rising to FINTREQ rising (Note 3) tscrh - 200 ns
Hold time for FINTREQ from FSCCLK rising (Note 4, 5) tscrl 0 - ns
Time from FSCCLK falling to FCS rising tsccsh 20 - ns
High time between active FCS tcsht 200 - ns
Time from FCS rising to FSCDOUT high-Z tcscdo 20 ns
Notes: 1. The specification fsck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the DSP application
code. The relevant application code user’s manual should be consulted for the software speed
limitations.
2. Data must be held for sufficient time to bridge the transition time of FSCCLK.
3. FINTREQ goes high only if there is no data to be read from the DSP at the rising edge of FSCCLK for
the second-to-last bit of the last byte of data during a read operation as shown.
4. If FINTREQ goes high as indicated in (Note 3), then FINTREQ is guaranteed to remain high until the
next rising edge of FSCCLK. If there is more data to be read at this time, FINTREQ goes active low
again. Treat this condition as a new read transaction. Raise chip select to end the current read
transaction and then drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start
a new read transaction.

18
 tsccsh

FCS
tcsht
tcss tscl
0 1 2 6 7 0 5 6 7

FSCCLK

tsch
t t
r f

FSCDIN A6 A5 A0 R/W MSB LSB A6

t cdisu t cdih

FSCDOUT MSB LSB

tri-state

tscdov tscdov
tcscdo

FINTREQ

tscrh tscrl

Figure 11. SPI Control Port Slave Mode Timing (DSPAB)

19
1.13 Switching Characteristics — SPI Control Port Slave Mode (DSPC)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Units
SCCLK clock frequency (Note 1) fsck - 5 MHz
CS falling to SCCLK rising tcss 4*DCLKP - ns
SCCLK low time tscl 4*DCLKP - ns
SCCLK high time tsch 4*DCLKP - ns
Setup time SCDIN to SCCLK rising tcdisu DCLKP - ns
Hold time SCCLK rising to SCDIN (Note 2) tcdih DCLKP+20 - ns
Time from SCCLK low to SCDOUT valid tscdov - 3*DCLKP+20 ns
Time from SCCLK rising to INTREQ rising tscrh - DCLKP ns
Hold time for INTREQ from SCCLK rising tscrl DCLKP - ns
Time from SCCLK falling to CS rising tsccsh 2*DCLKP+15 - ns
Time from SCCLK low to CS falling tsccsl 10 ns
High time between active CS tcsht 4*DCLKP - ns
Time from CS rising to SCDOUT high-Z tcscdo DCLKP ns
Notes: 1. The specification fsck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the software. The
relevant application code user’s manual should be consulted for the software speed limitations.
2. Data must be held for sufficient time to bridge the transition time of SCCLK.

20
 Figure 12. SPI Control Port Slave Mode Timing (DSPC)

21
1.14 Switching Characteristics — Digital Audio Input (DSPAB)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
FSCLKN1 period for Slave mode Tsclki 40 - ns
FSCLKN1 duty cycle for Slave mode 45 55 %
Slave Mode (Note 2)
Time from active edge of FSCLKN1(2) to FLRCLKN1(2) transition Tstlr 10 - ns
Time from FLRCLKN1(2) transition to FSCLKN1(2) active edge Tlrts 10 - ns
FSDATAN1(2) setup to FSCLKN1(2) transition (Note 1) Tsdsus 5 - ns
FSDATAN1(2) hold time after FSCLKN1(2) transition (Note 1) Tsdhs 5 - ns
Notes: 1. This timing parameter is defined from the active edge of FSCLKN1/2. The active edge of FSCLKN1/2
is the point at which the data is valid.
2. Slave mode is defined as FSCLKN1/2 and FLRCLKN1/2 driven by an external source.

FSC LKN1
FSC LKN2
T sclki
T lrts T stlr
FLRC LKN1
FL R C L K N 2
T s dsu s T sd hs

FS D A T A N 1
FSDATAN2

Figure 13. Digital Audio Input Data, Slave Clock Timing

22
1.15 Switching Characteristics — Serial Audio Input (DSPC)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
Slave Mode
SCLKN period for Slave mode Tsclki 40 - ns
SCLKN duty cycle for Slave mode 45 55 %
Time from active edge of SCLKN to LRCLKN transition Tstlr 20 - ns
Time from LRCLKN transition to SCLKN active edge Tlrts 20 - ns
SDATAN0 setup to SCLKN transition (Notes 2) Tsdsus 10 - ns
SDATAN0 hold time after SCLKN transition (Notes 2) Tsdhs 10 - ns
Notes: 1. Slave mode is defined as SCLKN and LRCLKN being driven by an external source.
2. This timing parameter is defined from the active edge of SCLKN. The active edge of SCLKN is the point
at which the data is valid.

SCLKN

Tsclki
Tlrts
Tstlr
LRCLKN

Tsdsus Tsdhs

SDATAN0, 1, 2, 3

Figure 14. Serial Audio Input Data, Slave Clock Timing

23
1.16 Switching Characteristics — CMPDAT, CMPCLK (DSPAB)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
Serial compressed data clock CMPCLK frequency Tcmpclk - 27 MHz
CMPDAT setup before CMPCLK high Tcmpsu 10 - ns
CMPDAT hold after CMPCLK high Tcmphld 10 - ns

CMPCLK

CMPDAT
Tcmpsu Tcmphld
Tcmpclk

Figure 15. Serial Compressed Data Timing

24
1.17 Switching Characteristics — Parallel Data Input (DSPAB)
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
CMPCLK Period Tcmpclk 4*DCLKP + 10 ns
FDAT[7:0] setup before CMPCLK high Tcmpsu 10 ns
FDAT[7:0] hold after CMPCLK high Tcmphld 10 ns
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can
be defined as follows:

Internal Clock Mode:

DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns
DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns

It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.

CMPCLK

FDAT[7:0]

Tcm psu Tcm phld

Tcm pclk

Figure 16. Parallel Data Timing

25
1.18 Switching Characteristics — Digital Audio Output
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
MCLK period Tmclk 40 - ns
MCLK duty cycle 40 60 %
SCLK0, SCLK1 period for Master or Slave mode (Note 2) Tsclk 40 - ns
SCLK0, SCLK1 duty cycle for Master or Slave mode (Note 2) 45 55 %
Master Mode (Output A1 Mode) (Note 2, 3)
SCLK0, SCLK1 delay from MCLK rising edge, MCLK as an Tsdmi 15 ns
input
LRCLK0, LRCLK1 delay from SCLK0, SCLK1 transition, Tlrds 10 ns
respectively (Note 4)
AUDATA7–0 delay from SCLK0, SCLK1 transition (Note 4) Tadsm 10 ns
Slave Mode (Output A0 Mode) (Note 5)
Time from active edge of SCLK0, SCLK1 to LRCLK0, LRCLK1 Tstlr 10 - ns
transition
Time from LRCLK0, LRCLK1 transition to SCLK0, SCLK1 Tlrts 10 - ns
active edge
AUDATA7–0 delay from SCLK0, SCLK1 transition (Note 4) Tadss 15 ns
Notes: 1. DSPC has two Digital Audio Output modules having analogous signal names ending in 0 and 1. Both
DAO ports share a common MCLK but have independent SCLKs and LRCLKs.
2. Master mode timing specifications are characterized, not production tested.
3. Master mode is defined as the CS49400 driving both SCLK0, SCLK1, LRCLK0, and LRCLK1. When
MCLK is an input, it is divided to produce SCLK0, SCLK1, LRCLK0 and LRCLK1.
4. This timing parameter is defined from the non-active edge of SCLK0 and SCLK1. The active edge of
SCLK0 and SCLK1 is the point at which the data is valid.
5. Slave mode is defined as SCLK0, SCLK1, LRCLK0 and LRCLK1 driven by an external source.

26
 MCLK (Input)
Tmclk

SCLK0,1 (Output)
T sdmo,T sdmi

SCLK 0,1
(Output)
Tsclk
Tlrds
LRCLK 0,1
(Output)
Tadsm

AUDATA7:0

Master Mode (Output A1) Output Clock Timing and Digital Audio
Output Data

SCLK 0,1
(Input)
Tlrts Tsclk
Tstlr
LRCLK 0,1
(Input)
Tadss

AUDATA7:0

Slave Mode (Output A0) Output Clock Timing and Digital Audio
Output Data
Figure 18. Digital Audio Output Data, Input and Output Clock Timing

27
1.19 Switching Characteristics — SRAM/FLASH Interface
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF)
Parameter Symbol Min Max Unit
Write Cycle
Single Byte Write Cycle Twrc (SRAM_FLASH_WR_CYCLE + 1) * DCLKP - ns
Data Hold after NV_WE or NV_CS high Tdh DCLKP-5 - ns
Data Valid after NV_CS and NV_WE low Tdv 10 ns
Data Strobe Tds DCLKP-5 - ns
Read Cycle
Single Byte Read Cycle Trdc (SRAM_FLASH_RD_CYCLE + 1) * DCLKP - ns
Data Strobe Tds DCLKP-5 - ns
Data Hold after NV_WE or NV_CS high Tdh DCLKP+5 - ns
Data Setup Time Tsu DCLKP+5 - ns

XTA[19:0]

NV_CS
T wrc
T ds

NV_WE

T dv T dh

XTD[7:0] MSP LSP

Figure 19. SRAM/Flash Controller Timing Diagram - Write Cycle

EXTA[19:0]

NV_CS
T rdc
Tds

NV_OE

T su Tdh

EXTD[7:0] MSP LSP

Figure 20. SRAM/Flash Controller Timing Diagram - Read Cycle

28
 EXTA[19:0] Valid

NV_CS
Twrc
T ds

NV_WE

NV_OE
T dv T dh

EXTD[7:0] LSP

Figure 21. SRAM/Flash Controller Timing Diagram - Single Byte Write Cycle

EXTA[19:0] Valid

NV_CS
Trdc
Tds

NV_OE

NV_WE

Tsu Tdh

EXTD[7:0] LSP

Figure 22. SRAM/Flash Controller Timing Diagram - Single Byte Read Cycle

29
1.20 Switching Characteristics — SDRAM Interface
(TA = 25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF, SD_CLKOUT = SD_CLKIN)
Parameter Symbol Min Max Unit
SD_CLKIN high time tclk_high 0.475*DCLKP - ns
SD_CLKIN low time tclk_low 0.475*DCLKP - ns
SD_CLKOUT rise/fall time tclkrf - 1 ns
SD_CLKOUT duty cycle tclkrf 45 55 %
SD_CLKOUT rising edge to signal valid td - 9.8 ns
Signal hold from SD_CLKOUT rising edge th 1.0 ns
SD_CLKOUT rising edge to SD_DQMn valid tDQd - 7.2 ns
SD_DQMn hold from SD_CLKOUT rising edge tDQh 1.0 - ns
SD_DATA valid setup to SD_CLKIN rising edge tDAs 8.3 ns
SD_DATA valid hold to SD_CLKIN rising edge tDAh 1.0 ns
SD_CLKOUT rising edge to ADDRn valid td - 8.0 ns

SD _CLK O UT

td th

S D _C S

S D _R A S

S D _C A S

S D _W E

SD _DQ M n

S D_AD D Rn O P CO D E

S D_DA TA n

Figure 23. SDRAM Controller Timing Diagram - Load Mode Register Cycle

30
 LKOUT

td th

S D_CS

D_RA S

D_CA S

S D_WE
tDQh

_DQMn 00 11

ADDRn

DATAn LSP0 MSP0

Figure 24. SDRAM Controller Timing Diagram - Burst Write Cycle

31
32
_CLKOUT
td th tclkrf
S D_ CS

S D_ RA S

S D_ CA S

S D_ W E TDQh
tDQd
SD_DQMn 00 11

D_ADDRn
td
tDAs tDAh
CAS=2
SD_DATAn LSP0 MSP0 LSP3 MSP3

SD_CLKIN

tclk_low tclk_high

Figure 25. SDRAM Controller Timing Diagram - Burst Read Cycle

SD_CLKOUT

td td th
SD_CS

SD_RAS

SD_CAS

SD_WE

SD_DQMn

SD_ADDRn

SD_DATAn

Figure 26. SDRAM Controller Timing Diagram - Auto Refresh Cycle

33
2. OVERVIEW • HDCD®
The CS49400 is a 24-bit fixed-point decoder DSP All of the above audio decoding/processing
followed by a 32-bit fixed point programmable algorithms and the associated application notes
post-processor DSP. The decoder portion of the (AN208 and their corresponding appendices) are
CS49400 is referred to as “DSPAB”. The post- available through the Crystal WareTM Software
processor DSP is referred to as “DSPC”. Both Licensing Program. Please refer to AN208 for the
DSPAB and DSPC include their own dedicated latest listing of application codes for DSPAB.
peripherals such as serial and parallel control ports, DSPC is unique to DSPAB in the sense that the
and serial audio interfaces. DSPC also has a designer may choose to just load a standard or
external memory interface which supports enhanced application code (.ULD file) from the
SRAM/SDRAM/EPROM. Crystal Ware Software Library or if they have
All the decoding/processing algorithms listed access to the Cirrus Framework DSPC
below require delivery of PCM or IEC61937- Development Kit, they may choose to build their
packed compressed data via I2S or LJ formatted own application code from a variety of modules. A
digital audio to the CS49400. Today the CS49400 DSPC application code contains all of the
will support all of the following necessary post-processing modules, such as
decoding/processing standards: Crossbar Mixer, Pro Logic Module, Bass Manager
• PCM Pass-Through/PCM Upsampler Module, and Audio Manager (Kernel). A module is
just a single processing module, such as Tone
• Dolby Digital™ (with Dolby Pro Logic)™ Control, Parametric/Graphic EQ, or Dolby Pro
• Dolby Digital Pro Logic II™ Logic matrix decoder. DSPC on the CS49400 will
support the following post-processing application
• Dolby Digital EX™ codes and/or modules:
• Dolby Digital EX Pro Logic II™ • Standard Post-Processor (includes the follow-
• MPEG-2, Advanced Audio Coding Algorithm ing modules all compiled into one .ULD file):
(AAC) Downmixer module, Dualzone module, Cross-
• MPEG Multichannel bar Mixer module, 7.1 Channel Bass Manager
module, Audio Manager module (Volume
• MPEG Multichannel with Dolby Pro Logic II™ Control, Trim Control and Channel Remap),
• MPEG-1/2, Layer III (MP3) and Delay module
• DTS Digital Surround™ • Advanced Post-Processor (includes the all of
• DTS 96/24™ (Front-end Decoder) the standard post-processing modules plus the
Tone Control module, Parametric EQ module,
• DTS Digital Surround™ with Re-EQ module in all compiled into one .ULD )
Dolby Pro Logic II™
• Dolby Pro Logic™
• DTS-ES Extended Surround™
• Dolby Pro Logic II™
(DTS-ES Discrete 6.1 and DTS-ES Matrix 6.1)
• SRS Circle Surround II™
• DTS-ES 96/24™ (Front-end Decoder)
• DTS Neo:6™
• DTS Neo:6™
• LOGIC7®
• LOGIC7®
• THX® Surround EX™ 7.1 Channel
• SRS Circle Surround™ II
Post-Processor

34
• THX® Ultra2 Cinema™ 7.1 Channel 2.2 DSPC
Post-Processor DSPC is a 32-bit, general-purpose, fixed-point
™ RAM-based processor which includes on-chip
• Cirrus Extra Surround
ROM tables. It has been designed with a generous
• Cirrus Original Multichannel Surround™
amount of on-chip program and data RAM, and has
• Virtual Dolby Digital™/Virtual Dolby Digital all necessary peripherals required to support the
Pro Logic II™ Virtualizer Module latest standards in consumer entertainment
products such as AV receivers and DVD-
• VMAx VirtualTheater™ Virtualizer Module
Audio/Video players.
• HDCD® Multichannel Decoder
DSPC has on-chip data and program RAM, and
• DVD-Audio/Video and Multichannel SACD both external SDRAM and SRAM memory
Bass Management interfaces. These interfaces can be used to expand
the data memory. DSPC also has its own 8-channel
• DTS/DTS-ES 96/24™ Back-End Decoder
digital audio input for post-processing PCM from a
• DTS/DTS-ES 96/24™ Back-End Decoder with Multichannel Super Audio CD (SACD) input or
THX® Ultra2 Cinema™ DVD-Audio/Video input, via high-performance
A/Ds or from some other type of multichannel
All of the above audio post-processing applications
digital input, capable of delivering 4 stereo digital
codes and/or Cirrus FrameworkTM modules and
audio channels such as IEEE1394 (a.k.a. I-Link®
the associated application notes (AN209 and the
associated appendices) are available through the or Firewire®). Data can be delivered to this port
using the standard audio formats (I2S or LJ). DSPC
Crystal WareTM Software Licensing Program. All
can be controlled serially using the SPI standard or
standard or enhanced post-processing code
via Parallel host control port using the Motorola®
modules are only available to customers who
or Intel® standard. DSPC has a Digital Audio
qualify for the Cirrus FrameworkTM CS49400
output port that has eight stereo serial data outputs
Family DSPC Programming Kit. Please refer to
for a total of 16 channels. Data can be delivered
AN209 for the latest listing of application codes
from these outputs in serial I2S or LJ format. Two
and Cirrus FrameworkTM modules available for
of these outputs (AUDAT3, AUDAT7) can be
DSPC.
configured as a IEC60958-format S/PDIF
2.1 DSPAB transmitter.
DSPAB is an enhanced version of the CS49300. It This document focuses on the electrical features of
was designed to have legacy code support for all the CS49400. The features are described from a
decoder applications developed for the CS49300. It hardware design perspective. It should be
includes performance enhancements such as the understood that not all of the features portrayed in
ability to decode AAC without the need for this document are supported by all of the versions
external SRAM memory. DSPAB has a Digital of application code available. The application code
Audio Input (DAI) and a Compressed Data Input user’s guides should be consulted to determine
(CDI) port for data delivery in either I2S or LJ which hardware features are supported by the
format. DSPAB can be controlled serially using the software.
SPI standard and can also be controlled via a Please note that a download of application software
Parallel host control port using the Motorola® or is required each time the part is powered up. This
Intel® communication standards. term should be interpreted as meaning the transfer of
application code into the internal memory of the part

35
from either an external microcontroller or through 3.2 Termination Requirements
one of the boot procedures listed in Section 8. The CS49400 incorporates open drain pins which
3. TYPICAL CONNECTION DIAGRAMS must be pulled high for proper operation.
FINTREQ and INTREQ are always open drains
Four typical connection diagrams have been which requires a pull-up for proper operation.
presented to illustrate using the part with the
different communication modes available. They Due to the internal, multiplexed design of the pins,
are as follows: certain signals may or may not require termination
depending on the mode being used. If a parallel
Figure 27, "SPI Control with External Memory - host communication mode is not being used, all
144 Pin Package" on page 38. parallel control pins must be terminated or driven
Figure 28, "Intel® Parallel Control Mode - 144 Pin as these pins will come up as high impedance
Package" on page 39.
inputs and will be prone to oscillation if they are
Figure 29, "Motorola® Parallel Control Mode - 144 left floating. The specific termination requirements
Pin Package" on page 40.
may vary since the state of some of the GPIO pins
The following should be noted when viewing the will determine the communication mode at the
typical connection diagrams: rising edge of reset (please see Section 6 “Control”
Note: The pins are grouped functionally in each on page 41 for more information). For the explicit
of the typical connection diagrams. Please be termination requirements of each communication
aware that the CS49400 symbol may appear mode please see the typical connection diagrams.
differently in each diagram.
Generally a 3.3k Ohm resistor is recommended for
The external memory interface is supported open drain and mode select pins. A 10k Ohm
when a serial or parallel communication mode resistor is sufficient for all other unused inputs.
has been chosen.

3.1 Multiplexed Pins 3.3 Phase Locked Loop Filter

The CS49400 incorporates a large amount of The internal phase locked loop (PLL) of the
flexibility into a 144 pin package. The pins are CS49400 requires an external filter. The topology
internally multiplexed to serve multiple purposes. of this filter is shown in the typical connection
Some pins are designed to operate in one mode at diagrams. The component values are shown below.
power up, and serve a different purpose when the Care should be taken when laying out the filter
DSP is running. Other pins have functionality circuitry to minimize trace lengths and to avoid any
which can be controlled by the application running high frequency signals. Any noise coupled onto the
on the DSP. In order to better explain the behavior filter circuit will be directly coupled into the PLL,
of the part, the pins which are multiplexed have which could affect performance.
been given multiple names. Each name is specific Reference Designator Value
to the pin’s operation in a particular mode. C1 2.2uF
In this document, pins will be referred to by their C2 1200pF
functionality. Section 12 “Pin Description” on C3 68pF
page 86 describes each pin of the CS49400 and lists R1 3k Ohm
all of its names. Please refer to this section when Table 1. PLL Filter Component Values
exact pin numbers are in question.

36
4. POWER 4.2 Analog Power Conditioning
The CS49400 requires a 2.5V digital power supply In order to obtain the best performance from the
for the core logic and 2.5V I/O and a 2.5V analog CS49400’s internal PLL, the analog power supply
power supply for the internal PLL. For systems PLLVDD must be as noise-free as possible. A
with external memory that runs on 3.3V, a 3.3V ferrite bead and two capacitors should be used to
digital power supply is required on the VDDSD filter the VDD to generate PLLVDD. This power
pins along with four digital grounds on VSSSD. scheme is shown in the typical connection
There are seven digital power pins, VDD1 through diagrams.
VDD7, along with seven digital grounds, VSS1
through VSS7. There is one analog power pin, 4.3 Ground
PLLVDD, and one analog ground, PLLVSS. The For two layer circuit boards, care should be taken
recommendations given below for decoupling and to have sufficient ground between the DSP and
power conditioning of the CS49400 will help to parts in which it will be interfacing (DACs, ADCs,
ensure reliable performance. S/PDIF Receivers, microcontrollers, and especially
external memory). Insufficient ground can degrade
4.1 Decoupling noise margins between devices resulting in data
It is necessary to decouple the power supply by integrity problems.
placing capacitors directly between the power and
ground of the CS49400. Each pair of power/ground 4.4 Pads
pins (VDD1/VSS1, etc.) should have its own The CS49400 has two different I/O voltage levels.
decoupling capacitors. The recommended All signal pins not associated with the External
procedure is to place both a 0.1uF and a 1uF SRAM/SDRAM memory interface operate from
capacitor as close as physically possible to each the 2.5V supply and are 3.3V tolerant. The external
power pin. The 0.1uF capacitor should be closest to SRAM/SDRAM memory interface operates at
the part (typically 5mm or closer). 3.3V only. However, if the external memory
interface is not used VDDSD1-4 may be connected
to 2.5V.

37
 NOTE:
1. A capacitor pair (.01uF and 0.1uF) must
be supplied for each power pin.
2. The digital supply (+2.5 VD) is filtered.
to obtain the analog suply (+2.5 VA).
+2.5 VD FERRITE BEAD +2.5 VA +3.3VD

+
3.3K
1
RESISTOR PACK.

1uF 0.1uF 47uF 0.1uF 0.01uF 0.1uF

C

RESISTOR PACK.
10K
10

+
9
8
7
6
5
4
3
2

10K
1uF 0.1uF

100
114
132
138
90

10
20

70
58
51
42
VDDSD1
VDDSD2
VDDSD3
VDDSD4
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
144 RESET SD_CS 68
3 INTREQ,ABOOT SD_CLK_EN 64
135 SCS SD_CLK_IN 61
142 SCCLK SD_CLK_OUT 59
136 SCDIN SD_DQM0 39
MICROCONTROLLER 140 SCDOUT,SCDIO SD_DQM1 45
78
SD_CAS +3.3VD
16 FINTREQ SD_RAS 77
15 FCS SD_WE 33
SPI 6 FAO,FSCCLK
INTERFACE 4 FA1, FSCDIN NV_CS,GPIO14 32
7 FHS2,FSCDIO,FSCDOUT NV_OE,GPIO15 31
NV_WE,GPIO16 30
129 CS,GPIO9
141 HINBSY,GPIO8 SD_ADDR0, EXTA0 73
120 WR,DS,GPIO10 SD_ADDR1, EXTA1 74
121 RD,R/W,GPIO11 SD_ADDR2,EXTA2 75
139 A1,GPIO12 SD_ADDR3,EXTA3 76
130 AO,GPIO13 SD_ADDR4,EXTA4 67
116 HDATA0,GPIO0 SD_ADDR5,EXTA5 66
115 HDATA1,GPIO1 SD_ADDR6,EXTA6 65
112 HDATA2,GPIO2 SD_ADDR7,EXTA7 63
105 HDATA3,GPIO3 SD_ADDR8, EXTA8 62
103 HDATA4,GPIO4 SD_ADDR9,EXTA9 60
97 HDATA5, GPIO5 SD_ADR10,EXTA10 72
96
95
HDATA6,GPIO6 CS494XX SD_DATA8,EXTA11 56
55
EXTERNAL ROM
HDATA7,GPIO7 SD_DATA9,EXTA12
SD_DATA10,EXTA13 54
12 FHS0,FWR,FDS SD_DATA11,EXTA14 53
13 FHS1,FRD,FR/ W SD_DATA12, EXTA15 52
29 FDAT0 SD_DATA13,EXTA16 49
27 FDAT1 SD_DATA14,EXTA17 47
24 FDAT2 SD_DATA15,EXTA18 46
22 FDAT3 SD_BA,EXTA19 71
19 FDAT4
18 FDAT5 SD_DAT0,EXTD0 34
14 FDAT6 SD_DAT1,EXTD1 35
9 FDAT7 SD_DAT2, EXTD2 36
99 MCLK SD_DATA3, EXTD3 37
117 CMPREQ,FLRCLKN2 SD_DATA4,EXTD4 38
ADC OR SPDIF RX 111
118
CMPCLK,FSCLKN2 SD_DATA5,EXTD5 40
43
CMPDAT,FSDATAN2 SD_DATA6,EXTD6
SD_DATA7,EXTD7 44
119 FLRCLKN1
ADC 134
131
FSCLKN1,STCCLK2
FSDATAN1
SCLK0 104
85 LRCLKN, GPIO23 LRCLK0 108
86 SCLKN,GPIO22 AUDATA0 110
82 SDATAN0,GPIO24 AUDATA1 109
6 DACs
ADCs 81
80
SDATAN1,GPIO25 AUDATA2 107
106
SDATAN2,GPIO26 AUDAT3,XMT958A
79 SDATAN3,GPIO27
98
2 SPDIF TX
SCLK1
OSCILLATOR +2.5 VA
127
126
CLKIN,XTALI LRCLK1 87
102
CLKOUT,XTAL0 AUDATA4,GPIO28
125 PLLVDD AUDATA5,GPIO29 94
123 FILT2 AUDATA6,GPIO30 93
+ 124 92
FILT1 AUDATA7,XMT958B,GPIO31
128 CLKSEL
C1 122 28
PLLVSS TEST
DBCK 26
DBDA 25
143 USH2,CS_OUT,GPIO17
R1 2 23
C2 C3 UHS1,GPIO19 FDBDA
1 UHS0,GPIO18 FDBCK 17
5 GPIO20
VSSSD1
VSSSD2
VSSSD3
VSSSD4

8 GPIO21
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

10
NC1
NC2
NC3
NC4
NC5

2
3
4
5
6
7
8
9

3.3K
101
113
133
137
89
88
84
83
48

91

11
21

69
57
50
41

3.3K 3.3K 10K 10K

C

+2.5 VD
1

Figure 27. SPI Control with External Memory - 144 Pin Package

38
 NOTE:
1. A capacitor pair (.01uF and 0.1uF) must
be supplied for each power pin.
2. The digital supply (+2.5 VD) is filtered.
to obtain the analog suply (+2.5 VA).

+2.5 VD FERRITE BEAD +2.5 VA +3.3VD

+
3.3K

1
1uF 0.1uF 47uF 0.1uF 0.01uF 0.1uF
C

3.3K
10

+
9
8
7
6
5
4
3
2

10K
1uF 0.1uF

100
114
132
138
90

10
20

70
58
51
42
VDDSD1
VDDSD2
VDDSD3
VDDSD4
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
144 RESET SD_CS 68
SD_CLK_EN 64
135 SCS SD_CLK_IN 61
142 SCCLK SD_CLK_OUT 59
136 SCDIN SD_DQM0 39
MICROCONTROLLER 140
7
SCDOUT,SCDIO SD_DQM1 45
78
FHS2,FSCDIO,FSCDOUT SD_CAS +3.3VD
SD_RAS 77
3 INTREQ,ABOOT SD_WE 33
PARALLEL 129 CS,GPIO9
INTERFACE 141 HINBSY,GPIO8 NV_CS,GPIO14 32
120 WR,DS,GPIO10 NV_OE,GPIO15 31
121 RD,R/W,GPIO11 NV_WE,GPIO16 30
130 AO,GPIO13
139 A1,GPIO12 SD_ADDR0, EXTA0 73
116 HDATA0,GPIO0 SD_ADDR1, EXTA1 74
115 HDATA1,GPIO1 SD_ADDR2,EXTA2 75
112 HDATA2,GPIO2 SD_ADDR3,EXTA3 76
105 HDATA3,GPIO3 SD_ADDR4,EXTA4 67
103 HDATA4,GPIO4 SD_ADDR5,EXTA5 66
97 HDATA5,GPIO5 SD_ADDR6,EXTA6 65
96 HDATA6,GPIO6 SD_ADDR7,EXTA7 63
95 HDATA7,GPIO7 SD_ADDR8, EXTA8 62
SD_ADDR9,EXTA9 60
16 FINTREQ SD_ADR10,EXTA10 72
15
12
FCS CS494XX SD_DATA8,EXTA11 56
55
EXTERNAL ROM
FHS0,FWR,FDS SD_DATA9,EXTA12
13 FHS1,FRD,FR/ W SD_DATA10,EXTA13 54
6 FAO,FSCCLK SD_DATA11,EXTA14 53
4 FA1, FSCDIN SD_DATA12, EXTA15 52
29 FDAT0 SD_DATA13,EXTA16 49
27 FDAT1 SD_DATA14,EXTA17 47
24 FDAT2 SD_DATA15,EXTA18 46
22 FDAT3 SD_BA,EXTA19 71
19 FDAT4
18 FDAT5 SD_DAT0,EXTD0 34
14 FDAT6 SD_DAT1,EXTD1 35
9 FDAT7 SD_DAT2, EXTD2 36
99 MCLK SD_DATA3, EXTD3 37
117 CMPREQ,FLRCLKN2 SD_DATA4,EXTD4 38
ADC OR SPDIF RX 111
118
CMPCLK,FSCLKN2 SD_DATA5,EXTD5 40
43
CMPDAT,FSDATAN2 SD_DATA6,EXTD6
SD_DATA7,EXTD7 44
119 FLRCLKN1
ADC 134
131
FSCLKN1,STCCLK2
FSDATAN1
SCLK0 104
85 LRCLKN,GPIO23 LRCLK0 108
86 SCLKN,GPIO22 AUDATA0 110
82 SDATAN0,GPIO24 AUDATA1 109
6 DACs
ADCs 81
80
SDATAN1,GPIO25 AUDATA2 107
106
SDATAN2,GPIO26 AUDAT3,XMT958A
79 SDATAN3,GPIO27
98
2 SPDIF TX
SCLK1
OSCILLATOR +2.5 VA
127
126
CLKIN,XTALI LRCLK1 87
102
CLKOUT,XTAL0 AUDATA4,GPIO28
125 PLLVDD AUDATA5,GPIO29 94
123 FILT2 AUDATA6,GPIO30 93
+ 124 92
FILT1 AUDATA7,XMT958B,GPIO31
128 CLKSEL
C1 122 28
PLLVSS TEST
DBCK 26
DBDA 25
143 USH2,CS_OUT,GPIO17
2 UHS1,GPIO19 FDBDA 23
R1 1 17
C2 C3 UHS0,GPIO18 FDBCK
5 GPIO20
VSSSD1
VSSSD2
VSSSD3
VSSSD4

8 GPIO21
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

10
NC1
NC2
NC3
NC4
NC5

2
3
4
5
6
7
8
9

3.3K
3.3K 3.3K 10K 10K
101
113
133
137
89
88
84
83
48

91

11
21

69
57
50
41

+2.5 VD
1

Figure 28. Intel® Parallel Control Mode - 144 Pin Package

39
 NOTE:
1. A capacitor pair (.01uF and 0.1uF) must
be supplied for each power pin.
2. The digital supply (+2.5 VD) is filtered.
to obtain the analog suply (+2.5 VA).

+2.5 VD FERRITE BEAD +2.5 VA +3.3VD

+
3.3K 10K
1

1
1uF 0.1uF 47uF 0.1uF 0.01uF 0.1uF
C

RESISTOR PACK.
10

10

+
9
8
7
6
5
4
3
2

9
8
7
6
5
4
3
2

10K
1uF 0.1uF

100
114
132
138
90

10
20

70
58
51
42
VDDSD1
VDDSD2
VDDSD3
VDDSD4
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
144 RESET SD_CS 68
SD_CLK_EN 64
135 SCS SD_CLK_IN 61
142 SCCLK SD_CLK_OUT 59
136 SCDIN SD_DQM0 39
MICROCONTROLLER 140
7
SCDOUT,SCDIO SD_DQM1 45
78
FHS2,FSCDIO,FSCDOUT SD_CAS +3.3VD
SD_RAS 77
3 INTREQ,ABOOT SD_WE 33
PARALLEL 129 CS,GPIO9
INTERFACE 141 HINBSY,GPIO8 NV_CS,GPIO14 32
120 WR,DS,GPIO10 NV_OE,GPIO15 31
121 RD,R/W,GPIO11 NV_WE,GPIO16 30
130 AO,GPIO13
139 A1,GPIO12 SD_ADDR0, EXTA0 73
116 HDATA0,GPIO0 SD_ADDR1, EXTA1 74
115 HDATA1,GPIO1 SD_ADDR2,EXTA2 75
112 HDATA2,GPIO2 SD_ADDR3,EXTA3 76
105 HDATA3,GPIO3 SD_ADDR4,EXTA4 67
103 HDATA4,GPIO4 SD_ADDR5,EXTA5 66
97 HDATA5,GPIO5 SD_ADDR6,EXTA6 65
96 HDATA6,GPIO6 SD_ADDR7,EXTA7 63
95 HDATA7,GPIO7 SD_ADDR8, EXTA8 62
SD_ADDR9,EXTA9 60
16 FINTREQ SD_ADR10,EXTA10 72
15
12
FCS CS494XX SD_DATA8,EXTA11 56
55
EXTERNAL ROM
FHS0,FWR,FDS SD_DATA9,EXTA12
13 FHS1,FRD,FR/ W SD_DATA10,EXTA13 54
6 FAO,FSCCLK SD_DATA11,EXTA14 53
4 FA1, FSCDIN SD_DATA12, EXTA15 52
29 FDAT0 SD_DATA13,EXTA16 49
27 FDAT1 SD_DATA14,EXTA17 47
24 FDAT2 SD_DATA15,EXTA18 46
22 FDAT3 SD_BA,EXTA19 71
19 FDAT4
18 FDAT5 SD_DAT0,EXTD0 34
14 FDAT6 SD_DAT1,EXTD1 35
9 FDAT7 SD_DAT2, EXTD2 36
99 MCLK SD_DATA3, EXTD3 37
117 CMPREQ,FLRCLKN2 SD_DATA4,EXTD4 38
ADC OR SPDIF RX 111
118
CMPCLK,FSCLKN2 SD_DATA5,EXTD5 40
43
CMPDAT,FSDATAN2 SD_DATA6,EXTD6
SD_DATA7,EXTD7 44
119 FLRCLKN1
ADC 134
131
FSCLKN1,STCCLK2
FSDATAN1
SCLK0 104
85 LRCLKN,GPIO23 LRCLK0 108
86 SCLKN,GPIO22 AUDATA0 110
82 SDATAN0,GPIO24 AUDATA1 109
6 DACs
ADCs 81
80
SDATAN1,GPIO25 AUDATA2 107
106
SDATAN2,GPIO26 AUDAT3,XMT958A
79 SDATAN3,GPIO27
98
2 SPDIF TX
SCLK1
OSCILLATOR +2.5 VA
127
126
CLKIN,XTALI LRCLK1 87
102
CLKOUT,XTAL0 AUDATA4,GPIO28
125 PLLVDD AUDATA5,GPIO29 94
123 FILT2 AUDATA6,GPIO30 93
+ 124 92
FILT1 AUDATA7,XMT958B,GPIO31
128 CLKSEL
C1 122 28
PLLVSS TEST
DBCK 26
DBDA 25
143 USH2,CS_OUT,GPIO17
R1 2 23
C2 C3 UHS1,GPIO19 FDBDA
1 UHS0,GPIO18 FDBCK 17
5 GPIO20
VSSSD1
VSSSD2
VSSSD3
VSSSD4

8 GPIO21
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

10
NC1
NC2
NC3
NC4
NC5

2
3
4
5
6
7
8
9

3.3K
101
113
133
137
89
88
84
83
48

91

11
21

69
57
50
41

10K 10K
C

+2.5 VD
1

Figure 29. Motorola® Parallel Control Mode - 144 Pin Package

40
5. CLOCKING 144-Pin Package
The CS49400 clock manager incorporates a UHS2 UHS1 UHS0 Host Interface Mode
programmable phase locked loop (PLL) clock (Pin 143) (Pin 2) (Pin 1)
1 0 1 Serial SPI
synthesizer. The PLL takes an input reference
1 1 0 8-bit Intel®
clock and produces all the clocks required to run
the DSP and peripherals. 1 1 1 8-bit Motorola®
100-Pin Package
In A/V Receiver designs, the CLKIN pin is
UHS2 UHS1 UHS0 Host Interface Mode
typically connected to a 12.288MHz oscillator.
(Pin 99) (Pin 2) (Pin 1)
The clock manager is controlled by the DSPAB 1 0 1 Serial SPI
application software. The software user’s guide for Table 3. Host Modes for DSPC
the application code being used should be
Whichever host communication mode is used, host
referenced for which CLKIN input frequency is
control of the CS49400 is handled through the
supported.
application software running on the DSP.
6. CONTROL Configuration and control of the CS49400 decoder
and its peripherals are indirectly executed through
Control of the CS49400 can be accomplished
a messaging protocol supported by the downloaded
through one of three methods. The CS49400
application code. In other words, successful
supports SPI serial communication and Motorola®
communication can only be accomplished by
and Intel® byte-wide parallel communication.
following the low level hardware communication
Both DSPAB and DSPC have their own control
format and high level messaging protocol. The
ports. Only one of the three communication modes
specifications of the messaging protocol can be
can be selected for control. Both DSPAB and
found in any of the software user’s guides, such as
DSPC use the same communication mode.
AN208 and AN209.
However, please note that the 100-pin package
only supports SPI serial communication. The states The system designer only needs to read the
of the FHS[2:0] for DSPAB and UHS[2:0] for subsection describing the communication mode
DSPC, sampled at the rising edge of RESET, being used. Please note that the communication
determine the communication interface (Table 2.) protocol might be slightly different for DSPAB and
DSPC.
144-Pin Package
FHS2 FHS1 FHS0 Host Interface Mode The following sections will explain each
(Pin 7) (Pin 13) (Pin 12) communication mode in more detail. Flow
1 0 1 Serial SPI diagrams will illustrate read and write cycles.
1 1 0 8-bit Intel® The timing diagrams shown demonstrate relative
1 1 1 ®
8-bit Motorola edge positions of signal transitions for read and
100-Pin Package write operations.
FHS2 FHS1 FHS0 Host Interface Mode
(Pin 6) (Pin 10) (Pin 9) 6.1 Serial Communication
1 0 1 Serial SPI
6.1.1 SPI Communication for DSPAB
Table 2. Host Modes for DSPAB
SPI communication with DSPAB is accomplished
.
with five communication lines: chip select, serial
control clock, serial data in, serial data out, and an
interrupt request line that signals DSPAB has data
to transmit to the host. Table 4 lists the mnemonic,

41
pin name, and pin number of each of these signals for DSPAB defaults to 1000000b. It is
on DSPAB. necessary to clock this address in prior to any
transfer in order for DSPAB to accept the write.
Mnemonic Pin Name 144-Pin 100-Pin In other words a byte of 0x80 should be clocked
Package, Package,
Pin Pin
into the device preceding any write. The 0x80
Number Number byte represents the 7-bit address 1000000b,
Chip Select FCS 15 11 with the least significant bit set to 0 to designate
Serial Clock FSCCLK 6 5 a write.
Serial Data In FSCDIN 4 4
3) The host should then clock data into the device
Serial Data Out FSCDOUT 7 6
most significant bit first, one byte at a time. The
Interrupt
Request FINTREQ 16 12 data byte is transferred from the shift register to
Table 4. SPI Communication Signals for DSPAB
the DSP input register on the falling edge of the
eighth serial clock. For this reason, the serial
6.1.1.1 Writing in SPI for DSPAB clock should default to low so that eight
transitions from low to high to low will occur
When writing to the device in SPI the same
for each byte. A 32 µS byte to byte latency must
protocol will be used whether writing a byte, a
message, or even an entire executable download be obeyed during run time.
image. The examples shown in this document can 4) When all of the bytes have been transferred,
be expanded to fit any write situation. Figure 30, chip select should be raised to signify an end of
"SPI Write Flow Diagram for DSPAB" on page 42 write. Once again it is crucial that the serial
shows a typical write sequence: clock transitions from high to low on the last bit
SPI START: FCS (LO W ) of the last byte before chip select is raised, or a
loss of data will occur.
W RIT E ADDRESS BYTE The same write routine could be used to send a
W ITH MODE BIT
SET TO 0 F OR W RITE
single byte, a message, or an entire application
code image. From a hardware perspective, it makes
no difference whether communication is by byte or
W RIT E DATA BY TE
multiple bytes of any length as long as the correct
hardware protocol is followed.
Y
MORE DATA? 6.1.1.2 Reading in SPI for DSPAB
N
A read operation is necessary when DSPAB signals
that it has data to be read. DSPAB does this by
SPI STO P: FCS (HIGH)
dropping its interrupt request line (FINTREQ) low.
Figure 30. SPI Write Flow Diagram for DSPAB When reading from the device in SPI, the same
protocol will be used whether reading a single byte
The following is a detailed description of an SPI or multiple bytes. The examples shown in this
write sequence with DSPAB. document can be expanded to fit any read situation.
Figure 32, "SPI Read Flow Diagram for DSPAB"
1) An SPI transfer is initiated when chip select
on page 44 shows a typical read sequence:
(FCS) is driven low.
The following is a detailed description of an SPI
2) This is followed by a 7-bit address and the read sequence with DSPAB.
read/write bit set low for a write. The address

42
 F SCCLK

FSCDIN AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

F CS

S PI W rite Functional Tim ing

F SCCLK

F SCDIN AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W

F SCDOUT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

F CS

F INTREQ

SPI Read Functional Tim ing Note 1 Note 2

Notes: 1. FINTREQ is guaranteed to stay LOW until the rising edge of FSCCLK for bit D1 of the last byte
to be transferred out of the CS49400.
2. FINTREQ is guaranteed to remain HIGH until the next rising edge of FSCCLK at which point
it may go LOW again if there is new data to be read. The condition of FINTREQ going LOW at
this point should be treated as a new read condition. After a stop condition, a new start
condition and an address byte should be sent

Figure 31. SPI Timing for DSPAB

43
 to designate a read.
4) After the falling edge of the serial control clock
(FSCCLK) for the read/write bit, the data is
N ready to be clocked out on the control data out
FINTREQ
(LOW )? pin (FCDOUT). Data clocked out by the host is
valid on the rising edge of FSCCLK. Data
Y
transitions occur on the falling edge of
FCS LOW FSCCLK. The serial clock should be default
low so that eight transitions from low to high to
low will occur for each byte.
W RITE ADD RES S BYTE
W ITH MODE BIT SET TO
5) If FINTREQ is still low, another byte should be
1 FOR READ clocked out of DSPAB. Please see the
discussion below for a complete description of
FINTREQ behavior.
READ DA TA BYTE
6) When FINTREQ is released, the chip select
line of DSPAB should be taken high to end the
read transaction.
Y
FINTRE Q STILL Understanding the role of FINTREQ is important
LO W ?
for successful communication. FINTREQ is
guaranteed to remain low (once it has gone low)
N until the second to last rising edge of FSCCLK of
the last byte to be transferred out of DSPAB. If
FCS HIGH
there is no more data to be transferred, FINTREQ
will go high at this point. For SPI this is the rising
Figure 32. SPI Read Flow Diagram for DSPAB edge for the second to last bit of the last byte to be
transferred. After going high, FINTREQ is
guaranteed to stay high until the next rising edge of
1) An SPI read transaction is initiated by DSPAB FSCCLK. This end of transfer condition signals the
dropping FINTREQ, signaling that it has data host to end the read transaction by clocking the last
to be read. data bit out and raising FCS. If FINTREQ is still
2) The host responds by driving chip select (FCS) low after the second to last rising edge of FSCCLK,
low. the host should continue reading data from the
serial control port.
3) This is followed by a 7-bit address and the
It should be noted that all data should be read out of
read/write bit set high for a read. The address
the serial control port during one transaction or a
for DSPAB defaults to 1000000b. It is loss of data will occur. In other words, all data
necessary to clock this address in prior to any should be read out of the chip until FINTREQ
transfer in order for DSPAB to acknowledge signals the last byte by going high as described
the read. In other words a byte of 0x81 should above. Please see Section 6.1.3 “FINTREQ
be clocked into the device preceding any read. Behavior: A Special Case” on page 48 for a more
The 0x81 byte represents the 7-bit address detailed description of FINTREQ behavior.
1000000b, and the least significant bit set to 1

44
Figure 31, "SPI Timing for DSPAB" on page 43
timing diagram shows the relative edges of the SPI START: SCS (LOW)
control lines for an SPI read and write.
6.1.2 SPI Communication for DSPC WRITE ADDRESS BYTE
WITH MODE BIT
SET TO 0 FOR WRITE
SPI communication with the DSPC is
accomplished with five communication lines: chip
select, serial control clock, serial data in, serial data
WRITE 4 DATA BYTES
out, and an interrupt request line that signals DSPC
has data to transmit to the host. Table 5 lists the
mnemonic, pin name, and pin number of each of MORE DATA?
Y HINBSY N

these signals on DSPC. (HIGH)?

N Y
Mnemonic Pin Name 144-Pin 100-Pin
Package, Package, SPI STOP: SCS (HIGH)
Pin Pin
Number Number Figure 33. SPI Write Flow Diagram for DSPC
Chip Select SCS 135 93
Serial Clock SCCLK 142 98 1) An SPI transfer is initiated when chip select
Serial Data In SCDIN 136 94 (SCS) is driven low.
Serial Data Out SCDOUT 140 97 2) This is followed by a 7-bit address and the
Host Busy HINBSY 141 N/A read/write bit set low for a write. The address
Interrupt for DSPC defaults to 1000001b. It is necessary
Request INTREQ 3 3
to clock in this address prior to any transfer in
Table 5. SPI Communication Signals for DSPC
order for DSPC to accept the write. In other
6.1.2.1 Writing in SPI for DSPC words a byte of 0x82 should be clocked into the
device preceding any write. The 0x82 byte
When writing to the device in SPI the same represents the 7-bit address 1000001b, and the
protocol will be used whether writing a byte, a least significant bit set to 0 to designate a write.
message or even an entire executable download
image. The examples shown in this document can 3) The host should then clock data into the device
be expanded to fit any write situation. Figure 33, most significant bit first, four bytes at a time.
"SPI Write Flow Diagram for DSPC" on page 45 The data byte is transferred to the DSP on the
shows a typical write sequence falling edge of the eighth serial clock. For this
The following is a detailed description of an SPI
write sequence with DSPC.

45
 reason, the serial clock should default to low so
that eight transitions from low to high to low
will occur for each byte.
4) When all 4 data bytes have been transferred, N
INTREQ (LO W )?
chip select should be raised to signify an end of
write. Once again it is crucial that the serial
Y
clock transitions from high to low on the last bit
of the last byte before chip select is raised, or a SCS LO W
loss of data will occur.
5) If more data needs to be sent, the host must
W RITE ADD RESS BYTE
verify that the HINBSY pin is low before it
W ITH MODE BIT S ET TO
sends more data to DSPC. Note the HINBSY 1 FOR RE AD
pin is available only on the 144 pin devices. A
32 µS byte to byte latency must be obeyed
during run time for the 100 pin devices. REA D 4 DA TA BYTES

The same write routine could be used to send a 4-

byte message or an entire application code image.
From a hardware perspective, communication must Y
be in 4-byte multiples. INTREQ STILL LOW ?

6.1.2.2 Reading in SPI for DSPC

N
A read operation is necessary when DSPC signals
that it has data to be read. DSPC does this by SCS HIGH
dropping its interrupt request line (INTREQ) low.
When reading from the device in SPI, the same Figure 35. SPI Read Flow Diagram for DSPC
protocol will be used whether reading a single byte
or multiple bytes. The examples shown in this
document can be expanded to fit any read situation. order for DSPC to acknowledge the read. In
Figure 35, "SPI Read Flow Diagram for DSPC" on other words a byte of 0x83 should be clocked
page 46 shows a typical read sequence: into the device preceding any read. The 0x83
The following is a detailed description of an SPI byte represents the 7 bit address 1000001b, and
read sequence with DSPC. the least significant bit set to 1 designates a
1) An SPI read transaction is initiated by DSPC read.
dropping INTREQ, signaling that it has data to 4) After the falling edge of the serial control clock
be read. (SCCLK) for the read/write bit, the data is
2) The host responds by driving chip select (SCS) ready to be clocked out on the control data out
low. pin (CDOUT). Data clocked out by the host is
valid on the rising edge of SCCLK and data
3) This is followed by a 7-bit address and the
transitions occur on the falling edge of SCCLK.
read/write bit set high for a read. The address
The serial clock should default to low so that
for DSPC defaults to 1000001b. It is necessary
eight transitions from low to high to low will
to clock this address in prior to any transfer in
occur for each byte.

46
 SCCLK

SCDIN AD 6 AD 5 A D4 AD 3 AD 2 AD 1 AD 0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 7 D6 D5 D4 D3 D2 D1 D0

S CS

S P I W rite F u n c tio n a l T im ing

SCCLK

SCDIN AD 6 AD 5 A D 4 AD 3 A D2 AD 1 AD 0 R /W

SCDOUT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

S CS

INTREQ

Note 1 Note 2
S P I R e a d F u n c tio n a l T im in g

Notes: 1. INTREQ is guaranteed to stay LOW until the rising edge of SCCLK for bit D1 of the last byte
to be transferred out of DSPC.
2. INTREQ is guaranteed to remain HIGH until the next rising edge of SCCLK at which point it
may go LOW again if there is new data to be read. The condition of INTREQ going LOW at this
point should be treated as a new read condition. After a stop condition, a new start condition
and an address byte should be sent

Figure 34. SPI Timing for DSPC

47
5) If INTREQ is still low after 4 bytes, another 4 high for one period of FSCCLK and then goes low
bytes should be clocked out of DSPC. again before the end of the read cycle.
6) When INTREQ is released, the chip select line In case (1) the host should perform a read operation
of DSPC should be taken high to end the read as discussed in the previous sections.
transaction. In case (2) an unsolicited message arrives before
the second to last FSCCLK of the final byte
All messages read back from DSPC will be in 4-
transfer of a read, forcing the FINTREQ pin to
byte multiples.
remain low. In this scenario the host should
6.1.3 FINTREQ Behavior: A Special Case continue to read from DSPAB without a stop/start
condition or data will be lost.
When communicating with DSPAB there are two
types of messages which force FINTREQ to go In case (3) an unsolicited message arrives between
low. These messages are known as solicited the second to last FSCCLK and the last FSCCLK
messages and unsolicited messages. For more of the final byte transfer of a read. In this scenario,
information on the specific types of messages that FINTREQ will transition high for one clock (as if
require a read from the host, one of the application the read transaction has ended), and then back low
code user’s guides should be referenced. (indicating that more data has queued). This final
case is the most complicated and shall be explained
In general, when communicating with DSPAB, in detail.
FINTREQ will not go low unless the host first
sends a read request command message. In other There are two constraints which completely
words the host must solicit a response from the characterize the behavior of the FINTREQ pin
DSP. In this environment, the host must read from during a read. The first constraint is that the
DSPAB until FINTREQ goes high again. Once the FINTREQ pin is guaranteed to remain low until the
FINTREQ pin has gone high it will not be driven second to last FSCCLK (FSCCLK number N-1) of
low until the host sends another read request. the final byte being transferred from DSPAB (not
necessarily the second to last bit of the data byte).
When unsolicited messages, such as those used for The second constraint is that once the FINTREQ
Autodetect, have been enabled, the behavior of pin has gone high it is guaranteed to remain high
FINTREQ is noticeably different. DSPAB will until the rising edge of the last FSCCLK (FSCCLK
drop the FINTREQ pin whenever it has an number N) of the final byte being transferred from
outgoing message, even though the host may not DSPAB (not necessarily the last bit of the data
have requested data. byte). If an unsolicited message arrives in the
There are three ways in which FINTREQ can be window of time between the rising edge of the
affected by an unsolicited message: second to last FSCCLK and the final FSCCLK,
1) During normal operation, while FINTREQ is FINTREQ will drop low on the rising edge of the
high, DSPAB could drop FINTREQ to indicate an final FSCCLK as illustrated in the functional
outgoing message, without a prior read request. timing diagram shown for the SPI read cycle.
2) The host is in the process of reading from FINTREQ behavior for SPI communication is
DSPAB, meaning that FINTREQ is already low. illustrated in Figure 31, "SPI Timing for DSPAB"
An unsolicited message arrives which forces on page 43. When using SPI communication, the
FINTREQ to remain low after the solicited FINTREQ pin will remain low until the rising edge
message is read. of FSCCLK for the data bit D1 (FSCCLK N-1), but
3) The host is reading from DSPAB when the it can go low at the rising edge of FSCCLK for data
unsolicited message is queued, but FINTREQ goes bit D0 (FSCCLK N) if an unsolicited message has

48
arrived. If no unsolicited messages arrive, the NULL byte (0x00) detected in the OPCODE
FINTREQ pin will remain high after rising. position of a read response message should be
Ideally, the host will sample FINTREQ on the discarded. Please see an Application Code User’s
falling edge of FSCCLK number N-1 of the final Guide for an explanation of the OPCODE.
byte of each read response message. If FINTREQ It is important that the host be aware of the
is sampled high, the host should conclude the presence of NULL bytes, or the communication
current read cycle using the stop condition defined channel could become corrupted.
for the communication mode chosen. The host When case (3) occurs and the host issues a stop
should then begin a new read cycle complete with condition before starting a new read cycle, the first
the appropriate start condition and the chip address. byte of the unsolicited message is loaded directly
If FINTREQ is sampled low, the host should into the shift register and 0x00 is never seen.
continue reading the next message from DSPAB
Alternatively, if case (3) occurs and the host
without ending the current read cycle.
continues to read from DSPAB without a stop
When using automated communication ports, condition (a multiple message read), the 0x00 byte
however, the host is often limited to sampling the must be shifted out of DSPAB before the first byte
status of FINTREQ after an entire byte has been of the unsolicited message can be read.
transferred. In this situation a low-high-low
transition (case 3) would be missed and the host In other words, if a host can only sample FINTREQ
after an entire byte transfer the following routine
will see a constantly low FINTREQ pin. Since the
host should read from DSPAB until it detects that should be used if FINTREQ is low after the last
FINTREQ has gone high, this condition will be byte of the message being read:
treated as a multiple-message read (more than one 1) Read one byte
read response is provided by DSPAB). Under these 2) If the byte = 0x00 discard it and skip to step 3.
conditions a single byte of 0x00 will be read out If the byte != 0x00 then it is the OPCODE for
before the unsolicited message. the next message. For this case skip to step 4.
The length of every read response is defined in the
3) Read one more byte. This is the OPCODE for
user’s manual for each piece of application code.
Thus, the host should know how many bytes to the next message.
expect based on the first byte (the OPCODE) of a 4) Read the rest of the message as indicated in the
read response message. It is guaranteed that no read previous sections.
responses will begin with 0x00, which means that a

49
6.2 Parallel Host Communication for • Flow diagram and description for a parallel
DSPAB byte read
The parallel host communication modes of DSPAB The four registers of DSPAB’s parallel host mode
provide an 8-bit interface to the DSP. An Intel-style are not used identically. The algorithm used for
parallel mode and a Motorola-style parallel mode communicating with each register will be given as
are supported. The host interface is implemented a functional description, building upon the basic
using four communication registers within DSPAB read and write protocols defined in the Motorola
as shown in Table 6, “Parallel Input/Output and Intel sections. The following will be covered:
Registers for DSPAB,” on page 51. • Flow diagram and description for a control
When the host is downloading code to DSPAB or write
configuring the application code, control messages
• Flow diagram and description for a control read
will be written to (and read from) the Host Message
register. The Host Control register is used during 6.2.5 Intel Parallel Host Communication
messaging sessions to determine when DSPAB can Mode for DSPAB
accept another byte of control data, and when
DSPAB has an outgoing byte that should be read. The Intel parallel host communication mode is
implemented using the pins given in Table 6.
All communication to DSPAB after download is in
Parallel host communication is available only on
24-bit words. Reads and writes are done in
the 144-pin package part.
multiples of 3-byte transactions. A 3-byte
transaction is accomplished by doing three
Mnemonic Pin Name 144-Pin
consecutive byte reads or byte writes. Package,
The PCM Data and Compressed Data registers are Pin
used strictly for the transfer of audio data. The host Number
cannot read from these two registers. Audio data Chip Select FCS 15
written to registers 11b and 10b are transferred Write Enable FWR 12
directly to the internal FIFOs of DSPAB. When the Output Enable FRD 13
level of the PCM FIFO reaches the FIFO threshold Register Address Bit 1 FA1 4
level, the MFC bit of the Host Control register will Register Address Bit 0 FA0 6
be set. When the level of the Compressed Data Interrupt Request FINTREQ 16
FIFO reaches the FIFO threshold level, the MFB DATA7 FDAT7 9
bit of the Host Control register will be set. Writing DATA6 FDAT6 14
data directly to the FIFOs is only supported in DATA5 FDAT5 18
specific applications. To see if an application DATA4 FDAT4 19
supports this feature, consult the appropriate DATA3 FDAT3 22
Application Note. DATA2 FDAT2 24
DATA1 FDAT1 27
A detailed description for each parallel host mode
DATA0 FDAT0 29
will now be given. The following information will
Table 6. Intel Mode Communication Signals for DSPAB
be provided for the Intel mode and Motorola mode:
• The pins of DSPAB which must be used for The HOUTRDY bit of the Host Control Register
proper communication (A[1:0] = 01b) indicates that the DSP has a
• Flow diagram and description for a parallel message for the host to read. The FINTREQ pin
can be controlled by the application code, and
byte write
allows for another method of requesting that the

50
6.2.1 Host Message (HOSTMSG) Register, A[1:0] = 00b
7 6 5 4 3 2 1 0
HOSTMSG7 HOSTMSG6 HOSTMSG5 HOSTMSG4 HOSTMSG3 HOSTMSG2 HOSTMSG1 HOSTMSG0

HOSTMSG7–0 Host data to and from the DSP. A read or write of this register operates handshake bits be-
tween the internal DSP and the external host. This register typically passes multibyte messages
carrying microcode, control, and configuration data (messages are written MSB first). HOST-
MSG is physically implemented as two independent registers for input and output (Read and
write).

6.2.2 Host Control (CONTROL) Register, A[1:0] = 01b

7 6 5 4 3 2 1 0
Reserved CMPRST PCMRST MFC MFB HINBSY HOUTRDY Reserved

Reserved Always write a 0 for future compatibility.

CMPRST When set, initializes the CMPDATA compressed data input channel. Writing a one to this bit
holds the port in reset. Writing zero enables the port. This bit must be low for normal operation.
(Write only)
PCMRST When set, initializes the PCMDATA linear PCM input channel. Writing a one to this bit holds the
port in reset. Writing zero enables the port. This bit must be low for normal operation. (Write
only)
MFC When high, indicates that the PCMDATA input buffer is almost full. (Read only)
MFB When high, indicates that the CMPDATA input buffer is almost full. (Read only)
HINBSY Set when the host writes to HOSTMSG. Cleared when the DSP reads data from the HOSTMSG
register. The host reads this bit to determine if the last host byte written has been read by the
DSP. (Read only)
HOUTRDY Set when the DSP writes to the HOSTMSG register. Cleared when the host reads data from
the HOSTMSG register. The DSP reads this bit to determine if the last DSP output byte has
been read by the host. (Read only)
Reserved Always write a 0 for future compatibility.

6.2.3 PCM Data Input (PCMDATA) Register, A[1:0] = 10b

7 6 5 4 3 2 1 0
PCMDATA7 PCMDATA6 PCMDATA5 PCMDATA4 PCMDATA3 PCMDATA2 PCMDATA1 PCMDATA0

PCMDATA7–0 The host writes PCM data to the DSP input buffer at this address. (Write only)

6.2.4 Compressed Data Input (CMPDATA) Register, A[1:0] = 11b

7 6 5 4 3 2 1 0
CMPDATA7 CMPDATA6 CMPDATA5 CMPDATA4 CMPDATA3 CMPDATA2 CMPDATA1 CMPDATA0
Table 6. Parallel Input/Output Registers for DSPAB

51
 1) The host must first drive the FA1 and FA0
ADDRESS A PARALLEL I/O REGISTER
(FA[1:0] SET APPROPRIATELY) register address pins of DSPAB with the
address of the desired Parallel I/O Register. The
address must be maintained for the duration of
the write cycle.
FCS (LOW)
FWR (LOW) Host Message: FA[1:0]==00b.
Host Control: FA[1:0]==01b.
PCMDATA: FA[1:0]==10b.
WRITE BYTE TO
FDAT[7:0] CMPDATA: FA[1:0]==11b.
2) The host then indicates that the selected register
will be written. The host initiates a write cycle
FCS (HIGH)
by driving the FCS and FWR pins low.
FWR (HIGH) 3) The host drives the data byte to the FDAT[7:0]
pins of DSPAB.
Figure 36. Intel Mode, One-Byte Write Flow Diagram
for DSPAB 4) Once the setup time for the write has been met,
the host ends the write cycle by driving the FCS
host read a message. When the code supports
and FWR pins high.
FINTREQ notification, the FINTREQ pin is
asserted (driven low) when the DSP has an 6.2.5.2 Reading a Byte in Intel Mode for DSPAB
outgoing message for the host.
Information provided in this section is intended as
FINTREQ is useful for informing the host of a functional description of how to read control
unsolicited messages without polling. An information from DSPAB. The system designer
unsolicited message is defined as a message must ensure that all of the timing constraints of the
generated by the DSP without an associated host Intel Parallel Host Mode Read Cycle are met.
read request. Unsolicited messages are used to
notify the host of conditions such as a change in the The flow diagram shown in Figure 37 illustrates
incoming audio data type (e.g. PCM --> AC-3). the sequence of events that define a one-byte read
Most unsolicited messages must be specifically in Intel mode. The protocol presented in Figure 37
enabled by setting the appropriate bit in the will now be described in detail.
application’s manager, enabling autodetection, or 1) The host must first drive the FA1 and FA0
enabling other host notification capabilities. register address pins of DSPAB with the
address of the desired Parallel I/O Register.
6.2.5.1 Writing a Byte in Intel Mode for DSPAB
Note that only the Host Message register and
Information provided in this section is intended as the Host Control register can be read. The
a functional description of how to write control address must be maintained for the duration of
information to DSPAB. The system designer must the read cycle.
ensure that all of the timing constraints of the Intel
Parallel Host Mode Write Cycle are met. Host Message: FA[1:0]==00b.
The flow diagram shown in Figure 36 illustrates Host Control: FA[1:0]==01b.
the sequence of events that define a one-byte write 2) The host initiates a read cycle by driving the
in Intel mode. The protocol presented in Figure 36 FCS and FRD pins low (bus must be tri-stated
will now be described in detail.

52
 ADDRESS A PARALLEL I/O REGISTER Mnemonic Pin Name 144-Pin
(FA[1:0] SET APPROPRIATELY) Package,
Pin
Number
Chip Select FCS 15
FCS (LOW) Data Strobe FDS 12
FRD (LOW)
Read or Write Select FR/W 13
Register Address Bit 1 FA1 4
Register Address Bit 0 FA0 6
READ BYTE FROM Interrupt Request FINTREQ 16
FDAT[7:0]
DATA7 FDAT7 9
DATA6 FDAT6 14
DATA5 FDAT5 18
FCS (HIGH) DATA4 FDAT4 19
FRD (HIGH) DATA3 FDAT3 22
DATA2 FDAT2 24
Figure 37. Intel Mode, One-Byte Read Flow Diagram
for DSPAB DATA1 FDAT1 27
DATA0 FDAT0 29
before this occurs). Table 7. Motorola Mode Communication Signals for
DSPAB
3) Once the data is valid (after waiting the
appropriate time specified in the timing FINTREQ is useful for informing the host of
specifications), the host can read the value of unsolicited messages. An unsolicited message is
the selected register from the FDAT[7:0] pins defined as a message generated by the DSP without
of DSPAB. an associated host read request. Unsolicited
messages are used to notify the host of conditions
4) The host should now terminate the read cycle such as a change in the incoming audio data type
by driving the FCS and FRD pins high. (e.g. PCM --> AC-3). Most unsolicited messages
must be specifically enabled by setting the
6.2.6 Motorola Parallel Communication appropriate bit in the application’s manager,
Mode for DSPAB enabling autodetection, or enabling other host
The Motorola parallel host communication mode is notification capabilities.
implemented using the pins given in Table 7.
6.2.6.1 Writing a Byte in Motorola Mode
Parallel host communication is available only on
the 144-pin package part . Information provided in this section is intended as
The HOUTRDY bit of the Host Control Register a functional description of how to write control
(A[1:0] = 01b) indicates that the DSP has a information to DSPAB. The system designer must
message for the host to read. The FINTREQ pin ensure that all of the timing constraints of the
can be controlled by the application code, and Motorola Parallel Host Mode Write Cycle are met.
allows for another method of requesting that the The flow diagram shown in Figure 38 illustrates
host read a message. When the code supports the sequence of events that define a one-byte write
FINTREQ notification, the FINTREQ pin is in Motorola mode. The protocol presented in
asserted (driven low) whenever the DSP has an Figure 38 will now be described in detail.
outgoing message for the host. 1) The host must drive the FA1 and FA0 register
address pins of DSPAB with the address of the

53
 address of the desired Parallel I/O Register. The protocol presented in Figure 39 will now be
address must be maintained for the duration of described in detail.
the read cycle. 1) The host must drive the FA1 and FA0 register
Host Message: FA[1:0]==00b. address pins of DSPAB with the address of the
desired Parallel I/O Register. Note that only the
Host Control: FA[1:0]==01b.
Host Message register and the Host Control
PCMDATA: FA[1:0]==10b. register can be read. The address must be
CMPDATA: FA[1:0]==11b. maintained for the duration of the read cycle.
2) The host indicates that this is a write cycle by Host Message: FA[1:0]==00b.
driving the FR/W pin low. Host Control: FA[1:0]==01b.
3) The host initiates a write cycle by driving the 2) The host indicates that this is a read cycle by
FCS and FDS pins low. driving the FR/W pin high.
4) The host drives the data byte to the FDAT[7:0] 3) The host initiates the read cycle by driving the
pins of DSPAB. FCS and FDS pins low (bus must be tri-stated
5) Once the setup time for the write has been met, by this time).
the host ends the write cycle by driving the FCS 4) Once the data is valid (after waiting the
and FDS pins high. appropriate time specified in the timing
specifications), the host can read the value of
6.2.6.2 Reading a Byte in Motorola Mode
the selected register from the FDAT[7:0] pins
The flow diagram shown in Figure 39, "Motorola of DSPAB.
Mode, One-Byte Read Flow Diagram for DSPAB"
on page 54 illustrates the sequence of events that 5) The host should now terminate the read cycle
define a one-byte read in Motorola mode. The by driving the FCS and FDS pins high.

FR/W (LOW) FR/W (HIGH)

ADDRESS A PARALLEL I/O REGISTER ADDRESS A PARALLEL I/O REGISTER
(FA[1:0] SET APPROPRIATELY) (FA[1:0] SET APPROPRIATELY)

FCS (LOW) FCS (LOW)

FDS (LOW) FDS (LOW)

WRITE BYTE TO READ BYTE FROM

FDAT[7:0] FDAT[7:0]

FCS (HIGH) FCS (HIGH)

FDS (HIGH) FDS (HIGH)

Figure 38. Motorola Mode, One-Byte Write Flow Dia- Figure 39. Motorola Mode, One-Byte Read Flow Di-
gram for DSPAB agram for DSPAB

54
6.2.7 Procedures for Parallel Host Mode 00b) using the selected communication mode
Communication for DSPAB (Intel or Motorola).

6.2.7.1 Control Write in a Parallel Host Mode 4) If the host would like to write any more control
bytes to DSPAB, the host should once again
for DSPAB
poll the Host Control Register (return to step 1).
When writing control data to DSPAB, the same
protocol is used whether the host is writing a 6.2.7.2 Control Read in a Parallel Host Mode
control message or an entire executable download for DSPAB
image. Messages sent to DSPAB should be written When reading control data from DSPAB, the same
most significant byte first. Likewise, downloads of protocol is used whether the host is reading a single
the application code should also be performed most byte, a 6 byte message, or a string of messages.
significant byte first.
During the boot procedure, a handshaking protocol
The example shown in this section can be is used by DSPAB. This handshake consists of a 3
generalized to fit any control write situation. The byte write to DSPAB followed by a 1 byte response
generic function ‘Read_Byte_*()’ is used in the from the DSP. The host must read the response byte
following example as a generalized reference to and act accordingly. The boot procedure is
either Read_Byte_MOT() (read a byte in Motorola discussed in Section 8 “Boot Procedure” on page
mode) or Read_Byte_INT() (read a byte in Intel 71.
mode), and ‘Write_Byte_*()’ is a generic reference
to Write_Byte_MOT() (write a byte in Motorola During regular operation (at run-time), the
mode) or Write_Byte_INT() (write a byte in Intel responses from DSPAB will always be 6 bytes in
mode). Figure 40 shows a typical write sequence. length.
The protocol presented in Figure 40 will now be
described in detail.
READ_BYTE_*(HOST
1) When the host is communicating with DSPAB, CONTROL REGISTER)
the host must verify that DSPAB is ready to
accept a new control byte. If DSPAB has not
Y
read the previous byte from the control port, it HINBSY == 1
will be unable to receive another byte.
N
2) In order to determine whether DSPAB is ready
to accept a new control byte the host must read WRITE_BYTE_*(HOST
the HINBSY bit of the Host Control Register MESSAGE REGISTER)

(bit 2 in FA[1:0]=01b) using the selected

communication mode (Intel or Motorola). If Y
MORE BYTES
HINBSY is high, then the DSP is not prepared TO WRITE?
to accept a new control byte, and the host
N
should poll the Host Control Register again. If
HINBSY is low, then the host may write a FINISHED
control byte into the Host Message Register.
3) Once the host knows that the DSP is ready for
a new control byte, it should write the control
byte to the Host Message Register (FA[1:0] = Figure 40. Typical Parallel Host Mode Control
Write Sequence Flow Diagram for DSPAB

55
The example shown in this section can be used for DSPAB has an outgoing message. Note that
any control read situation. The generic function even with the use of FINTREQ, HOUTRDY
‘Read_Byte_*()’ is used in the following example must be checked to ensure that the current byte
as a generalized reference to either is ready to be read by the host during the read
Read_Byte_MOT() (Motorola byte read) or process. Please note that the state of FINTREQ
Read_Byte_INT() (Intel byte read). Figure 41 is undefined during boot, and it is valid only
shows a typical read sequence. The protocol once the application code is loaded.
presented in Figure 41 will now be described in
detail. 2) The host reads the Host Control Register
(FA[1:0] = 01b) in order to determine the state
F IN T R E Q = 0 ? of the communication interface.
( o p tio n a l)
3) In order to determine whether DSPAB has an
Y
outgoing control byte that is valid, the host
R E A D _ B Y T E _ *( H O S T must check the HOUTRDY bit of the Host
C O N T R O L R E G IS T E R )
Control Register (bit 1, FA[1:0] = 01b). If
HOUTRDY is high, then the Host Message
N Register contains a valid message byte for the
H OUTR DY == 1
host. If HOUTRDY is low, then the DSP has
Y not placed a new control byte in the Host
Message Register, and the host should poll the
R E A D _ B Y T E _ *( H O S T
M E S S A G E R E G IS T E R ) Host Control Register again.
4) Once the host knows that the DSP is ready to
Y
provide a new response byte, the host can
MORE BYTES TO
READ?
safely read a byte from the Host Message
Register (FA[1:0] = 00b) using the appropriate
communication protocol (Motorola or Intel).
N

W A IT 1 0 0 M IC R O S E C 5) If the host expects to read any more response

bytes, the host should once again check the
HOUTRDY bit (return to step 1). Messages
R E A D _ B Y T E _ *( H O S T
C O N T R O L R E G IS T E R ) from the application code (post-download) on
the DSP will always be 6 bytes, unless
otherwise stated in the associated Application
Y
H OUTR DY == 1 Note.
6) After the response has been read the host
N
should wait at least 100 uS and check
F IN IS H E D HOUTRDY one final time. If HOUTRDY is
high once again this means that an unsolicited
Figure 41. Typical Parallel Host Mode Control Read message has come during the read process and
Sequence Flow Diagram for DSPAB
the host has another message to read (i.e. skip
back to step 4 and read out the new message). It
1) Optionally, FINTREQ going low may be used
is the host’s responsibility to insure that any
as an interrupt to the host to indicate that
pending messages are read from the DSP.

56
 Failure to do this may cause the DSP’s output The HOSTDATA1 and HOSTDATA2 registers
message buffer to overflow, corrupting any are used strictly for the transfer of audio data to
pending outbound messages. DSPC. The host cannot read from these two
registers. Support of these registers is DSPC
6.3 Parallel Host Communication for DSPC application code specific, see the appropriate
The parallel host communication modes of DSPC Application Note for availability.
provide an 8-bit interface to the DSP. An Intel-style A detailed description for each parallel host mode
parallel mode and a Motorola-style parallel mode will now be given. The following information will
are supported. The host interface is implemented be provided for the Intel mode and Motorola mode:
using four communication registers within DSPC • The pins of DSPC which must be used for prop-
as shown in Table 8, “Parallel Input/Output er communication
Registers for DSPC,” on page 58. The HOSTMSG
register is a 32 bit register. Since there are only • Flow diagram and description for a parallel
eight data pins, only one byte can be transferred at byte write
a time, but a full 32 bits are transferred in each read • Flow diagram and description for a 32-bit word
or write to this register. (4-byte) write
When the host is downloading code or configuring
• Flow diagram and description for a parallel
the application code in DSPC, control messages
must be written to (and read from) the Host byte read
Message register 32 bits at a time. The HINBSY • Flow diagram and description for a 32-bit word
pin and the HINBSY bit in the Host Control (4-byte) read
register are used during messaging sessions to
The four registers of DSPC’s parallel host mode are
determine when DSPC can accept another 32-bit
not used identically. The algorithm used for
word of control data. The HINBSY pin and the
communicating with each register will be given as
HINBSY bit (in the Host Control register) go high
a functional description, building upon the basic
when the host writes 32 bits (4 bytes) to the
read and write protocols defined in the Motorola
HOSTMSG register. The HINBSY pin and
and Intel sections. The following will be covered:
HINBSY bit go low when DSPC reads the 32 bit
data from the register. The INTREQ pin goes low • Flow diagram and description for a control
and the HOUTRDY bit (in the Host Control write
register) goes high when DSPC has an message that • Flow diagram and description for a control read
must be read by the host.

57
6.3.1 Host Message (HOSTMSG) Register, A[1:0] = 00b
31 30 29 28 27 26 25 24
MS_BYTE
23 22 21 20 19 18 17 16
BYTE_B
15 14 13 12 11 10 9 8
BYTE_A
7 6 5 4 3 2 1 0
LS_BYTE
The HOSTMSG register is a 32-bit register that is all the code, control and configuration data to and
used to read from or write to DSPC. It is read and from DSPC. Messages are read and written
written in 4-byte transactions. This register passes MS_BYTE first.
MS_BYTE This is the most significant byte (bits 31:24).
BYTE_B This is BYTE_B (bits 23:16).
BYTE_A This is BYTE_A (bits 15:8).
LS_BYTE This is the least significant byte (bits 7:0).

6.3.2 Host Control (CONTROL) Register, A[1:0] = 01b

7 6 5 4 3 2 1 0
Reserved Reserved Reserved BYTE_SEL HINBSY HOUTRDY Reserved

Reserved Always write a 0.

BYTE_SEL Always write a 11b to these bits.
HINBSY This bit is the Host Input Ready signal. It is set when the host writes to the HOSTMSG register.
It is cleared when DSPC reads the HOSTMSG register. This bit is also pinned out on the
HINBSY pin. Read only by the host and DSPC.
HOUTRDY This bit is set when DSPC writes data to the HOST_MSG register, and indicates that the DSP
has a pending message for the host. The HOUTRDY bit is cleared when the host reads the
HOSTMSG register. The bit is inverted and pinned out on the INTREQ pin. Read only by the
host and DSPC

6.3.3 Host Data1 Input (HOSTDATA1) Register, A[1:0] = 10b

7 6 5 4 3 2 1 0
HOSTDATA1_ HOSTDATA1_ HOSTDATA1_ HOSTDATA1_ HOSTDATA1_ HOSTDATA1_ HOSTDATA1_ HOSTDATA1_
7 6 5 4 3 2 1 0

HOSTDATA1_7–0 The host writes data to DSPC at this address. (Write only)

6.3.4 Host Data2 Input (HOSTDATA2) Register, A[1:0] = 11b

7 6 5 4 3 2 1 0
HOSTDATA2_ HOSTDATA2_ HOSTDATA2_ HOSTDATA2_ HOSTDATA2_ HOSTDATA2_ HOSTDATA2_ HOSTDATA2_
7 6 5 4 3 2 1 0

HOSTDATA2_7–0 The host writes data to DSPC at this address. (Write only)
Table 8. Parallel Input/Output Registers for DSPC

58
6.3.5 Intel Parallel Host Communication
ADDRESS A PARALLEL I/O REGISTER
Mode for DSPC (A[1:0] SET APPROPRIATELY)
The Intel parallel host communication mode is
implemented using the pins given in Table 9.
Parallel host communication is available only on
CS (LOW )
the 144-pin package version of the CS49400. W R (LOW )
The INTREQ pin is asserted (driven low)
whenever the DSP has an outgoing message for the
host. This same information is reflected by the
W RITE BYTE TO
HOUTRDY bit of the Host Control Register
HDAT[7:0]
(A[1:0] = 01b).
INTREQ is useful for informing the host of
unsolicited messages. An unsolicited message is
defined as a message generated by the DSP without CS (HIGH)
W R (HIGH)
an associated host read request.
Figure 42. Intel Mode, One-Byte Write Flow Diagram
Mnemonic Pin Name 144-Pin for DSPC
Package,
Pin
Number
The flow diagram shown in Figure 42 illustrates
Chip Select CS 129
the sequence of events that define a one-byte write
Write Enable WR 120
in Intel mode. One-byte writes should only be
Output Enable RD 121
perfomed to the Host Control and Host Data
Register Address Bit 1 A1 139
registers. The protocol presented in Figure 42 will
Register Address Bit 0 A0 130
now be described in detail.
Interrupt Request INTREQ 3 1) The host must first drive the A1 and A0 register
Host Busy HINBSY 141 address pins of DSPC with the address of the
DATA7 HDAT7 95 desired Parallel I/O Register. The address is
DATA6 HDAT6 96 latched on the falling edge of CS.
DATA5 HDAT5 97
Host Control: A[1:0]==01b.
DATA4 HDAT4 103
DATA3 HDAT3 105 Host Data1: A[1:0]==10b.
DATA2 HDAT2 112
Host Data2: A[1:0]==11b.
DATA1 HDAT1 115
DATA0 HDAT0 116 2) The host initiates a write cycle by driving the
Table 9. Intel Mode Communication Signals for DSPC CS and WR pins low.
3) The host drives the data byte to the HDAT[7:0]
6.3.5.1 Writing a Byte in Intel Mode for DSPC pins of DSPC.
Information provided in this section is intended as 4) Once the setup time for the write has been met,
a functional description of how to write control
the host ends the write cycle by driving the WR
information to DSPC. The system designer must
and CS pins high.
ensure that all of the timing constraints of the Intel
Parallel Host Mode Write Cycle are met.

59
6.3.5.2 Writing a 32-bit (4-byte) Word in Intel
ADDRESS A PARALLEL I/O REGISTER
Mode for DSPC (A[1:0] SET APPROPRIATELY)

Information provided in this section is intended as

a functional description of how to write control
information to DSPC. The system designer must CS (LOW)
RD (LOW)
ensure that all of the timing constraints of the Intel
Parallel Host Mode Write Cycle are met.
The flow diagram shown in Figure 43 illustrates
READ BYTE FROM
the sequence of events that define a 4-byte write in HDAT[7:0]
Intel mode. 32-bit (4-byte) writes should only be
used to write to the Host Message register. The
protocol presented in Figure 43 will now be CS (HIGH)
described in detail. RD (HIGH)

1) The host must first drive the A1 and A0 register

address pins of DSPC with the address of the Figure 44. Intel Mode, One-Byte Read Flow Diagram
desired Parallel I/O Register (both low for for DSPC
A1=A0=0). The address must be maintained
for the duration of the write cycle, and is 10) Once the setup time for the write has been met,
latched on the falling edge of CS and WR. the host drives WR high to strobe in the data
Host Message: A[1:0]==00b. byte.
2) The host initiates a write cycle by driving the 11) The host drives WR low.
CS and WR pins low. 12) The host drives the least significant data byte
3) The host drives the most significant data byte (bits 7:0) to the HDAT[7:0] pins of DSPC.
(bits 31:24) to the HDAT[7:0] pins of DSPC. 13) Once the setup time for the write has been met,
4) Once the setup time for the write has been met, the host drives WR high to strobe in the data
the host drives WR high to strobe in the most byte.
significant data byte. 14) The host drives CS high to end the write
5) The host drives WR low. transaction.
6) The host drives the next most significant data 6.3.5.3 Reading a Byte in Intel Mode for DSPC
byte, BYTE_B (bits 23:16), to the HDAT[7:0] Information provided in this section is intended as
pins of DSPC. a functional description of how to read control
7) Once the setup time for the write has been met, information from DSPC. The system designer must
the host drives WR high to strobe in the data ensure that all of the timing constraints of the Intel
byte. Parallel Host Mode Read Cycle are met.
8) The host drives WR low. The flow diagram shown in Figure 44 illustrates
the sequence of events that define a one-byte read
9) The host drives the next most significant data in Intel mode. One-byte reads should only be done
byte, BYTE_A (bits 15:8), to the HDAT[7:0] with the Host Control register. The protocol
pins of DSPC. presented in Figure 44 will now be described in
detail.

60
 ADDRESSAPARALLELI/OREGISTER
1) The host must first drive the A1 and A0 register
(A[1:0] SETAPPROPRIATELY) address pins of DSPC with the address of the
desired Parallel I/O Register (A1=0, A0=1).
CS(LOW) Note that only the Host Control register can be
WR(LOW) read using a byte read. The address must be
maintained for the duration of the read cycle,
WRITEMS_BYTETO and is latched on the falling edge of CS.
HDAT[7:0]
Host Control: A[1:0]==01b.
2) The host initiates a read cycle by driving the CS
WR(HIGH)
and RD pins low (bus must be tri-stated by this
time).
WR(LOW) 3) Once the data is valid (after waiting the
appropriate time specified in the timing
specifications), the host can read the value of
WRITEBYTE_BTO
HDAT[7:0] the selected register from the HDAT[7:0] pins
of DSPC.
WR(HIGH) 4) The host should now terminate the read cycle
by driving the CS and RD pins high.
6.3.5.4 Reading a 32-bit (4-byte) Word from
WR(LOW)
DSPC in Intel Mode
Information provided in this section is intended as
WRITEBYTE_ATO
HDAT[7:0] a functional description of how to read control
information from DSPC. The system designer must
ensure that all of the timing constraints of the Intel
WR(HIGH) Parallel Host Mode Read Cycle are met.
The flow diagram shown in Figure 45, "Intel
Mode, 32-Bit (4-Byte) Read Flow Diagram for
WR(LOW) DSPC" on page 62 illustrates the sequence of
events that define a 4-byte read in Intel mode. 4-
byte (32-bit) reads should only be done with the
WRITELS_BYTETO
HDAT[7:0] Host Message register. The protocol presented in
Figure 45 will now be described in detail.
1) The host must first drive the A1 and A0 register
WR(HIGH)
address pins of DSPC with the address of the
desired Parallel I/O Register (A1=A0=0). Note
CS(HIGH)
that only the Host Message register can be read
using a 4-byte read cycle. The address must be
Figure 43. Intel Mode, 32-bit (4-byte) Write Flow
maintained for the duration of the read cycle,
Diagram for DSPC and is latched on the falling edge of CS.
Host Message: A[1:0]==00b.

61
 ADDRESS A PARALLEL I/O REGISTER
2) The host initiates a read cycle by driving the CS
(A[1:0] SET APPROPRIATELY) and RD pins low (bus must be tri-stated by this
time).
CS (LOW) 3) Once the data is valid (after waiting the
RD (LOW)
appropriate time specified in the timing
specifications), the host can read the most
READ MS_BYTE FROM
HDAT[7:0] significant data byte (bits 31:24) from the
HDAT[7:0] pins of DSPC.
4) The host drives RD high to indicate that the
RD (HIGH)
data byte has been read.
5) The host drives RD low to clock out the next
RD (LOW) data byte.
6) Once the data is valid (after waiting the
READ BYTE_B FROM appropriate time specified in the timing
HDAT[7:0]
specifications), the host can read BYTE_B (bits
23:16) from the HDAT[7:0] pins of DSPC.
RD (HIGH) 7) The host drives RD high to indicate that the
data byte has been read.

RD (LOW)
8) The host drives RD low to clock out the next
data byte.
9) Once the data is valid (after waiting the
READ BYTE_A FROM
HDAT[7:0] appropriate time specified in the timing
specifications), the host can read BYTE_A
(bits 15:8) from the HDAT[7:0] pins of DSPC.
RD (HIGH)
10) The host drives RD high to indicate that the
data byte has been read.
RD (LOW) 11) The host drives RD low to clock out the next
data byte.
READ LS_BYTE FROM 12) Once the data is valid (after waiting the
HDAT[7:0]
appropriate time specified in the timing
specifications), the host can read the least
RD (HIGH) significant data byte (bits 7:0) from the
HDAT[7:0] pins of DSPC.
13) The host drives RD high to indicate that the
CS (HIGH)
data byte has been read.
Figure 45. Intel Mode, 32-Bit (4-Byte) Read Flow 14) The host should now terminate the read cycle
Diagram for DSPC by driving the CS pin high.

62
6.3.6 Motorola Parallel Host
R/W (LOW )
Communication Mode for DSPC ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY)
The Motorola parallel host communication mode is
implemented using the pins given in Table 10.

Mnemonic Pin Name 144-Pin CS (LOW )

Package, DS (LOW )
Pin
Number
Chip Select CS 129
W RITE BYTE TO
Data Strobe DS 120 HDAT[7:0]
Read or Write Select R/W 121
Register Address Bit 1 A1 139
Register Address Bit 0 A0 130
Interrupt Request INTREQ 3 CS (HIGH)
DS (HIGH)
Host Busy HINBSY 141
DATA7 HDAT7 95 Figure 46. Motorola Mode, One-Byte Write Flow
DATA6 HDAT6 96 Diagram for DSPC
DATA5 HDAT5 96
DATA4 HDAT4 103
6.3.6.1 Writing a Byte in Motorola Mode for
DATA3 HDAT3 105
DATA2 HDAT2 112 DSPC
DATA1 HDAT1 115 Information provided in this section is intended as
DATA0 HDAT0 116 a functional description of how to write control
Table 10. Motorola Mode Communication Signals for information to DSPC. The system designer must
DSPC ensure that all of the timing constraints of the
Motorola Parallel Host Mode Write Cycle are met.
Parallel host communication is available only on The flow diagram shown in Figure 46 illustrates
the 144-pin package part. The INTREQ pin is the sequence of events that define a one-byte write
asserted (driven low) whenever the DSP has an in Motorola mode. One byte writes should only be
outgoing message for the host. This same used with the Host Control and Host Data registers.
information is reflected by the HOUTRDY bit of The protocol presented in Figure 46 will now be
the Host Control Register (A[1:0] = 01b). described in detail.
INTREQ is useful for informing the host of 1) The host must first drive the A1 and A0 register
unsolicited messages. An unsolicited message is address pins of DSPC with the address of the
defined as a message generated by DSPC without desired Parallel I/O Register. The address is
an associated host read request. latched on the falling edge of CS.
Host Control: A[1:0]==01b.
Host Data1: A[1:0]==10b.
Host Data2: A[1:0]==11b.
2) The host indicates that this is a write cycle by
driving the R/W pin low.

63
3) The host initiates a write cycle by driving the
R/W (LOW)
CS and DS pins low. ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY)
4) The host drives the data byte to the HDAT[7:0]
pins of DSPC.
CS (LOW)
5) Once the setup time for the write has been met, DS (LOW)
the host ends the write cycle by driving the DS
and CS pins high. WRITE MS_BYTE TO
HDAT[7:0]
6.3.6.2 Writing a 32-bit (4-byte) Word in
Motorola Mode for DSPC
DS (HIGH)
Information provided in this section is intended as
a functional description of how to write control
information to DSPC. The system designer must DS (LOW)
ensure that all of the timing constraints of the
Motorola Parallel Host Mode Write Cycle are met.
WRITE BYTE_B TO
The flow diagram shown in Figure 43 illustrates HDAT[7:0]
the sequence of events that define a 32-bit (4-byte)
write in Motorola mode. 32-bit (4-byte) writes
DS (HIGH)
should only be done to the Host Message register.
The protocol presented in Figure 43 will now be
described in detail.
DS (LOW)
1) The host must first drive the A1 and A0 register
address pins of DSPC with the address of the
desired parallel I/O register (A1=A0=0). The WRITE BYTE_A TO
HDAT[7:0]
address must be maintained for the duration of
the write cycle, and is latched on the falling
edge of CS. DS (HIGH)

Host Message: A[1:0]==00b.

2) The host indicates that this is a write cycle by DS (LOW)

driving the R/W pin low.

3) The host initiates a write cycle by driving the WRITE LS_BYTE TO
CS and DS pins low. HDAT[7:0]

4) The host drives the most significant data byte

(bits 31:24) to the HDAT[7:0] pins of DSPC. DS (HIGH)

5) Once the setup time for the data has been met,
the host latches this byte in by driving DS high. CS (HIGH)

6) The host drive DS low.

Figure 47. Motorola Mode, 32-bit (4-byte) Write Flow
7) The host drives the next most significant data Diagram for DSPC
byte, BYTE_B (bits 23:16), to the HDAT[7:0]

64
 pins of DSPC.
R/W (HIGH)
8) Once the setup time for the data has been met, A DDRE SS A PA RALLE L I/O REGISTE R
(A [1:0] S ET AP PRO PRIA TE LY)
the host latches this byte in by driving DS high.
9) The host drive DS low.
10) The host drives the next most significant data CS (LOW )
DS (LOW )
byte, BYTE_A (bits 15:8), to the HDAT[7:0]
pins of DSPC.
11) Once the setup time for the data has been met, RE AD B YT E F ROM
the host latches this byte in by driving DS high. HDA T[7:0]

12) The host drive DS low.

13) The host drives the least significant data byte CS (HIGH)
DS (HIGH)
(bits 7:0) to the HDAT[7:0] pins of DSPC.
14) Once the setup time for the data has been met, Figure 48. Motorola Mode, One-Byte Read Flow
the host latches this byte in by driving DS high. Diagram for DSPC

15) The host ends the write cycle by driving the CS 3) The host initiates a read cycle by driving the CS
pin high. and DS pins low (bus must be tri-stated by this
6.3.6.3 Reading a Byte in Motorola Mode for time).
DSPC 4) Once the data is valid (after waiting the
Information provided in this section is intended as appropriate time specified in the timing
a functional description of how to write control specifications), the host can read the value of
information to DSPC. The system designer must the selected register from the HDAT[7:0] pins
ensure that all of the timing constraints of the of DSPC.
Motorola Parallel Host Mode Read Cycle are met. 5) The host should now terminate the read cycle
The flow diagram shown in Figure 48 illustrates by driving the CS and DS pins high.
the sequence of events that define a one-byte read
in Motorola mode. Single byte reads should only be 6.3.6.4 Reading a 32-bit (4-byte) word from
done with the Host Control register. The protocol DSPC in Motorola mode
presented in Figure 48 will now be described in Information provided in this section is intended as
detail. a functional description of how to read control
1) The host must first drive the A1 and A0 register information from DSPC. The system designer must
address pins of DSPC with the address of the ensure that all of the timing constraints of the
desired Parallel I/O Register (A1=0, A0=1). Motorola Parallel Host Mode Read Cycle are met.
The address must be maintained for the The flow diagram shown in Figure 49, "Motorola
duration of the read cycle, and is latched on the Mode, 32-Bit (4-Byte) Read Flow Diagram for
falling edge of CS. DSPC" on page 66 illustrates the sequence of
events that define a 32-bit (4-byte) read in
Host Control: A[1:0]==01b.
Motorola mode. Reading a 32-bit (4-byte) word
2) The host indicates that this is a read cycle by should only be done with the Host Message
driving the R/W pin high.

65
 R/W (HIGH) register. The protocol presented in Figure 49 will
ADDRESS A PARALLEL I/O REGISTER now be described in detail.
(A[1:0] SET APPROPRIATELY)
1) The host must first drive the A1 and A0 register
CS (LOW)
address pins of DSPC with the address of the
DS (LOW) desired Parallel I/O Register (A1=A0=0). Note
that only the Host Message register can be read
READ MS_BYTE TO using 4-byte reads. The address must be
HDAT[7:0] maintained for the duration of the read cycle,
and is latched on the falling edge of CS.
DS (HIGH) Host Message: A[1:0]==00b.
2) The host indicates that this is a read cycle by
DS (LOW) driving the R/W pin high.
3) The host initiates a read cycle by driving the CS
and DS pins low (bus must be tri-stated by this
READ BYTE_B TO
HDAT[7:0] time).
4) Once the data is valid (after waiting the
DS (HIGH) appropriate time specified in the timing
specifications), the host can read the most
significant byte (bits 31:24) from the
DS (LOW) HDAT[7:0] pins of DSPC.
5) The host indicates the byte has been read by
READ BYTE_A TO driving DS high.
HDAT[7:0]
6) The host latches out the next byte by driving
DS low.
DS (HIGH)
7) Once the data is valid (after waiting the
appropriate time specified in the timing
DS (LOW) specifications), the host can read the next most
significant byte, BYTE_B (bits 23:16), of the
selected register from the HDAT[7:0] pins of
READ LS_BYTE TO DSPC.
HDAT[7:0]
8) The host indicates the byte has been read by
driving DS high.
DS (HIGH)
9) The host latches out the next byte by driving
DS low.
CS (HIGH)
10) Once the data is valid (after waiting the
appropriate time specified in the timing
Figure 49. Motorola Mode, 32-Bit (4-Byte) Read Flow
specifications), the host can read the next most
Diagram for DSPC
significant byte, BYTE_A (bits 15:8), of the
selected register from the HDAT[7:0] pins of

66
 DSPC. generic reference to Write_Word_MOT() (write a
32-bit word in Motorola mode) or
11) The host indicates the byte has been read by
Write_Word_INT() (write a 32-bit word in Intel
driving DS high.
mode). Figure 50 shows a typical write sequence.
12) The host latches out the next byte by driving The protocol presented in Figure 50 will now be
DS low. described in detail.
13) Once the data is valid (after waiting the 1) When the host is communicating with DSPC,
appropriate time specified in the timing the host must verify that DSPC is ready to
specifications), the host can read the least accept a new 32-bit control word. If DSPC has
significant byte (bits 7:0) of the selected not read the previous word from the control
register from the HDAT[7:0] pins of DSPC. port, it will be unable to receive another word.
14) The host indicates the byte has been read by 2) In order to determine whether DSPC is ready to
driving DS high. accept a new 32-bit control word the host must
read the HINBSY bit of the Host Control
15) The host should now terminate the read cycle
Register (bit 2 in FA[1:0]=01b) using the
by driving the CS pin high.
selected communication mode (Intel or
6.3.7 Procedures for Parallel Host Mode Motorola). If HINBSY is high, then the DSP is
Communication for DSPC not prepared to accept a new control word, and
the host should poll the Host Control Register
6.3.7.1 Control Write in a Parallel Host Mode again. If HINBSY is low, then the host may
for DSPC write a control word (32-bits) into the Host
When writing control data to DSPC, the same
protocol is used whether the host is writing a
control message or an entire executable download
READ_BYTE_*(HOST
image. Messages sent to DSPC should be written CONTROL REGISTER)
most significant byte first. Likewise, downloads of
the application code should also be performed most
significant byte first. Y
HINBSY == 1
The example shown in this section can be
generalized to fit any control write situation. The N
generic function ‘Read_Byte_*()’ is used in the
following example as a generalized reference to WRITE_WORD_*(HOST
MESSAGE REGISTER)
either Read_Byte_MOT() (read a byte in Motorola
mode) or Read_Byte_INT() (read a byte in Intel
mode), and ‘Write_Byte_*()’ is a generic reference Y
MORE BYTES
to Write_Byte_MOT() (write a byte in Motorola TO WRITE?
mode) or Write_Byte_INT() (write a byte in Intel
N
mode). Similarly, the generic function
‘Read_Word_*()’ is used in the following example FINISHED
as a generalized reference to either
Read_Word_MOT() (read a 32-bit word in
Motorola mode) or Read_Word_INT() (read a 32-
bit word in Intel mode), and ‘Write_Word_*()’ is a Figure 50. Typical Parallel Host Mode Control
Write Sequence Flow Diagram for DSPC

67
 Message Register.
3) Once the host knows that the DSP is ready for FINTREQ = 0?

a new control word, it should write the 32-bit Y

control word to the Host Message Register
READ_BYTE_*( HOST
(FA[1:0] = 00b) using the selected CONTROL REGISTER)
communication mode (Intel or Motorola).
4) If the host would like to write any more 32-bit N
control words to DSPC, the host should once HOUTRDY == 1

again poll the Host Control Register (return to Y

step 1).
READ_WORD_*( HOST
6.3.7.2 Control Read in a Parallel Host Mode MESSAGE REGISTER)

for DSPC
When reading control data from DSPC, the same Y
MORE WORDS TO
protocol is used whether the host is reading a single READ?
32-bit word, or a string of message words.
Reads and writes to the Host Message Register are N
always 32-bits (4-bytes), and reads of the Host WAIT 100 MICROSEC
Control Register are always a single byte.
The example shown in this section can be used for
READ_BYTE_*( HOST
any control read situation. The generic function CONTROL REGISTER)
‘Read_Word_*()’ is used in the following example
as a generalized reference to either
Read_Word_MOT() (Motorola 32-bit word read) Y
HOUTRDY == 1
or Read_Word_INT() (Intel 32-bit word read).
Figure 51 shows a typical read sequence. The
N
protocol presented in Figure 51 will now be
FINISHED
described in detail.
1) Optionally, INTREQ going low may be used as
an interrupt to the host to indicate that DSPC Figure 51. Typical Parallel Host Mode Control Read
Sequence Flow Diagram for DSPC
has an outgoing message.
2) The host reads the Host Control Register not placed a new control word in the Host
(A[1:0] = 01b) in order to determine the state of Message Register, and the host should poll the
the communication interface. Host Control Register again.

3) In order to determine whether DSPC has an 4) Once the host knows that the DSP is ready to
outgoing control word that is valid, the host provide a new 32-bit response word, the host
must check the HOUTRDY bit of the Host can safely read a word from the Host Message
Control Register (bit 1, A[1:0] = 01b). If Register (A[1:0] = 00b) using the appropriate
HOUTRDY is high, then the Host Message communication protocol (Motorola or Intel).
Register contains a valid 32-bit word for the 5) If the host expects to read more 32-bit response
host. If HOUTRDY is low, then the DSP has words, the host should once again check the

68
 HOUTRDY bit (return to step 1). 144-Pin 100-Pin
Pin Name Pin Description Number Number
6) After the response has been read the host EXTA0 SRAM Address 0 73 51
should wait at least 100 uS and check EXTA1 SRAM Address 1 74 52
HOUTRDY one final time. If HOUTRDY is EXTA2 SRAM Address 2 75 53
high once again this means that an unsolicited EXTA3 SRAM Address 3 76 54
EXTA4 SRAM Address 4 67 46
message has come during the read process and EXTA5 SRAM Address 5 66 45
the host has another message to read (i.e. skip EXTA6 SRAM Address 6 65 44
back to step 4 and read out the new message). It EXTA7 SRAM Address 7 63 43
is the host’s responsibility to insure that any EXTA8 SRAM Address 8 62 42
EXTA9 SRAM Address 9 60 41
pending messages are read from the DSP. EXTA10 SRAM Address 10 72 50
Failure to do this may cause the DSP’s output EXTA11 SRAM Address 11 56 40
message buffer to overflow, corrupting any EXTA12 SRAM Address 12 55 39
pending outbound messages. EXTA13 SRAM Address 13 54 38
EXTA14 SRAM Address 14 53 37
7. EXTERNAL MEMORY EXTA15 SRAM Address 15 52 36
EXTA16 SRAM Address 16 49 35
The system designer has the option of using EXTA17 SRAM Address 17 47 34
external memory. The external memory interface is EXTA18 SRAM Address 18 46 33
implemented with two controllers. The SRAM EXTA19 SRAM Address 19 71 N/A
EXTD0 SRAM Data 0 34 23
controller allows the DSP to autoboot from a
EXTD1 SRAM Data 1 35 24
parallel FLASH or EEPROM device. The SRAM EXTD2 SRAM Data 2 36 25
and SDRAM controllers are used to extend the data EXTD3 SRAM Data 3 37 26
memory of the DSP during runtime. A system can EXTD4 SRAM Data 4 38 27
use a FLASH/EEPROM device for autoboot, and EXTD5 SRAM Data 5 40 28
either SRAM or SDRAM for runtime memory. The EXTD6 SRAM Data 6 43 31
EXTD7 SRAM Data 7 44 32
application user’s guide for a particular code load
NV_OE# SRAM Output Enable 31 21
will inform the system designer if memory is NV_WE# SRAM Write Enable 71 N/A
required, and will specify the memory type and NV_CS# SRAM Chip Select 32 22
speed. If no mention is made of external memory, Table 11. SRAM Interface Pins
then external memory is not required for that
144-Pin
application. The SDRAM interface is not Pin Name Pin Description Number
available on the 100-pin device. SD_DATA0 SDRAM Data 0 34
The signals for the external memory interface SD_DATA1 SDRAM Data 1 35
SD_DATA2 SDRAM Data 2 36
are listed in Table 11. and Table 12.
SD_DATA3 SDRAM Data 3 37
For both controllers, memory access speed is SD_DATA4 SDRAM Data 4 38
controlled by the DSP clock setting which is SD_DATA5 SDRAM Data 5 40
constrained by the application code. The SRAM SD_DATA6 SDRAM Data 6 43
SD_DATA7 SDRAM Data 7 44
interface is capable of in-system programming a
SD_DATA8 SDRAM Data 8 56
FLASH device. Wait states are available to support SD_DATA9 SDRAM Data 9 55
slower FLASH/EEPROM and SRAM devices. The SD_DATA10 SDRAM Data 10 54
SRAM interface supports 1Mx8 addressable space. SD_DATA11 SDRAM Data 11 53
We recommend 12nS or better SRAM for optimal SD_DATA12 SDRAM Data 12 52
performance. The SDRAM interface supports SD_DATA13 SDRAM Data 13 49
SD_DATA14 SDRAM Data 14 47
16Mbit parts organized as 512k x 16bits x 2 banks
which yields a 1Mx16 addressable space. The burst Table 12. SDRAM Interface Pins

69
 144-Pin Kickstarting the downloaded DSPC application
Pin Name Pin Description Number code.
SD_DATA15 SDRAM Data 15 46
SD_ADDR0 SDRAM Address 0 73 Hex
SD_ADDR1 SDRAM Address 1 74 Mnemonic Message
SD_ADDR2 SDRAM Address 2 75
SRAM_CONTROLLER_TIMING 0x8100000F
SD_ADDR3 SDRAM Address 3 76
0x00000aaa
SD_ADDR4 SDRAM Address 4 67
0xaaa = 0www wwrr rrre (in binary)
SD_ADDR5 SDRAM Address 5 66
SD_ADDR6 SDRAM Address 6 65
w = SRAM_FLASH_WR_CYCLE vari-
SD_ADDR7 SDRAM Address 7 63
able found in the SRAM Switching char-
SD_ADDR8 SDRAM Address 8 62
acteristics table in Section 1.19.
SD_ADDR9 SDRAM Address 9 60
SD_ADDR10 SDRAM Address 72
r = SRAM_FLASH_RD_CYCLE variable
10
found in the SRAM Switching character-
SD_DQM0 SDRAM Data 39
istics table in Section 1.19.
Mask Output0
SD_WE# SDRAM Write 37
Enable e = SRAM Enable/Disable = 0/1.
SD_CAS# SDRAM Column 78
Address Strobe Default, aaa = 0x000
SD_RAS# SDRAM Row 77
Table 13. SRAM Controller Timing
Address Strobe
SD_CS# SDRAM Chip 68
Select Hex
SD_BA SDRAM Bank 71 Mnemonic Message
Select SDRAM_CONFIG 0x81000017
SD_DQM1 SDRAM Data 45 0xaaaabbbe
SD_CLK_IN SDRAM Clock 61 aaaa = Auto refresh setting.
Input For example for a 16 µS refresh period
SD_CLK_OUT SDRAM Clock 59 and a DCLK of 86 Mhz the value pro-
Output grammed should be:
SD_CLK_EN SDRAM Clock 64 16X10-6 X 86X106 = 0x(1376) = 0x0560
Enable
Table 12. SDRAM Interface Pins bbb = Mode register setting. These bits
set the 12 least significant bits in the
length is fixed to 8. We recommed SDRAM with a
mode register. The bits are to the follow-
CAS latency of 2 for optimal performance. The ing by default:
refresh rate and the mode register of the SDRAM bits(2..0) = 011 = Burst length 8.
must be set before Kickstart. Refer to Table 14, bit3 = 0 = Sequential Burst Type.
“SDRAM Config Register,” on page 70 for details bits(6..4) = 010 = CAS latency of 2.
on the SDRAM config register. The SDRAM is bits(8..7) = 00 = Mode Register Set.
bit9 = 0 = Write Burst.
initialized after Kickstart.
bit(12..10) = 000 = reserved
7.1 Configuring SRAM Timing Parameters
e = SDRAM Enable/Disable
Since not all SRAM manufacturers conform to the =0001/0000.
exact same timing specifications, it is necessary to
configure the DSP to match the timing Default, 0xaaaabbbe = 0x0560008c0
specifications of the particular SRAM that is used Table 14. SDRAM Config Register
in your design. This message must be sent before

70
8. BOOT PROCEDURE C_SLAVE_MODE 0x80 00 00 00
In this section the process of booting and C_MASTER_BOOT_FLASH
1110 wwww wrrr rrAA 0xEw cb AA AA
downloading to the CS49400 will be covered as
well as how to perform a soft reset. There are two c b
ways to boot the DSP:
AAAA AAAA AAAA AAAA
• Host Controlled MasterBoot Where
• Host Boot Via DSPC
w = SRAM_FLASH_WR_CYCLE
Each of these boot procedures will be described in variable found in the SRAM Switch-
detail with pseudocode. The flow charts use the ing characteristics table in Section
following messages: 1.19.
r = SRAM_FLASH_RD_CYCLE
• Write-C_* Write to DSPC variable found in the SRAM Switch-
• Read-C_* Read from DSPC ing characteristics table in Section
1.19.
• Write-AB_* Write to DSPAB A = 18-bit start address/4

• Read-AB_* Read from DSPAB

Table 16. Boot Write Messages for DSPC (Continued)
Note:When reading from DSPAB the host must
wait for FINTREQ to fall before starting the read
MNEMONIC VALUE
cycle. When reading from DSPC the host must
wait for INTREQ to fall before starting the read C_BOOT_START 0x00 00 00 01
cycle. C_BOOT_SUCCESS 0x00 00 00 02
Note:The * can be replaced by SPI, INTEL, or C_APP_START 0x00 00 00 04
MOT depending on the mode of host C_BOOT_ERROR_CHECKSUM 0x00 00 00 FF
communication. For each case the general
download algorithm is the same. INVALID_BOOT_TYPE 0x00 00 00 FE
Table 16, and Table 17 define the boot write Table 17. Boot Read Messages from DSPC
messages and boot read messages in mnemonic and
actual hex value for DSPAB and DSPC. These 8.1 Host Controlled Master Boot
messages will be used in the boot sequence A host controlled master boot is a sequence where
a host instructs the DSP to load application code
MNEMONIC VALUE into itself from external memory. External memory
AB_APP_START 0x03 can either be FLASH or SPI EEPROM.
AB_APP_FAILURE 0xF0 The flow chart given in Figure 52, "Host
Table 15. Application Messages from DSPAB Controlled Master Boot (Downloading both a
DSPAB Application Code and a DSPC
MNEMONIC VALUE Application Code)" on page 72 demonstrates the
C_RESERVED 0x00 00 00 00 interaction required by the microcontroller when
C_SOFT_RESET 0x40 00 00 00 placing the DSP into a host controlled master
Table 16. Boot Write Messages for DSPC mode.
1) A download sequence is started when the host
holds the mode pins appropriately (UHS[2:0]
and FHS[1:0]) and toggles RESET.
2) The host must then send the
C_MASTER_SOURCE_MODE boot message

71
 STAR T

R ESET(LOW )
R EAD-C_*(C_ MESSAGE)

RESET(H IGH)
N
M SG==
EXIT(ER ROR)
C _BOOT_SU CC ESS
W AIT ?? u S
Y

W RITE-C_* W RITE-C_*(C_SOFT_ RESET)

(C_M ASTER_SOU RC E_MODE)

N TIMEOU T
N TIMEOUT INTREQ LOW ?
IN TR EQ LOW ? AFTER (10 mS)
A FTER (10 m S)

Y
Y
READ -C _*(C _ME SSAGE)
RE AD-C_*(C_M ESSAGE)

MSG== N
MSG N EXIT(ER ROR)
EX IT(ERR OR ) C_ APP_START
==C _BOOT_START
Y
Y
W R ITE-C_*(C_ HW _ CONFIG_MSG,
RELEAS E
MS G_ SIZE)
C ON TR OL OF B US

W RITE-C _*(C_SW _CON FIG_M SG,

N TIM EOUT MS G_ SIZE)
IN TR EQ LOW ?
AFTE R (500 m S)

Y
W RITE-C_*(KICKS TAR T,
MS G_ SIZE)
R EAD-C_ *(C_ MESSAGE)

C _APPL ICATION_R UN NIN G

N
MSG==
EXIT(ER ROR)
C_B OOT_SUC CES S

Y FINTREQ LOW ? N TIMEOUT

HOUTRD Y HI? AFTER (10 mS )
W RITE-C_*
(C_M ASTER_SOU RC E_MODE) Y

R EAD-AB_*(A B_MESS AGE )

N TIMEOUT
IN TR EQ LOW ?
A FTER (10 m S)

MSG== N
Y EXIT(E RROR )
AB_ APP_START

RE AD-C_*(C_M ESSAGE)
Y

W R ITE -AB_*(AB_H W _C ONFIG_ MSG,

MS G_ SIZE)
MSG N
EX IT(ERR OR )
==C _BOOT_START

Y W RITE-AB_*(AB_SW _ CONFIG_MSG,
MS G_ SIZE)
RELEAS E
C ON TR OL OF B US
W RITE-AB_*(KICKSTAR T,
MS G_ SIZE)
N TIM EOUT
INTREQ LOW ? AFTE R (500 m S)

AB_APPLICATION_R UN NIN G
Y

Figure 52. Host Controlled Master Boot

(Downloading both a DSPAB Application Code and a DSPC Application Code)

72
 to DSPC. The supported messages are to go low.
described in Table 16. This message tells Note:DSPC will autoboot DSPC. After this
DSPC where to get the DSPAB image from. DSPC will release control of the communication
Currently the C_MASTER_BOOT_FLASH interface, but only when in SPI Master Boot
Mode.
message is supported and allows booting from 9) The end of the .ULD file contains a four byte
external byte-wide flash or eprom. checksum. If the checksum is good after the
3) If the initialization was successful DSPC sends download, DSPC will send a
out the C_BOOT_START message and the C_BOOT_SUCCESS message to the host. If
host must proceed to step 4. If initialization the checksum was bad, DSPC responds with
fails the host must re-try steps 1 through 3 and the C_BOOT_ERROR_CHECKSUM message
if failure is met again, the communication and waits for a hard reset.
timing and protocol should be inspected. 10) After reading out the C_BOOT_SUCCESS
4) After receiving the C_BOOT_START message, the host must send the
message, the host must release control of the C_SOFT_RESET message which will cause
communication interface and wait for INTREQ the application code to reset and allow the
to go low. downloaded application to run.
Note: DSPC will autoboot DSPAB. After this 11) If the soft reset was successful, DSPC sends out
DSPC will release control of the communication
interface, but only when in SPI Master Boot
a C_APP_START message the host can
Mode. proceed to step 12. If DSPC does not send an
5) The end of the .ULD file contains a three byte the application start message, the host must re-
checksum. If the checksum is good after the try the whole procedure again.
download, DSPC will send a 12) Next the host can send hardware and software
C_BOOT_SUCCESS message to the host. If configuration messages for DSPC.
the checksum was bad, DSPC responds with
the C_BOOT_ERROR_CHECKSUM message 13) At this point the application code on DSPC is
message and waits for a hard reset. running and the host needs to configure
DSPAB.
6) After reading out the C_BOOT_SUCCESS
message, the host must send a second 14) The host must read the AB_APP_START
C_MASTER_SOURCE_MODE boot message message from DSPAB. If DSPAB does not
to DSPC. This messages tells DSPC where the send an the application start message the host
to get image for DSPC. must re-try the whole procedure again, starting
with step 1.
7) If the initialization was successful DSPC sends
out the C_BOOT_START message and the 15) The host must send hardware and software
host must proceed to step 8. If initialization configuration messages for DSPAB, ending
fails the host must re-try step 6. If failure is met with the kickstart message.
again, the communication timing and protocol 16) At this point the application code on DSPAB is
should be inspected. running.
8) After receiving the C_BOOT_START Note: Hardware configuration messages are
used to define the behavior of the DSP’s audio
message, the host must release control of the
ports. A more detailed description of the
communication interface and wait for INTREQ different hardware configurations can be found

73
 in the Section 10 “Hardware Configuration” on the host should re-try step 6. If failure is met
page 78.
again, the communication timing and protocol
Note: The software configuration messages
are specific to each application. The application should be inspected.
code user’s guide for each application provides
a list of all pertinent configuration messages.
8) After receiving the C_BOOT_START
Writing the KICKSTART message to DSPAB message, the host should write the
begins the audio decode process. downloadable image for DSPC.
8.2 Host Boot Via DSPC 9) The host must wait for INTREQ to go low and
A host controlled boot via DSPC is a sequence read the message from DSPC.
where the host boots DSPAB and DSPC through 10) After reading out the C_BOOT_SUCCESS
DSPC with two separate images (.ULD files). message. The host must send the
Figure 53, "Host Boot Via DSPC" on page 75 C_SOFT_RESET message which will cause
demonstrates the interaction required by the the application code to reset and allow the
microcontroller. downloaded application to run.
1) A download sequence is started when the host 11) If the soft reset was successful, DSPC sends out
holds the mode pins appropriately (UHS[2:0] a C_APP_START message the host can
and FHS[1:0]) and toggles RESET. proceed to step 8. If DSPC does not send an the
2) The host must then send the application start message, the host must re-try
C_SLAVE_MODE boot message to DSPC. the whole procedure again.
This causes DSPC to initialize itself. 12) Next the host can send hardware and software
3) If the initialization was successful DSPC sends configuration messages for DSPC.
out a C_BOOT_START message. The host 13) At this point the application code on DSPC is
should proceed to step 4. If initialization fails, running and the host needs to configure
the host should re-try steps 1 through 3 and if DSPAB.
failure is met again, the communication timing
14) The host must read the AB_APP_START
and protocol should be inspected.
message from DSPAB. If DSPAB does not
4) After receiving the C_BOOT_START send an the application start message the host
message, the host should write the must re-try the whole procedure again,
downloadable image for DSPAB(.ULD file) to beginning at setp 1.
DSPC.
15) The host must send hardware and software
5) The host must wait for INTREQ to go low and configuration messages for DSPAB.
read the message from DSPC.
16) At this point the application code on DSPAB is
6) After reading out the C_BOOT_SUCCESS running.
message, the host must then send the
Note: Hardware configuration messages are
C_SLAVE_MODE message to DSPC once used to define the behavior of the DSP’s audio
more. This causes DSPC to initialize itself and ports. A more detailed description of the
get ready to accept a stream. different hardware configurations can be found
in the Section 10 “Hardware Configuration” on
7) If the initialization was successful DSPC sends page 78.
out a C_BOOT_START message. The host Note: The software configuration messages
are specific to each application. The application
should proceed to step 8. If initialization fails, code user’s guide for each application provides

74
 STAR T

RE SET(LO W )
RE AD -C _*(C _MES SA GE )

W A IT 10 uS

MSG== N
EXIT(ER R OR )
C _B OOT_SUC CE SS
R ESE T(HIGH)

W R ITE-C_*(C_SOFT_RE SET)
W RITE -C _*
(C_SLAVE _MOD E)

N TIME OU T
N TIME OUT IN TR EQ LOW ?
INTR EQ LO W ? A FTER (5 m S )
AFTER (5 m S)

Y
Y
R EA D-C_*(C_ME SS AGE)
RE AD-C_*(C_MES SAGE )

MSG== N
MSG N E XIT(ERR OR )
EXIT(ER ROR ) C_A PP_S TA R T
==C_BOOT_S TA RT

Y
Y
W RITE -C _*(C_H W _C ONFIG_MSG,
W R ITE-C_*(.U LD FILE ,FILE MSG_S IZE)
S IZE) for DS P AB

W R ITE-C_*(C_SW _CON FIG_MSG,

N M SG_SIZE )
TIME OU T
INTR EQ LO W ?
A FTER (5 mS )

W R ITE-C_*(KIC KS TA RT,
Y
M SG_SIZE )

RE AD -C _*(C _M ESSA GE)

C_AP PLIC ATION _R UN NIN G

Y
MSG== N
EXIT(E RR OR)
C_BOOT_S UC CE SS
FINTR EQ LOW ? N TIME OUT
HOU TR DY H I? A FTER (5 m S )

W RITE -C _* Y
(C_SLAVE _MOD E)
REA D -AB _*(A B_ME SSA GE)

N TIME OUT
INTR EQ LO W ?
AFTER (5 m S) N
MSG==
EXIT(ER R OR)
AB _AP P_STA RT
Y

RE AD-C_*(C_MES SAGE ) Y

W RITE -AB _*(AB_H W _C ON FIG_MSG,

M SG_SIZE )

MSG N
EXIT(ER ROR )
==C_BOOT_S TA RT W R ITE-A B_*(AB _SW _CON FIG_MS G,
M SG_SIZE )
Y

W R ITE-C_*(.U LD FILE ,FILE W RITE-AB_*(KIC K START,

S IZE) for D SP C M SG_SIZE )

N TIME OU T AB_AP PLIC ATION _R UN NIN G

INTR EQ LO W ?
A FTER (5 mS )

Figure 53. Host Boot Via DSPC

75
 a list of all pertinent configuration messages. and FHS[1:0]) and toggles RESET.
Writing the KICKSTART message to DSPAB
begins the audio decode process. 2) The host must send the C_SOFT_RESET
message to DSPC. This causes the application
9. SOFT RESETTING THE CS49400
code on DSPAB and DSPC to reset and allow
Soft resetting the CS49400 uses a combination of the downloaded application to run.
software and hardware. This method of resetting
the DSP is usually referred to as a “soft reset” even 3) If the soft reset was successful, DSPC sends out
though it involves toggling the reset pin due to the a C_APP_START message the host can
fact that a soft reset message is sent to the DSP. To proceed to step 4. If DSPC does not send an the
soft reset the device, a previous application code application start message, the host must re-try
must have been downloaded without power cycling the whole procedure again.
the DSP. Figure 54, "Host Controlled Master 4) The host can send hardware and software
Softreset" on page 77 describes the soft reset configuration messages for DSPC.
procedure. The main purpose behind a soft reset is
to take advantage of the fact that all AC-3 based 5) At this point the application code on DSPC is
codes can accept both AC-3 compressed data as running and the host needs to configure
well as PCM data. This allows for a the host to DSPAB.
reconfigure the AC-3 application code for PCM or 6) Next the host must wait for FINTREQ to go
AC-3 without having to completely redownload the
low and read the AB_APP_START message
same application code.
from DSPAB. If DSPAB does not send an the
9.1 Host Controlled Master Soft Reset application start message the host must re-try
This reset procedure is used to restart the the whole procedure again, beginning from step
application code that has already been loaded on 1.
the DSP. All writes and reads with the CS49400 7) The host must send hardware and software
should follow the protocol given in Section 8 configuration messages for DSPAB.
“Boot Procedure” on page 71.
8) At this point the application code on DSPAB is
1) A Soft Reset sequence is started when the host
running.
holds the mode pins appropriately (UHS[2:0]

76
 S TA RT

RES ET(LOW )

W AIT 10 uS

RES ET(HIGH)

W RITE-C_*(C_S OFT_RES ET)

N TIM EOUT N TIME OUT

INTRE Q LOW ? FINTREQ LOW ?
AFTE R (5 m S) A FTE R (5 m S )

Y Y

REA D-C_*(C_ME SS AGE) RE A D-AB _*(AB _M E SS AGE)

MS G== N M SG== N
E XIT(ERROR) E XIT(E RROR)
C_AP P_S TA RT A B_APP _S TART

Y Y

W RITE -C_*(C_HW _CONFIG_M S G, W RITE-AB _*(A B_HW _CONFIG_M S G,

MSG_S IZE) MS G_SIZE)

W RITE -C_*(C_S W _CONFIG_MS G, W RITE-AB _*(A B_S W _CONFIG_MS G,

MSG_S IZE) MS G_SIZE)

W RITE -C_*(K ICK START, W RITE-A B_*(K IC KS TA RT,

MSG_S IZE) MS G_SIZE)

C _A PP LICA TION_RUNNING AB _AP PLICATION _RUNNING

Figure 54. Host Controlled Master Softreset

77
10. HARDWARE CONFIGURATION 11.1 Digital Audio Formats
After download or soft reset, and before kickstart, This subsection will describe some common audio
the host has the option of changing the default formats that the CS49400 supports. It should be
hardware configuration. (Please see the Audio noted that the input ports use up to 24-bit PCM
Manager in the Application Messaging Section of resolution and 16-bit compressed data word
any Application Code User’s Guide for more lengths. The output port of the CS49400 provides
information on kickstarting.) up to 24-bit PCM resolution.
Hardware configuration messages are used to
physically reconfigure the hardware of the audio
11.1.1 I2S
decoder, as in enabling or disabling address Figure 55, "I2S Format" on page 79 shows the I2S
checking for the serial communication port. format. For I2S, data is presented most significant
Hardware configuration messages are also used to bit first, one FSCLKN1 delay after the transition of
initialize the data type (i.e., PCM or compressed) FLRCLKN1, and is valid on the rising edge of
and format (e.g., I2S, left justified, etc.) for digital FSCLKN1. For the I2S format, the left subframe is
data inputs, as well as the data format and clocking presented when FLRCLKN1 is low; the right
options for the digital output port. subframe is presented when FLRCLKN1 is high.
In general, the hardware configuration can only be FSCLKN1 is required to run at a frequency of 48Fs
changed immediately after download or after soft or greater on the input ports.
reset and before kickstart. However, some 11.1.2 Left Justified
applications provide the capability to change the
input ports without affecting other hardware Figure 56, "Left Justified Format (Rising Edge
configurations, after sending a special Application Valid SCLK)" on page 79 shows the left justified
Restart message. (Please see the Audio Manager in format with a rising edge FSCCLK. Data is
any Application Code User’s Guide to determine presented most significant bit first on the first
whether the Application Restart message is FSCLKN1 after an FLRCLKN1 transition and is
supported.) valid on the rising edge of FSCLKN1. For the left
justified format, the left subframe is presented
11. DIGITAL INPUT AND OUTPUT when FLRCLKN1 is high and the right subframe is
DATA FORMATS presented when FLRCLKN1 is low. The left
The CS49400 supports a wide variety of data input justified format can also be programmed for data to
and output data formats through various input and be valid on the falling edge of FSCLKN1.
output ports. Hardware availability is entirely FSCLKN1 is required to run at a frequency of 48Fs
dependent on whether the software application or greater on the input ports.
code being used supports the required mode. This 11.2 Digital Audio Input Port
data sheet presents most of the modes available
with the CS49400 hardware. This does not mean The digital audio input port (DAI) on DSPAB, is
that all of the modes are available with any used for both compressed and PCM digital audio
particular piece of application code. The data input. In addition this port supports a special
Application Code User’s Guide for the particular clocking mode in which a clock can be input to
code being used should be referenced to determine directly drive the internal 33 bit counter. Table 18,
if a particular mode is supported. In addition if a “Digital Audio Input Port,” on page 79 shows the
particular mode is desired that is not presented,
please contact your local FAE as to its availability.

78
pin names, mnemonics and pin numbers associated Pin Name Pin Description 144-Pin 100-Pin
with the DAI. Package, package,
Pin Pin
Pin Name Pin Description 144-Pin 100-Pin Number Number
Package, Package, FSDATAN2 Serial Data In 118 79
Pin Pin CMPDAT Compressed Data
Number Number In
FSDATAN1 Serial Data In 131 84 FSCLKN2 Serial Bit Clock 111 78
FSCLKN1 Serial Bit Clock 134 81 CMPCLK
FSTCCLK2 Secondary STC FLRCLKN2 Frame Clock 117 80
Clock CMPREQ Data Request Out
FLRCLKN1 Frame Clock 119 85 Table 19. Compressed Data Input Port
Table 18. Digital Audio Input Port
11.4 Input Data Hardware Configuration
The DAI is fully configurable including support for for CDI and DAI on DSPAB
I2S and left-justified formats. DAI is programmed
for slave clocks, where FLRCLKN1 and Both data format (I2S, Left Justified) and data type
FSCLKN1 are inputs. All DAI configuration (compressed or PCM) are required to fully define
messages must be sent to DSPAB. the input port’s hardware configuration. The DAI
and the CDI are configured by the same group of
11.3 Compressed Data Input Port messages since their configurations are
The compressed data input port (CDI) on DSPAB interrelated. The naming convention of the input
can be used for both compressed and PCM data hardware configuration is as follows:
input. Table 19 shows the mnemonic, pin name, INPUT A B C
and pin number of the pins associated with the CDI where A, B, C and are the parameters used to fully
port on the CS49400. define the input port. The parameters are defined as
The CDI port is fully configurable for all data follows:
formats including: I2S, left-justified and A - Data Type
multichannel formats. FLRCLKN2 and FSCLKN2
on the CDI port are programmed to be inputs. All B - Data Format
CDI configuration messages must be sent to C - SCLK Polarity
DSPAB.

FLRCLKN1 Left Right

FSCLKN1
FSDATAN1 MSB LSB MSB LSB

Figure 55. I2S Format

FLRCLKN1 Left Right

FSCLKN1
FSDATAN1 MSB LSB MSB LSB MSB
Figure 56. Left Justified Format (Rising Edge Valid SCLK)

79
The following tables show the different values for Hex
each parameter as well as the hex message that B Value Data Format Message
needs to be sent. When creating the hardware 1 PCM - Left Justified 24-bit 0x800217
configuration message, only one hex message 0x8080FF
should be sent per parameter. It should be noted Compressed - Left Justified 0x80021A
16-bit 0x8080FF
that the entire B parameter hex message must be (Compressed means any type of 0x800117
sent, even if one of the input ports has been defined compressed data such as IEC61937- 0x001000
as unused by the A parameter. packed AC-3, DTS, MPEG 0x80011A
Multichannel, AAC or MP3 elementary 0x001800
Hex stream data from a DVD or IEC60958-
A Value Data Type Message packed elementary stream DTS data
0 DAI - PCM 0x800210 from a DTS-CD)
(default) CDI - Compressed 0x3FBFC0
Table 21. Input Data Format Configuration
0x800110
(Input Parameter B) (Continued)
0x80002C
1 DAI - PCM and Compressed 0x800210
SCLK Polarity (Both CDI and Hex
CDI - Unused 0x3FBFC0
C Value DAI Port) Message
0x800110
0xC0002C 0 Data Clocked in on Rising 0x800217
(default) Edge 0xFFFFDF
2 DAI - Unused 0x800210
0x80021A
CDI - PCM 0x3FBFC0
0xFFFFDF
0x800110
0x800020 1 Data Clocked in on Falling 0x800117
Edge 0x000020
Table 20. Input Data Type Configuration 0x80011A
(Input Parameter A) 0x000020
Table 22. Input SCLK Polarity Configuration
Hex
(Input Parameter C)
B Value Data Format Message
0 PCM - I2S 24-bit 0x800217
11.4.1 Input Configuration Considerations
(default) 0x8080FF
Compressed - I2S 16-bit 0x80021A 1) 24-bit PCM input requires at least 24 SCLKs
Compressed means any type of com- 0x8080FF
per sub-frame. The DSP always uses 24-bit
pressed data such as IEC61937- 0x800117
packed AC-3, DTS, MPEG Multichan- 0x011100
resolution for PCM input. Systems having less
nel, AAC or MP3 elementary stream 0x80011A than 24-bit resolution will not have a problem
data from a DVD or IEC60958-packed 0x011900 as the extra bits taken by the DSP will be under
elementary stream DTS data from a
the noise floor of the input signal for left
DTS-CD)
justified and I2S formats. For compressed
Table 21. Input Data Format Configuration input, data is always taken in 16 bit word
(Input Parameter B)
lengths.
2) If the clocks to the audio ports are known to be
corrupted, such as when a S/PDIF receiver goes
out of lock, the DSP should undergo an
application restart (if applicable), soft reset, or
hard reset. All three actions will result in the
input FIFO being reset. Failure to do so may
result in corrupted data being latched into the

80
 input FIFO and may result in corrupted data be sent to DSPC to configure and enable the SAI
being heard on the outputs. port.
Corruption is only an issue when PCM data is D Value Data Type Hex Message
being delivered. When compressed data is 0 2
PCM - I S 24-bit 0x81000010
being delivered, there are sync words 0x00000001
embedded in the data stream to which the DSP 0x81000011
0x00011701
can lock. Certain application codes that are
0x81000012
capable of processing PCM may now have a 0x00004E4F
special feature called “PCM Robustness” 1 PCM - Left Justified 24-bit 0x81000010
which prevents the corruption described above, 0x00000001
but you should still use a FIFO reset to ensure 0x81000011
0x00001600
good data. 0x81000012
0x00005E4F
11.5 Serial Audio Input
Table 24. SAI Data Type Configuration
The Serial Audio Input (SAI) provides four stereo (Input Parameter D)
inputs to DSPC. The SAI can be used to post-
process PCM data from a multichannel Super 11.6 Digital Audio Output Port
Audio CD input or DVD Audio/Video input via
high-performance A/Ds. Table 19 shows the The Digital Audio Output port (DAO) can transmit
up to 16 channels of PCM data that are fully
configurable into standard audio format. It also has
Pin Name Pin Description 144-Pin 100-Pin
Package, Package,
two IEC60958 pins that provide CMOS level bi
Pin Pin phase encoded outputs. Table 25 shows the signals
Number Number associated with the DAO. As with the input ports
SCLKN Serial Bit Clock 86 60 the clocks and data are fully configurable via
LRCLKN Frame Clock 85 59 hardware configuration. All DAO configuration
SDATAN3 Serial Data In 3 79 55 messages must be sent to DSPC.
SDATAN2 Serial Data In 2 80 56
SDATAN1 Serial Data In 1 81 57
Pin Name Pin Description 144-Pin 100-Pin
SDATAN0 Serial Data In 0 82 58
Number Number
Table 23. Serial Audio Input Port
MCLK Master Clock 99 68
SCLK1 Serial Bit Clock for 98 67
mnemonic, pin name and pin number of the pins AUDATA 4-7
associated with the SAI port on the CS49400. LRCLK1 Frame Clock for 87 61
The SAI has 4 stereo data inputs that are fully AUDATA 4-7
configurable including support for I2S, left- AUDATA7,X Serial Data Out 7, 92 64
justified and multichannel formats. The SAI port MT958B IEC60958 Trans-
operates in slave mode only with LRCLKN and mitter
SCLKN as inputs. Processing on the CDI and DAI AUDATA6 Serial Data Out 6 93 65
ports must be disabled before the SAI port is AUDATA5 Serial Data Out 5 94 66
enabled. Either the input D0 or D1 message must AUDATA4 Serial Data Out 4 102 71
Table 25. Digital Audio Output Port

81
 Pin Name Pin Description 144-Pin 100-Pin different MCLK frequencies. (All values are
Number Number expressed in terms of the sampling frequency, Fs.)
SCLK0 Serial Bit Clock for 104 72
AUDATA 0-3 SCLK (Fs)
MCLK
LRCLK0 Frame Clock for 108 75 (Fs) 32 48 64 128 256 512
AUDATA 0-3
128 X X
AUDATA3,X Serial Data Out 3, 106 73
384 X X X
MT958A IEC60958 Trans-
mitter 256 X X X X
AUDATA2 Serial Data Out 2 107 74 512 X X X X X
AUDATA1 Serial Data Out 1 109 76 Table 26. MCLK/SCLK Master Mode Ratios
AUDATA0 Serial Data Out 0 110 77
Table 25. Digital Audio Output Port (Continued) Both the AUDAT0 and AUDAT4 Digital Audio
Output porst are configurable to provide output for
MCLK is the master clock and is firmware two, four, or six channels of PCM data.
configurable to be either an input or an output. If AUDATA1, AUDATA2, AUDATA3,
MCLK is to be used as an output, the internal PLL AUDATA5, AUDATA6 and AUDATA7 are only
must be used. As an output MCLK can be capable of outputting two channels of PCM data.
configured to provide a 128Fs, 256Fs, or 512Fs Typically AUDATA[0:7] are configured for
clock, where Fs is the output sample rate. outputting either left justified or I2S formatted data.
In a standard 5.1 channel AVR, AUDATA0,
SCLK0 is the bit clock used to clock data out on
AUDATA1 and AUDATA2 are used to output the
AUDATA0, AUDATA1, AUDATA2 and
six discrete channels (Left, Center, Right, Left
AUDATA3. LRCLK0 is the data framing clock
Surround, Right Surround, and Subwoofer).
whose frequency is typically equal to the sampling
frequency for AUDATA0, AUDATA1, AUDATA3 can be used with AUDATA0,
AUDATA2 and AUDATA3. AUDATA1 and AUDATA2 to support 7.1 output.
Alternatively AUDATA3 and AUDATA7 can be
SCLK1 is the bit clock used to clock data out on
used for dual zone support. AUDATA3 and
AUDATA4, AUDATA5, AUDATA6 and
AUDATA7 are multiplexed with the XMT958
AUDATA7. LRCLK1 is the data framing clock
output so only one can be used at any one time.
whose frequency is typically equal to the sampling
frequency for AUDATA4, AUDATA5, Please refer to AN208, AN209 and their
AUDATA6 and AUDATA7. corresponding appendices for information about
which output modes are supported, as this is
LRCLK0, LRCLK1, SCLK0 and SCLK1 can be
specific to each application code.
configured as either inputs (Slave) or outputs
(Master). A valid MCLK is required for all output 11.6.1 S/PDIF Outputs
modes. When LRCLK0, LRCLK1, SCLK0 and
Both AUDATA3 and AUDATA7 digital audio
SCLK1 are configured as outputs, they are derived
output ports are unique, in that they can serve either
from MCLK. Whether MCLK is configured as an
an additional output for I2S or Left Justified PCM
input or an output, an internal divider from the
data OR as IEC60959 bi-phase mark encoded data
MCLK signal is used to produce LRCLK0,
S/PDIF transmitters. When either of these ports are
LRCLK1, SCLK0 and SCLK1. The ratios shown
configured as a S/PDIF transmitter, the MCLK
in Table 26 give the possible SCLK values for
required for such functionality can be provided
from either the internally locked PLL or from an

82
MCLK input. All consumer channel status DAO Data Format Of
information can be included in the S/PDIF stream, AUDATA0, 1, 2 (or
provided that the particular application code B AUDATA0 for Multichannel Hex
supports this functionality. Value Modes) Message
0 I2S 24-bit 0x81800003
When configured as a S/PDIF transmitter, the (default) (Configuration of AUDATA3 as 0xFFFE3FFF
designer should understand that in order for these S/PDIF (IEC60958) or Digital Audio 0x81400003
ports to be fully IEC60958 compliant, the outputs in the format of I2S or Left Justified is 0x0001C000
would need to be buffered through an RS422 covered in AN209) 0x81000005
device or an optocoupler as its outputs are only 0x00101701
0x81000006
CMOS driven. 0x00100001
11.7 Output Data Hardware Configuration 0x81000007
0x00100001
The DAO naming convention is as follows: 0x81000008
0x00100001
OUTPUT A B C D,
1 Left Justified 24-bit 0x81800003
where the parameters are defined as: (Configuration of AUDATA3 as 0xFFFE3FFF
S/PDIF (IEC60958) or Digital Audio 0x81400003
A - DAO Mode (Master/Slave for LRCLK0, in the format of I2S or Left Justified is 0x0000C000
LRCLK1, SCLK0 and SCLK1) covered in AN209) 0x81000005
0x00101701
B - Data Format 0x81000006
C - MCLK, SCLK, LRCLK Frequency 0x00100000
0x81000007
The following tables show the different values for 0x00100000
each parameter as well as the hex message that 0x81000008
needs to be sent. When creating the hardware 0x00100000
configuration message, only one hex message Table 28. Output Data Configuration Parameter B)
should be sent per parameter.
Hex
A DAO Modes (LRCLK and C Value SCLK/LRCLK Frequency Message
Value SCLK) Hex Message 0 MCLK = 256 FS 0x81800003
0 MCLK - Slave 0x81800003 (default) 0xFFFFFC7F
(default) SCLK0 - Slave 0x00101000 0x81400003
LRCLK0 - Slave 0x00000100
SCLK1 - Slave SCLK = MCLK / 4 = 64 FS 0x81000009
LRCLK1 - Slave LRCLK = SCLK / 64 = FS 0x00077030
1 MCLK - Slave 0x81800003 1 MCLK = 256 FS 0x81800003
SCLK0 - Master 0xFFEFFFFF 0xFFFFFC7F
LRCLK0 - Master 0x81400003
SCLK1 - Master 0x00000200
LRCLK1 - Master SCLK = MCLK / 2 = 128 FS 0x81000009
LRCLK = SCLK / 128 = FS 0x00177010
Table 27. Output Clock Configuration
(Parameter A) Table 29. Output SCLK/LRCLK Configuration
(Parameter C)

83
 Hex This is the default configuration so no
C Value SCLK/LRCLK Frequency Message configuration message is required.
2 MCLK = 256 FS 0x81800003 DAI:Left Justified
0xFFFFFC7F
0x81400003 PCM and Compressed data
0x00000300 CDI:Not used
SCLK = MCLK / 1 = 256 FS 0x81000009
LRCLK = SCLK / 256 = FS 0x00377000 The above configuration corresponds to
3 MCLK = 512 FS 0x81800003 INPUT A1 B1
0xFFFFFC7F
0x81400003 which corresponds to a configuration message of:
0x00000100
SCLK = MCLK / 8 = 64 FS 0x81000009
0x800210
LRCLK = SCLK / 64 = FS 0x00077070 0x3FBFC0
4 MCLK = 128FS 0x81800003 0x800110
0xFFFFFC7F 0xC0002C
0x81400003
0x00000100 0x800217
SCLK = MCLK / 2 = 64FS 0x81000009 0x8080FF
LRCLK = SCLK / 64 = FS 0x00077010 0x80021A
Table 29. Output SCLK/LRCLK Configuration 0x8080FF
(Parameter C) 0x800117
0x001000
Hex
D Value SCLK Polarity Message
0x80011A
0 Data Valid on Rising Edge 0x81800003 0x001800
(default) (clocked out on falling) 0xFFFBFFFF
1 Data Valid on Falling Edge 0x81400003
(clocked out on rising) 0x00040000 DAO:Left Justified slave mode (LRCLK,
Table 30. Output SCLK Polarity Configuration
SCLK inputs)
(Parameter D) MCLK @ 256Fs
SCLK @ 64Fs
11.8 Creating Hardware Configuration
The above configuration corresponds to
Messages
The single hardware configuration message that OUTPUT A0 B1 C0 D0
must be sent to the CS49400 after download or soft which has a configuration message of:
reset should be a concatenation of the messages in 0x81800003
the previous sections. The complete hardware
0xFFFE3FFF
configuration message should be created by taking
a message for each parameter (where the default is 0x81400003
not acceptable) and concatenating the messages 0x0000C000
together. No messages need to be sent if the default 0x81000005
configuration for a particular parameter is
acceptable. This example can be easily expanded to 0x00101701
fit other system requirements. 0x81000006
E.g. if the host system has this configuration: 0x00100000
Address Checking: Disabled 0x81000007

84
 0x00100000 2 0x3FBFC0 8 0x8080FF
0x81000008 3 0x800110 9 0x800117
0x00100000 4 0xC0002C 10 0x001000
5 0x800217 11 0x80011A
Concatenating the messages together gives the
hardware configuration message shown in 6 0x8080FF 12 0x001800
Table 31, “Example Values to be Sent to DSPAB Table 31. Example Values to be Sent to DSPAB After
After Download or Soft Reset,” on page 85, which Download or Soft Reset
should be sent to DSPAB after download or soft
reset. Table 32, “Example Values to be Sent to
WORD# VALUE WORD# VALUE
DSPC After Download or Soft Reset,” on page 85,
which should be sent to DSPC after download or 1 0x81000006 12 0x81000007
soft reset. 2 0x00101700 13 0x00100000
3 0x81000006 14 0x81000008
4 0x00100000 15 0x00100000
WORD# VALUE WORD# VALUE
1 0x800210 7 0x80021A Table 32. Example Values to be Sent to DSPC After
Download or Soft Reset
Table 31. Example Values to be Sent to DSPAB After
Download or Soft Reset

85
12.0 PIN DESCRIPTION
12.1 144-Pin LQFP Package Pin Layout

AUDATA7, XMT958B, GPIO31

AUDATA3, XMT958A

SD_ADDR3 ,EXTA3
SD_ADDR2 ,EXTA2
SD_ADDR1 ,EXTA1
SD_ADDR0, EXTA0
SDATAN0, GPIO24
SDATAN1, GPIO25
SDATAN2, GPIO26
SDATAN3, GPIO27
AUDATA4, GPIO28

AUDATA5, GPIO29
AUDATA6, GPIO30

LRCLKN, GPIO23
SCLKN, GPIO22
HDATA3, GPIO3

HDATA4, GPIO4

HDATA5, GPIO5
HDATA6, GPIO6
HDATA7, GPIO7
AUDATA2

SD_CAS
SD_RAS
LRCLK0

LRCLK1
SCLK0

SCLK1
MCLK
VDD2

VDD1
VSS2

VSS1

NC1
NC2

NC3
NC4
105

100

90

85

75
95

80
AUDATA1 SD_ADDR10, EXTA10
AUDATA0 110 SD_BA, EXTA19
CMPCLK, FSCLKN2 70 VDDSD1
HDATA2, GPIO2 VSSSD1
VSS3 SD_CS
VDD3 SD_ADDR4, EXTA4
HDATA1, GPIO1 115 SD_ADDR5, EXTA5
HDATA0, GPIO0 65 SD_ADDR6, EXTA6
CMPREQ, FLRCLKN2 SD_CLK_EN
CMPDAT, FSDATAN2 SD_ADDR7, EXTA7
FLRCLKN1 SD_ADDR8, EXTA8
WR, DS, GPIO10 120 SD_CLK_IN
RD, R/W, GPIO11 60 SD_ADDR9, EXTA9
PLLVSS SD_CLK_OUT
FILT2 VDDSD2
FILT1 VSSSD2
PLLVDD 125 SD_DATA8, EXTA11
XTALO 55 SD_DATA9, EXTA12
CLKIN, XTALI SD_DATA10, EXTA13
CLKSEL SD_DATA11, EXTA14
CS, GPIO9 SD_DATA12, EXTA15
A0, GPIO13 130 VDDSD3
FSDATAN1 50 VSSSD3
VDD4 SD_DATA13, EXTA16
VSS4 NC5
FSCLKN1, STCCLK2 SD_DATA14, EXTA17
SCS 135 SD_DATA15, EXTA18
SCDIN 45 SD_DQM1
VSS5 SD_DATA7, EXTD7
VDD5 SD_DATA6, EXTD6
A1, GPIO12 VDDSD4
SCDOUT, SCDIO 140 VSSSD4
HINBSY, GPIO8 40 SD_DATA5, EXTD5
SCCLK SD_DQM0
UHS2, CS_OUT, GPIO17 SD_DATA4, EXTD4
RESET 144 SD_DATA3, EXTD3
35
25

30
20
10

15
5
1
UHS0, GPIO18
UHS1, GPIO19

FA1, FSCDIN
GPIO20
FAO, FSCCLK
FHS2, FSCDIO, FSCDOUT
GPIO21
FDAT7
VDD6
VSS6
FHS0, FWR, FDS
FHS1, FRD, FR/W
FDAT6
FCS
FINTREQ
FDBCK
FDAT5
FDAT4
VDD7
VSS7
FDAT3
FDBDA
FDAT2
DBDA
DBCK
FDAT1
TEST
FDAT0
NV_WE, GPIO16
NV_OE, GPIO15
NV_CS, GPIO14
SD_WE
SD_DATA0, EXTD0
SD_DATA1, EXTD1
SD_DATA2, EXTD2
INTREQ

Figure 57. Pin Layout (144-Pin LQFP Package)

86
 SCCLK
SCS
CLKIN, XTALI
PLLVSS

FSCLKN1, STCCLK2
FILT1
CMPDAT, FSDATAN2

UHS2, CS_OUT, GPIO17

VDD5
FSDATAN1
FLRCLKN1
VSS3
AUDATA0
AUDATA1

CMPREQ, FLRCLKN2
CMPCLK, FSCLKN2

SCDOUT, SCDIO
XTALO
PLLVDD

SCDIN
VSS5 95
CLKSEL 90
VDD3 80

FILT2 85

RESET 100
UHS0, GPIO18 1 75 LRCLK0
UHS1, GPIO19 AUDATA2
INTREQ AUDATA3, XMT958A
FA1, FSCDIN SCLK0
FA0, FSCCLK 5 AUDATA4, GPIO28
FHS2, FSCDIO, FSCDOUT 70 VSS2
VDD6 VDD2
VSS6 MCLK
12.2 100-Pin LQFP Package Pin Layout

FHS0, FWR, FDS SCLK1

FHS1, FRD, FR/W 10 AUDATA5, GPIO29
FCS 65 AUDATA6, GPIO30
FINTREQ AUDATA7, XMT958B, GPIO31
FDBCK VSS1
VDD7 VDD1
VSS7 15 LRCLK1
FDBDA 60 SCLKN, GPIO22
DBDA LRCLKN, GPIO23
DBCK SDATAN0, GPIO24
TEST SDATAN1, GPIO25
NV_WE, GPIO16 20 SDATAN2, GPIO26

Figure 58. Pin Layout (100-Pin LQFP Package)

NV_OE, GPIO15 55 SDATAN3, GPIO27
NV_CS, GPIO14 EXTA3
EXTD0 EXTA2
EXTD1 EXTA1
EXTD2 25 EXTA0
EXTA9
EXTA8
EXTA7
EXTA6
45 EXTA5
EXTA4

EXTD3
EXTD4
EXTD5
EXTD6
EXTD7
EXTA18
EXTA17
35 EXTA16
EXTA15
EXTA14
EXTA13
EXTA12
40 EXTA11
EXTA19
50 EXTA10

VSSSD4
VSSSD1

30 VDDSD4
VDDSD1

87
12.3 Pin Definitions
FILT1 — Phase-Locked Loop Filter
Connects to an external filter for the on-chip phase-locked loop.

FILT2 — Phase Locked Loop Filter

Connects to an external filter for the on-chip phase-locked loop.

CLKIN, XTALI — External Clock Input/Crystal Oscillator Input

CS49400 clock input. This pin accepts an external clock input signal that is used to drive the
internal core logic. When in internal clock mode (CLKSEL == VSS), this input is connected to
the internal PLL from which all internal clocks are derived. When in external clock mode
(CLKSEL == VDD), this input is connected to the DSP clock. Alternatively, a 12.288 mhZ
crystal oscillator can be connected between XTALI and XTALO. INPUT

XTALO — Crystal Oscillator Output

Crystal oscillator output. OUTPUT

CLKSEL — DSP Clock Select

This pin selects the internal source clock. When CLKSEL is low, CLKIN is connected to the
internal PLL from which all internal clocks are derived. When CLKSEL is high, the PLL is
bypassed and the external clock directly drives all input logic. INPUT

FDAT7 — DSPAB Bidirectional Data Bus

FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
In parallel host mode, these pins provide a bidirectional data bus to DSPAB. These pins have
an internal pull-up.
BIDIRECTIONAL - Default: INPUT

FA0, FSCCLK — Host Parallel Address Bit Zero or Serial Control Port Clock
In parallel host mode, this pin serves as one of two address input pins used to select one of
four parallel registers. In serial host mode, this pin serves as the serial control clock signal,
specifically as the SPI clock input. INPUT

88
FA1, FSCDIN — Host Address Bit One or SPI Serial Control Data Input
In parallel host mode, this pin serves as one of two address input pins used to select one of
four parallel registers. In SPI serial host mode, this pin serves as the data input. INPUT

FHS1, FRD, FR/W — Mode Select Bit 1 or Host Parallel Output Enable or Host Parallel R/W
DSPAB control port mode select bit 1. This bit is one of 3 control port select bits that are
sampled on the rising edge of RESET to determine the control port mode of DSPAB. In Intel
parallel host mode, this pin serves as the active-low data bus enable input. In Motorola parallel
host mode, this pin serves as the read-high/write-low control input signal. In serial host mode,
this pin can serve as the external memory active-low data-enable output signal.
BIDIRECTIONAL - Default: INPUT

FHS0, FWR, FDS — Mode Select Bit 0 or Host Write Strobe or Host Data Strobe
DSPAB control port mode select bit 0. This bit is one of 3 control port select bits that are
sampled on the rising edge of RESET to determine the control port mode of DSPAB. In Intel
parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola
parallel host mode, this pin serves as the active-low data-strobe-input signal. In serial host
mode, this pin can serve as the external-memory active-low write-enable output signal.
BIDIRECTIONAL - Default: INPUT

FCS — Host Parallel Chip Select, Host Serial SPI Chip Select
In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host
SPI mode, this pin is used as the active-low chip-select input signal. INPUT

FHS2, FSCDIO, FSCDOUT — Mode Select Bit 2 or Serial Control Port Data Input and Output, Par-
allel Port Type Select
DSPAB control port mode select bit 2. This bit is one of 3 control port select bits that are
sampled on the rising edge of RESET to determine the control port mode of DSPAB. In SPI
mode this pin serves as the data output pin. In parallel host mode, this pin is sampled at the
rising edge of RESET to configure the parallel host mode as an Intel type bus or as a
Motorola type bus. BIDIRECTIONAL - Default: INPUT

FINTREQ — Control Port Interrupt Request

Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has
outgoing control data that should be read by the host.
OPEN DRAIN I/O - Requires 3.3K Ohm Pull-Up

FSCLKN1, STCCLK2 — PCM Audio Input Bit Clock

Digital-audio bit clock input. FSCLKN1 operates asynchronously from all other DSPAB clocks.
In master mode, FSCLKN1 is derived from DSPAB’s internal clock generator. The active edge
of FSCLKN1 can be programmed by the DSP.
BIDIRECTIONAL - Default: INPUT

FLRCLKN1 — PCM Audio Input Sample Rate Clock

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 Digital-audio frame clock input. FLRCLKN1 typically is run at the sampling frequency.
FLRCLKN1 operates asynchronously from all other DSPAB clocks. The polarity of FLRCLKN1
for a particular subframe can be programmed by the DSP.
BIDIRECTIONAL - Default: INPUT

FSDATAN1 — PCM Audio Data Input One

Digital-audio data input that can accept from one compressed line or 2 channels of PCM data.
FSDATAN1 can be sampled with either edge of FSCLKN1, depending on how FSCLKN1 has
been configured. INPUT

CMPCLK, FSCLKN2 — PCM Audio Input Bit Clock

Digital-audio bit clock input. FSCLKN2 operates asynchronously from all other DSPAB clocks.
The active edge of FSCLKN2 can be programmed by the DSP.
BIDIRECTIONAL - Default: INPUT

CMPDAT, FSDATAN2 — PCM Audio Data Input Number Two

Digital-audio data input that can accept either one compressed line or 2 channels of PCM
data. FSDATAN2 can be sampled with either edge of FSCLKN2, depending on how FSCLKN2
has been configured.
BIDIRECTIONAL - Default: INPUT

FDBCK — Reserved
This pin is reserved and should be pulled up with an external 3.3k resistor. INPUT
FDBDA — Reserved
This pin is reserved and should be pulled up with an external 3.3k resistor.
BIDIRECTIONAL - Default: INPUT

PLLVDD — PLL Supply Voltage

2.5 V PLL supply.

PLLVSS — PLL Ground Voltage

PLL ground.

RESET — Master Reset Input

Asynchronous active-low master reset input. Reset should be low at power-up to initialize the
DSP and to guarantee that the device is not active during initial power-on stabilization periods.
At the rising edge of reset the host interface mode of DSPAB is selected contingent on the
state of the FHS0, FHS1, and FHS2 pins. At the rising edge of reset the host interface mode
of DSPC is selected contingent on the state of the UHSO, UHS1, and UHS2 pins. If reset is
low all bidirectional pins are high-Z inputs. INPUT

TEST — Reserved

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 This should be tied low for normal operation. INPUT

MCLK — Audio Master Clock

Bidirectional master audio clock. As an output, MCLK provides a low jitter oversampling clock.
MCLK supports all standard oversampling frequencies. BIDIRECTIONAL - Default: INPUT
SCLK0 — Audio Output Bit Clock
Bidirectional digital-audio output bit clock for AUDATA0, AUDATA1, AUDATA2, and AUDATA3.
As an output, SCLK0 can provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs frequencies and is
synchronous to MCLK. As an input, SCLK0 is independent of MCLK.
BIDIRECTIONAL - Default: INPUT

SCLK1 — Audio Output Bit Clock

Bidirectional digital-audio output bit clock for AUDATA4, AUDATA5, AUDATA6, and AUDATA7.
As an output, SCLK1 can provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs frequencies and is
synchronous to MCLK. As an input, SCLK1 is independent of MCLK.
BIDIRECTIONAL - Default: INPUT

LRCLK0 — Audio Output Sample Rate Clock

Bidirectional digital-audio output frame clock for AUDATA0, AUDATA1, AUDATA2, and
AUDATA3. As an output, LRCLK0 can provide all standard output sample rates up to 192 kHz
and is synchronous to MCLK. As an input, LRCLK0 is independent of MCLK.
BIDIRECTIONAL - Default: INPUT

LRCLK1 — Audio Output Sample Rate Clock

Bidirectional digital-audio output frame clock for AUDATA4, AUDATA5, AUDATA6, and
AUDATA7. As an output, LRCLK1 can provide all standard output sample rates up to 192 kHz
and is synchronous to MCLK. As an input, LRCLK1 is independent of MCLK.
BIDIRECTIONAL - Default: INPUT

AUDATA0 — Digital Audio Output 0

PCM digital-audio data output. OUTPUT

AUDATA1 — Digital Audio Output 1

PCM digital-audio data output. OUTPUT

AUDATA2 — Digital Audio Output 2

PCM digital-audio data output. OUTPUT

AUDATA3, XMT958A — Digital Audio Output 3, S/PDIF Transmitter

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 CMOS level output that outputs a biphase-mark encoded (S/PDIF) IEC60958 signal or digital
audio data which is capable of carrying two channels of PCM digital audio. OUTPUT

AUDATA4, GPIO28 — Digital Audio Output 4, General Purpose I/O

PCM digital-audio data output. This pin can act as a general-purpose input or output that can
be individually configured and controlled by DSPC. BIDIRECTIONAL - Default: OUTPUT
AUDATA5, GPIO29 — Digital Audio Output 5, General Purpose I/O
PCM digital-audio data output. This pin can act as a general-purpose input or output that can
be individually configured and controlled by DSPC. BIDIRECTIONAL - Default: OUTPUT
AUDATA6, GPIO30 — Digital Audio Output 6, General Purpose I/O
PCM digital-audio data output. This pin can act as a general-purpose input or output that can
be individually configured and controlled by DSPC. BIDIRECTIONAL - Default: OUTPUT
AUDATA7, XMT958B, GPIO31 — Digital Audio Output 7, S/PDIF Transmitter, General Purpose I/O
CMOS level output that contains a biphase-mark encoded (S/PDIF) IEC60958 signal or digital
audio data which is capable of carrying two channels of PCM digital audio. This pin can also
act as a general-purpose input or output that can be individually configured and controlled by
DSPC. BIDIRECTIONAL - Default: OUTPUT
DBCK — Debug Clock
Must be tied high to 3.3k ohm resistor. INPUT

DBDA — Debug Data

Must be tied high to 3.3k ohm resistor. BIDIRECTIONAL - Default: INPUT

SLCKN, GPIO22 — PCM Audio Input Bit Clock, General Purpose I/O
Digital-audio bit clock that is an input. SCLKN operates asynchronously from all other DSPAB
clocks. The active edge of SCLKN can be programmed by the DSP. This pin can act as a
general-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: INPUT

LRCLKN, GPIO23 — PCM Audio Input Sample Rate Clock, General Purpose I/O
Digital-audio frame clock input. LRCLKN operates asynchronously from all other DSPAB
clocks. The polarity of LRCLKN for a particular subframe can be programmed by the DSP.
This pin can act as a general-purpose input or output that can be individually configured and
controlled by DSPC. BIDIRECTIONAL - Default: INPUT

SDATAN0, GPIO24 — PCM Audio Input Data, General Purpose I/O

Digital-audio PCM data input. This pin can act as a general-purpose input or output that can
be individually configured and controlled by DSPC. BIDIRECTIONAL - Default: INPUT

SDATAN1, GPIO25 — PCM Audio Input Data, General Purpose I/O

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 Digital-audio PCM data input. This pin can act as a general-purpose input or output that can
be individually configured and controlled by DSPC. BIDIRECTIONAL - Default: INPUT

SDATAN2, GPIO26 — PCM Audio Input Data, General Purpose I/O

Digital-audio PCM data input. This pin can act as a general-purpose input or output that can
be individually configured and controlled by DSPC. BIDIRECTIONAL - Default: INPUT

SDATAN3, GPIO27 — PCM Audio Input Data, General Purpose I/O

Digital-audio PCM data input. This pin can act as a general-purpose input or output that can
be individually configured and controlled by DSPC. BIDIRECTIONAL - Default: INPUT

SCS — Host Serial SPI Chip Select

SPI mode active-low chip-select input signal. INPUT

SCCLK — Serial Control Port Clock

This pin serves as the serial SPI clock input. INPUT

SCDIN — SPI Serial Control Data Input

In SPI mode this pin serves as the data input pin. INPUT

SCDOUT, SCDIO — Serial Control Port Data Input and Output

In SPI mode this pin serves as the data output pin. BIDIRECTIONAL - Default: OUTPUT in
SPI mode

INTREQ — Control Port Interrupt Request

Open-drain interrupt-request output. This pin is driven low to indicate that DSPC has outgoing
control data and should be serviced by the host.
OPEN DRAIN I/O - Requires 3.3K Ohm Pull-Up

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HDATA7, GPIO7 — DSPC Bidirectional Data Bus, General Purpose I/O
HDATA6, GPIO6
HDATA5, GPIO5
HDATA4, GPIO4
HDATA3, GPIO3
HDATA2, GPIO2
HDATA1, GPIO1
HDATA0, GPIO0
In parallel host mode, these pins provide a bidirectional data bus. These pins can also act as
general purpose input or output pins that can be individually configured and controlled by
DSPC. These pins have an internal pull-up. BIDIRECTIONAL - Default: INPUT

A0, GPIO13 — Host Parallel Address Bit 0, General Purpose I/O

In parallel host mode, this pin serves as the LS Bit of a two bit address input used to select
one of four parallel registers. This pin can act as a general-purpose input or output that can be
individually configured and controlled by DSPC. BIDIRECTIONAL - Default: INPUT

A1, GPIO12 — Host Address Bit 1, General Purpose I/O

In parallel host mode, this pin serves as the MS Bit of a two bit address input used to select
one of four parallel registers. This pin can act as a general-purpose input or output that can be
individually configured and controlled by DSPC. BIDIRECTIONAL - Default: INPUT

RD, R/W, GPIO11 — Host Parallel Output Enable, Host Parallel R/W, General Purpose I/O
In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola
parallel host mode, this pin serves as the read-high/write-low control input signal. This pin can
act as a general-purpose input or output that can be individually configured and controlled by
DSPC. This pin has an internal pull-up. BIDIRECTIONAL - Default: INPUT

WR, DS, GPIO10 — Host Write Strobe, Host Data Strobe, General Purpose I/O
In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola
parallel host mode, this pin serves as the read-high/write-low control input signal. In serial host
mode, this pin can serve as a general purpose input or output bit. This pin can act as a
general-purpose input or output that can be individually configured and controlled by DSPC.
This pin has an internal pull-up.
BIDIRECTIONAL - Default: INPUT

CS, GPIO9 — Host Parallel Chip Select, General Purpose I/O

In parallel host mode, this pin serves as the active-low chip-select input signal. This pin can
act as a general-purpose input or output that can be individually configured and controlled by
DSPC. This pin has an internal pull-up. BIDIRECTIONAL - Default: INPUT

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HINBSY, GPIO8 — Input Host Message Status, General Purpose I/O
This pin indicates that serial or parallel communication data written to the DSP has not been
read yet. This pin can act as a general-purpose input or output that can be individually
configured and controlled by DSPC. This pin has an internal pull-up. BIDIRECTIONAL -
Default: OUTPUT
SD_DATA15, EXTA18 — SDRAM Data Bus, SRAM External Address Bus
SD_DATA14, EXTA17
SD_DATA13, EXTA16
SD_DATA12, EXTA15
SD_DATA11, EXTA14
SD_DATA10, EXTA13
SD_DATA9, EXTA12
SD_DATA8, EXTA11
SDRAM data bus 15:8. SRAM external address bus 18:11. OUTPUT

SD_DATA7, EXTD7 — SDRAM Data Bus, SRAM External Data Bus

SD_DATA6, EXTD6
SD_DATA5, EXTD5
SD_DATA4, EXTD4
SD_DATA3, EXTD3
SD_DATA2, EXTD2
SD_DATA1, EXTD1
SD_DATA0, EXTD0
SDRAM data bus 7:0. SRAM external data bus 7:0. BIDIRECTIONAL - Default: INPUT

SD_ADDR10, EXTA10 — SDRAM Address Bus, SRAM External Address Bus

SD_ADDR9, EXTA9
SD_ADDR8, EXTA8
SD_ADDR7, EXTA7
SD_ADDR6, EXTA6
SD_ADDR5, EXTA5
SD_ADDR4, EXTA4
SD_ADDR3, EXTA3
SD_ADDR2, EXTA2
SD_ADDR1, EXTA1
SD_ADDR0, EXTA0
SDRAM address bus 10:0. SRAM external address bus 10:0. OUTPUT

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SD_CLK_OUT — SDRAM Clock Output
SDRAM clock output. OUTPUT

SD_CLK_IN — SDRAM Re-timing Clock Input

SDRAM re-timing clock input. INPUT

SD_CLK_EN — SDRAM Clock Enable

SDRAM clock enable. OUTPUT

SD_BA, EXTA19 — SDRAM Bank Address Select, SRAM External Address Bus
SDRAM bank address select. SRAM external address bus 19. OUTPUT

SD_CS — SDRAM Chip Select

SDRAM chip select. OUTPUT

SD_RAS — SDRAM Row Address Strobe

SDRAM row address strobe. OUTPUT

SD_CAS — SDRAM Column Address Strobe

SDRAM column address strobe. OUTPUT

SD_WE — SDRAM Write Enable

SDRAM write enable. OUTPUT

SD_DQM1 — SDRAM Data Mask 1

SDRAM data mask 1. OUTPUT

SD_DQM0 — SDRAM Data Mask 2

SDRAM data mask 0. OUTPUT

NV_CS, GPIO14 — SRAM Chip Select, General Purpose I/O

SRAM/Flash chip select. This pin can act as a general-purpose input or output that can be
individually configured and controlled by DSPC. BIDIRECTIONAL - Default: OUTPUT

NV_OE, GPIO15 — SRAM Output Enable, General Purpose I/O

SRAM/Flash output enable. This pin can act as a general-purpose input or output that can be
individually configured and controlled by DSPC. BIDIRECTIONAL - Default: OUTPUT

96
NV_WE, GPIO16 — SRAM Write Enable, General Purpose I/O
SRAM/Flash write enable. This pin can act as a general-purpose input or output that can be
individually configured and controlled by DSPC. BIDIRECTIONAL - Default: OUTPUT

UHS2, CS_OUT, GPIO17 — Mode Select Bit 2, External Serial Memory Chip Select,
General Purpose I/O
DSPC control port mode select bit 2. This pin is sampled at the rising edge of RESET and is
one of three pins used to select the control port mode. In serial control port mode, this pin can
serve as an output to provide the chip-select for a serial EEPROM. This pin can act as a
general-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: INPUT

UHS0, GPIO18 — Mode Select Bit 0, General Purpose I/O

DSPC control port mode select bit 0. This pin is sampled at the rising edge of RESET and is
one of three pins used to select the control port mode. This pin can act as a general-purpose
input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: INPUT

UHS1, GPIO19 — Mode Select Bit 1, General Purpose I/O

DSPC control port mode select bit 1. This pin is sampled at the rising edge of RESET and is
one of three pins used to select the control port mode. This pin can act as a general-purpose
input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: INPUT

GPIO20 — General Purpose I/O

This pin can act as a general-purpose input or output that can be individually configured and
controlled by DSPC. This pin has an internal pull-up.
BIDIRECTIONAL - Default: INPUT

GPIO21 — General Purpose I/O

This pin can act as a general-purpose input or output that can be individually configured and
controlled by DSPC.This pin has an internal pull-up.
BIDIRECTIONAL - Default: INPUT

VDD[7:1] — 2.5V Supply Voltage

2.5V supply voltage.

VSS — 2.5V Ground

2.5V ground.

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NC[5:1] — No Connect
Recommended tie to ground.

VDDSD[4:1] — 3.3V SDRAM/SRAM/EPROM Interface Supply

3.3V SDRAM/SRAM/EPROM supply.

VSSSD — 3.3V SDRAM/SRAM/EPROM Interface Ground

3.3V ground.

13. ORDERING INFORMATION

CS494002-CQ 144-pin, accommodates SRAM/SDRAM
CS494502-CQ 100-pin, external SRAM memory interface only (no SDRAM), no parallel-control ports, no
FLASH programming.
(Contact the factory for the 100-pin package pin-out and dimension drawing)
Temp Range 0-70º C for both parts

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14. PACKAGE DIMENSIONS
14.1 144-Pin LQFP Package

E
E1

D D1

1
Note: See Legend Below
e B
Θ A

A1
L Figure 59. 144-Pin LQFP Package Drawing

INCHES MILLIMETERS
DIM MIN NOM MAX MIN
A --- 0.55 0.063 ---
A1 0.002 0.004 0.006 0.05
B 0.007 0.008 0.011 0.17
D 0.854 0.866 BSC 0.878 21.70
D1 0.783 0.787 BSC 0.791 19.90
E 0.854 0.866 BSC 0.878 21.70
E1 0.783 0.787 BSC 0.791 19.90
e 0.016 0.020 0.024 0.40
Θ 0.000° 4° 7.000° 0.00°
L 0.018 0.024 0.030 0.45

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