SOUTH EASTERN KENYA UNIVERSITY

SCHOOL OF PURE AND PHYSICAL SCIENCES

DEPARTMENT OF PHYSICAL SCIENCES
UNIT CODE: SPH 312/309 UNIT NAME: DIGITAL ELECTRONICS
LECTURER: Ngumbi PK EMAIL: pngumbi@seku.ac.ke

Purpose
To provide students with the fundamentals of digital electronics technology and concepts

Expected Learning Outcomes

By the end of the course the learner should be able to:
i) Describe various digital electronics concept
ii) Perform simple digital operation involving number systems
iii) Design and implement simple digital circuits
iv) Develop hands–on-experience and understanding of the design of digital and basic components
of a complete digital electronic hardware.

Course Content
Number system: Binary, Decimal, Octal, Hexadecimal and their conversion; Logic gates and truth tables;
Boolean algebra complement; Simplification techniques; combinational circuits: Decoders and encoders;
Code converters; Multiplexers and demultiplexers; Arithmetic circuits; Logic circuit families; Digital
memories; Interfacing: Analogue/digital converters; Digital/analogue converters; Introduction to
integrated circuit technology

Teaching/Learning Methodologies: Lectures; Tutorials; Class discussion, Laboratory sessions

Instructional Materials and Equipment: Handouts; projector, whiteboard and Laboratory equipment.

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Course Assessment
Examination - 70%; Continuous Assessments (Exercises and Tests) - 30%; Total - 100%

Recommended Text Books

i) Bignell; (2009)Digital Electronics: Logic And Systems, With Cd. Thomson Business
InformationISBN: 8131509567
ii) Anil K. Maini; (2007). Digital Electronics: Principles And Integrated Circuits. Wiley
ISBN: 8126514663
iii) Satish Jain (2006); Guide To Digital Electronics And Devices(question & Answer).
ISBN: 8183331459
iv) D C Green (1999); Digital Electronics; Harlow Longman 1999 London
v) William Weitz (2006);Digital Electronic A Practical approach; Prentice Hall (2007) New Jersey
USA

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1. WEEK 1-2: DIGITAL NUMBER SYSTEMS.................................................................................. 1

1.1 INTRODUCTION .................................................................................................................................. 1

1.2 DIGITAL SYSTEMS AND INFORMATION REPRESENTATION ................................................................... 1
1.3 DIGITAL NUMBERS ............................................................................................................................ 2
1.3.1 The Decimal numbers ............................................................................................................... 2
1.3.2 The Binary numbers .................................................................................................................. 2
1.3.3 The Octal numbers .................................................................................................................... 5
1.3.4 Hexadecimal numbers ............................................................................................................... 6
1.4 SIGNED AND UNSIGNED NUMBERS ..................................................................................................... 8
1.4.1 Unsigned binary numbers ......................................................................................................... 8
1.4.2 Signed Binary numbers ............................................................................................................. 8
1.5 2‘S COMPLEMENT REPRESENTATION ................................................................................................. 8

2. WEEK 3: BINARY LOGIC SYSTEMS ......................................................................................... 10

2.1 BINARY LOGIC AND BASIC GATES ................................................................................................... 10

2.1.1 AND operation (AND gate) .................................................................................................... 10
2.1.2 OR operation (OR gate) .......................................................................................................... 10
2.1.3 NOT (complement) operation (NOT Gate or inverter)........................................................... 11
2.2 UNIVERSAL GATES .......................................................................................................................... 12
2.2.1 NAND gate ............................................................................................................................. 12
2.2.2 NOR gate ................................................................................................................................ 12

3. WEEK 4-5: BOOLEAN ALGEBRA ............................................................................................... 13

3.1 BOOLEAN ALGEBRA SET.................................................................................................................. 13

3.2 BOOLEAN IDENTITIES....................................................................................................................... 14
3.3 THE DEMORGAN‘S THEOREM .......................................................................................................... 15
3.3.1 First DeMorgan‘s theorem ...................................................................................................... 16
3.3.2 Second DeMorgan‘s theorem ................................................................................................. 16
3.4 DUALITY PRINCIPLE ......................................................................................................................... 16
3.5 SIMPLIFICATION TECHNIQUES .......................................................................................................... 16
3.5.1 Algebraic manipulation method .............................................................................................. 16
3.5.2 Karnaugh-Map (K-map) Simplification method .................................................................... 22
3.6 TWO-LEVEL IMPLEMENTATION ........................................................................................................ 28
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 3.7 CONVERSION FROM SOP TO POS USING K-MAP ............................................................................. 29

4. WEEK 6-7: DIGITAL MEMORIES .............................................................................................. 30

4.1 WHAT IS AN ELECTRONIC MEMORY? ............................................................................................... 30

4.2 REGISTERS ....................................................................................................................................... 30
4.3 COMPUTER MEMORIES .................................................................................................................... 31
4.3.1 Primary Storage Devices......................................................................................................... 32
4.3.2 Secondary Storage Devices..................................................................................................... 42

5. WEEK 8-9: INTERFACING ........................................................................................................... 46

5.1 ANALOGUE AND DIGITAL SIGNALS .................................................................................................. 46

5.2 INTERFACING PROCESS .................................................................................................................... 46
5.3 A/D CONVERTERS............................................................................................................................ 47
SAMPLING ....................................................................................................................................... 48
QUANTIZATION ............................................................................................................................... 49
5.4 D/A CONVERTERS............................................................................................................................ 56

6. WEEK 10-12: INTEGRATED CIRCUITS .................................................................................... 64

6.1 COMBINATIONAL LOGIC CIRCUITS .................................................................................................. 64

6.1.1 Arithmetic circuits .................................................................................................................. 66
6.1.2 Code Converters...................................................................................................................... 69
6.2 TECHNOLOGY AND CHARACTERISTICS OF ICS ................................................................................. 75
6.2.1 What is an Integrated Circuit? ................................................................................................ 75
6.2.2 Classification of ICs by structure ............................................................................................ 76
6.2.3 Advantages of ICs ................................................................................................................... 76
6.2.4 Drawbacks of ICs .................................................................................................................... 78
6.2.5 Levels of integrated circuits .................................................................................................... 78
6.2.6 Integrated circuit families ....................................................................................................... 79
6.2.7 IC Operational properties ........................................................................................................ 80

7. WEEK 13-15: REVISION AND EXAMS....................................................................................... 82

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 1. WEEK 1-2: DIGITAL NUMBER SYSTEMS
1.1 Introduction
In this lesson, students are expected to get more conversant with binary numbers and representation of
numeric values using the binary number system. The number system helps one to express and reason
about quantities and the currently employs the concept of place value to enable us to express any value by
combining only 10 symbols (0, 1, 2 …9), hence called a ―base 10‖ number system. To develop a
computer based number system, only two symbols (0,1) corresponding with the two states of a single bit
are available. However, the place value power allows our ―base 2‖ or binary number system to express
any value of choice. Based on binary representation of numbers, certain values (1, 2, 4, 8, 16, etc.) are
seen repeatedly and written as 1, 10, 100, 1000, 10000, etc, similar to their incremental place values in
this binary number system.

1.2 Digital systems and Information representation

Digital implies any process accomplished using discrete units i.e. single or group of units representing a
whole number. The main difference between analog and digital is that in digital, only two points are used
i.e. maximum and minimum points while in analog instantaneous points are used.
By converting continuous analog signals into a finite number of discrete states, a process called
digitization, then to the extent that the states are sufficiently well separated so that noise does create
errors, the resulting digital signals allow the following (slightly idealized):
 storage over arbitrary periods of time
 flawless retrieval and reproduction of the stored information
 flawless transmission of the information

Discrete elements of information are represented in a digital system by physical quantities called signals.
The most common are the electrical signals such as voltages and currents.
Generally, signals used have two discrete values and are hence said to be binary. Output and input signals
ranges are usually given names such as HIGH or LOW, TRUE or FALSE and 1 or 0.

Some information is intrinsically digital, so it is natural to process and manipulate it using purely digital
techniques e.g. number. The drawback to digitization is that a single analog signal (e.g. a voltage which
is a function of time, like a stereo signal) needs many discrete states, or bits, in order to give a
satisfactory reproduction. The explosion in digital techniques and technology has been made possible by
the incredible increase in the density of digital circuitry, its robust performance, its relatively low cost,
and its speed. This circuitry is based upon the transistor, which can be operated as a switch with two

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states. Hence, the digital information is intrinsically binary. So in practice, the terms digital and binary
are used interchangeably.
Digital logic design deals with the basic concepts and tools used to design digital hardware consisting of
logic circuits.

1.3 Digital Numbers

There are four main types of digital number systems. These are: Decimal numbers, Binary numbers,
Octal numbers and Hexadecimal numbers.

1.3.1 The Decimal numbers

Are numbers whose base of operation (radix) is 10 i.e. their coefficients are multiplied by powers of 10
and uses 10 distinct digits ranging from 0-9.

1.3.2 The Binary numbers

Are numbers whose base of operation is 2. They have only two digits i.e. 0 and 1. Consider a fuel
dispenser indicator in decimals and a binary odometer shown below.

Decimal fuel dispenser indicator Binary odometer

The readings as it starts to read are given in 4 digits. Similarly, the readings are given in 4 digits
When the reading goes to 10, the unit part sets a starting from 0000. Every unit of distance moved
carry to the tenths column and so on. This involves adds a 1 to the LSB. The first unit reading
resetting. becomes 0001. For the next unit, the LSB resets
while the second bit set to the carry (1) and so on.
 Note: All computers and digital systems use the binary representation.

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  Addition of binary numbers
Consider the examples below for two binary numbers (note the names of the operands for the addition).

 Subtraction of binary numbers

Consider the examples below for two binary numbers (note the names of the operands for the addition).

 Note that a borrow into a given column adds 2 to the minuend bit. In the first example, there is no
borrow. In example two, the subtrahend bit is 1 with the minuend bit 0, so it is necessary to borrow
from the second position. This gives a difference bit in the first position as 1 i.e. (2 + 0 – 1 = 1). In the
second position, the borrow is subtracted, so the borrow is necessary.
If the subtrahend is larger than the minuend, we
subtract the minuend from the subtrahend and give
the result a minus sign as shown here.

 Task
Work out the following

 Conversion of binary to decimal numbers

The decimal equivalent of a binary number can be found by expanding the numbers as a power series
with a base of 2, for example;

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  Note that each digit in a binary number is a 0 or a 1 and is called bits, which is an abbreviation of
binary digit. When a bit is equal to 0, it does not contribute to the sum during the conversion.
Therefore, the conversion to decimal can be obtained by adding the numbers with powers of two
corresponding to bits that are equal to 1.

(Generally the subscripts will be omitted, since it will be clear from the context.)
Convert the following binary into decimal
1111 (b) 110101 (c) 01001111
(d) 1011.01 (e) 11000.11

 Conversion of decimal numbers to binary

To convert from base 10 to binary, the number is throughout divided by 2. All the remainders are then
assembled in reverse order.
 Examples
Convert the following decimal numbers into binary form: 7910, 18510 and 62510

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 The largest number which can be represented by n bits is 2n - 1.
For example, with 4 bits the largest number is 11112 = 15.
The digit to the far left is known as the most significant bit
(MSB) since it is the bit representing the highest power of 2
while the digit to the far right is known as the least significant
bit (LSB) since it is the bit representing the lowest power of 2.
 A number with 4 binary digits (bits) is known as a
nibble while one with 8 bits is known as a byte.

 Conversion of decimal fractions to binary

 Example
Convert the decimal fraction 0.687510 into binary.

 Task
Convert the following decimal into binary numbers

1.3.3 The Octal numbers

Octal numbers are ones whose base (radix) is 8 and have 8 digits ranging from 0-7 with increasing or
decreasing powers of 8.

 Multiplication of octal numbers

 Example
Perform the multiplication (762)8 x (45)8

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  Conversion of octal numbers to decimal
 Example
Determine the equivalent decimal value of the following octal number
1278
1278 = 1(82) + 2(81) + 7(80) = 64 + 16 + 7 = (87)10
0.4078
0.4078 = 4(8-1) + 0(8-2) + 7(8-3) = 0.5 + 0 + 0.013671875 = (0.514)10
Note: Digits 8 and 9 do not appear in octal numbers.

 Task
Determine the equivalent octal value of the
following decimal number

1.3.4 Hexadecimal numbers

Hexadecimal numbers are to base-16 and range from 0-15 with increasing or decreasing powers of 16.
The first 10 digits of hexadecimal are borrowed from the decimal system and the letters A, B, C, D, E,
and F used for the values 10, 11, 12, 13, 14, and 15 respectively.

Both octal and Hexadecimal numbers systems are

useful (in working of microprocessors) for
representing binary quantities indirectly since they
their bases are powers of two i.e. 8 = 23 and 16 =
24. Each octal digit corresponds to 3 bits and each
hexadecimal digit corresponds to 4 bits. This
makes the binary string more compact (short)
hence convenient

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  Addition of hexadecimal numbers
 Example
Perform the addition;
(59F)16 + (E46)16

 Conversion of binary into octal or hexadecimal

This is done by partitioning the binary number into groups of three bits each for octal and four bits for
hexadecimal, starting from the binary point and proceeding to the left and to the right. The corresponding
octal digit is then assigned to each group as shown below.

 Task
Convert (11010100111101110.111001000110)2 into Octal and Hexadecimal equivalent

 Conversion of octal or hexadecimal into binary

This is done by reversing the above procedure. I.e. each octal digit is converted into three-bit binary
equivalent and the extra 0‘s deleted. Similarly, each hexadecimal digit is converted to its four-bit binary
equivalent as shown below.

 Task
Convert 8516, 3AD16, F2.5C16, and 3728 into their binary equivalent

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 1.4 Signed and Unsigned numbers
1.4.1 Unsigned binary numbers
Sometime +ve and –ve data is not differentiated. To do this, it calls for use of its magnitude. Consider 8-
bit numbers.

Concentrating on the magnitude, where each number represents the magnitude (weight) of the
corresponding decimal number, the numbers can be added only if there is no overflow i.e. they do not
exceed the limit.

1.4.2 Signed Binary numbers

This involves numbers with +ve and –ve signs e.g. -1, -2, -3, +4. Forgetting the signs, their magnitudes
are 1, 2, 3, 4. In their decimal form we have -001, -010, -011, +101.
Since microprocessors do not understand signs, all input data including signs must be in binary form
where +ve sign is coded 0 and -ve sign is coded 1. The MSB represents the sign of that number e.g.

1.5 2’s Complement Representation

This is a rare but important number system that determines how complex (or easy) an arithmetic circuit
is. 1‘s complement of a number means complementing each bit of that number. E.g. 1110 becomes 0001

A 2‘s complement is obtained by getting the 1‘s complement then adding 1 to the LSB. E.g.

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 Examples
Express the following in 2‘s complement
representation in an 8-bit word -5, -6, -7

 Examples
Work out the following

 Topical questions
 Define a signal in and explain the term digitization as used in electronics
 Differentiate between digital and analogue system
 State three main ways in which signals can be classified in binary form
 Explain the four main digital number systems
 Why are binary numbers very important in digital electronics
 In binary number system, explain the terms; bit, byte and nibble
 How many bits make one byte
 What is the decimal equivalent of the largest binary integer that can be obtained with 1byte?
 Differentiate between Most significant bit and Least significant bit in a binary number
 Differentiate between unsigned and signed binary numbers
 In signed form, what do the binary digits 0 and 1 represent
 Differentiate between 1‘s and 2‘s complement
 Work out: (2EC)16 + (7B)16

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 2. WEEK 3: BINARY LOGIC SYSTEMS
2.1 Binary Logic and Basic Gates
Digital circuits are described as hardware components that manipulate binary information. The circuits
are implemented using transistors and interconnections in complex semiconductor devices called
integrated circuits (ICs). Each basic circuit is known as a logic gate. To simplify circuit designs, the
transistor based-electronic circuits are modeled as logic gates where each gate performs a specific logic
operation. Digital circuits are formed by combining logic gates by applying the outputs of some gates to
the input of other gates. A binary logic system of mathematical notation known as the Boolean algebra is
used to specify the operation of each gate. It is also used in design and analysis of digital circuits.

Logic operations deals with binary variables that take on two discrete values (H-L, T-F, 1-0) and the
operations of mathematical logic applied to these variables? For our purpose the variables are represented
by alphabetical letters e.g. A, B, C, X, Y, Z and can only take the binary values 1 and 0.
There are three basic logical operations associated with binary variables; AND, OR and NOT. For every
operation, there is a corresponding logic gate.

The various combinations of binary variables showing the relationship between the input values of the
variable and the output (results) of the operation are usually listed in a table known as a truth table.

2.1.1 AND operation (AND gate)

This operation is represented by a dot. For example C = A.B. This is read as ``C is equal to A and B``.
The AND logic operation is taken to mean that C = 1 iff A = 1 and B = 1; otherwise C = 0.
Consider the circuit below for the various combinations.

AND gate operation

2.1.2 OR operation (OR gate)

This operation is represented by a plus symbol. For example C = A + B. This is read as ``C is equal to A
OR B``.

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The OR logic operation is taken to mean that C = 1 if A = 1 or if B = 1, or if both A = 1 and B = 1. C = 0
iff A = 0 and B = 0.

OR gate operation

Note that, AND and OR gates may have more than two input. An AND gate with three inputs is known
as a 3-input AND gate. A three input AND gate responds with a logic-1 output if all the three inputs are
logic 1 and the output is logic 0 if any of the inputs is 0.

There are other two gate that relates to the OR gate. These are;
(i) Inclusive-OR gate: This is obtained when the output C is logic-1 i.e. C = 1 and both A = 1 and
B= 1
(ii) Exclusive-OR gate: This is obtained when the output C = 1 and either A = 1 or B = 1 but not
both.

2.1.3 NOT (complement) operation (NOT Gate or inverter)

This operation is represented by a bar over the
variable. For example C = A . This is read as ``C is
equal to NOT A``.

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The NOT logic operation is taken to mean that C is
what A is not. i.e. If A = 1, then C = 0 and if
A = 0, the C = 1.

Note that a double inverter leads to the original logic value

2.2 Universal Gates

NAND & NOR gates are called as universal gates. Because we can implement any Boolean function,
which is in sum of products form by using NAND gat
es alone. Similarly, we can implement any Boolean function, which is in product of sums form by using
NOR gates alone.

2.2.1 NAND gate

This is an AND gate followed by an inverter (NOT gate)
Truth Table

2.2.2 NOR gate

This is an OR gate followed by an inverter (NOT gate)
Truth Table NOR Gate

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 3. WEEK 4-5: BOOLEAN ALGEBRA
3.1 Boolean Algebra Set
This is a set of mathematical algebra dealing with binary variables and logic operations which can be
used to formalize the combinations of binary logic states. For a given value of the binary variable Q, a
Boolean function can be equal to either 1 or 0. For example;
Q  A  BC

The two parts of the expression A and B C , are known as terms of the function Q . The function Q is

equal to 1 if term A is equal to 1 or if term B C (both B and C ) is equal to 1. Otherwise Q is equal to 0.

Here the complement operation dictates that if B =1 then B must be equal to 0.therefore we say that Q =
1 if A = 1, or if B = 0 and Q = 1. A Boolean function then expresses the logical relationship between
binary variables. It is evaluated by determining the binary value of the expression for all possible
combinations of the values of the variables.

A Boolean function can be represented in a truth table. The number of rows in a Truth Table
truth table is 2 n , where n is the number of variables in the function. The binary A B C Q=A+B'C
combinations in a truth table are the n -bit binary numbers that correspond to 0 0 0 0
0 0 1 1
counting in decimal from 0 to 2 n  1 . 0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
XOR Gate 1 1 1 1

From the truth table, there are eight possible combinations. The function Q = 1 if A = 1 and B = 0 and
C = 1. Otherwise the function Q = 0. A Boolean function can be transformed from an algebraic

expression to a circuit diagram composed of logic gates. From the circuit diagram of the function Q , the

inverter on input B generates the complement B . An AND gate operates on B and C and an OR gate
combines A and B C . In a logic circuit diagram, the gates are interconnected b wires that carry logic
signals. Such logic circuits are called combinational logic circuits since the variables are ``combined`` by
logical operations.
By manipulating the Boolean expressions according to the Boolean algebraic rules, it is possible to obtain
a simpler expression for the same function but with reduced number of inputs to the gates and number of
gates for the circuit.

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 3.2 Boolean Identities
The following are the basic identities of Boolean algebra.

10. Commutative

11. Associative

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12. Distributive

13. DeMorgan' s

These laws are important since they determine how bulky or simple the circuit will be. They are hence
used to reduce Boolean expressions in their simplest form.

3.3 The DeMorgan’s Theorem

Identities 13 ( A  B  A  B and A  B  A  B ) from the above table are referred to as the DeMorgan‘s
theorem.

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 3.3.1 First DeMorgan’s theorem
States that: The complement of the sum of variables is equal to the product of their complements.

i.e. A  B  A.B .
For N terms, the general A  B  C  .....  N  A  B  C  ........  N .
This theorem can be verified by means of truth tables e.g.

3.3.2 Second DeMorgan’s theorem

States that: The complement of the product of variables is equal to the sum of their complements.
i.e. A .B  A  B .

For N terms, the general A  B  C.....  N  A  B  C  ........  N .

 Task
Using truth tables, show that A.B  A  B

3.4 Duality principle

The duality principle of Boolean algebra states that a Boolean equation remains valid if we take the dual
of the expression on both sides of the equal sign. This means Changing all AND gates into OR gates and
all OR gates into AND gates and then convert all 1s to 0s and 0s to 1s.

3.5 Simplification Techniques

3.5.1 Algebraic manipulation method
This is useful when simplifying Boolean expressions. The following steps are taken.
 Complement the expression
 Convert operation AND to OR operation
 Convert operation OR to AND operation
 Complement to get the simplified expression

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Examples
Draw the logic circuit hence determine its equivalent circuit for the following Boolean expression using
the Boolean theorems hence draw its circuit.

(a) Y  A B  BC  (b) Y  A  B  A  B  (c) Q  X YZ  X Y Z  XZ


(a) Y  A B  BC 
A
A(B+AC)
B
B
B+AC
C BC

Solution

Y  A B  BC  A A(B+C)
B
Y  AB  BC  C
 A  B  BC 
 A  B.BC  A  B.BC

Y  A  BC  A B  C 

 A B B C  Y  A BC  
 A  B B  BC
i.e. Y is equivalent to using three gates, an inverter, an OR
 A  BC
gate and an AND gate as shown.

(b) Y  A  B  A  B  Y  B
Y  A  B  A  B  Y  B
This is circuit is equivalent to using a single input from B to
Y  A  B  A  B 
Y.
 A  B    A  B 
B Y
 AB  A B
 AB  A B

 B A A  B 

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  Standard Form
A standard form of a Boolean function facilitates simplification procedures. It contains;
Product terms: Logical product consisting of AND operation on the variables e.g. ABC
Sum terms: Logical sum consisting of OR operation on the variables e.g. A  B  C

 Minterms and Maxterms

Minterm is a product term in which all the variables appear exactly once, either complemented or
uncomplemented. The symbol for minterms is m j where j denotes the decimal equivalent for the binary

combination for which the minterm has the value 1. Each minterm is 1 for the corresponding binary
combination and 0 for all other combinations.
Maxterm is a sum term in which all the variables appear exactly once, either complemented or
uncomplemented.
For a n variable function, there are minterms and 2 n maxterms. The symbol for maxterms is M j where

j denotes the decimal equivalent for the binary combination for which the maxterm has the value 0.
Each maxterm is 0 for the corresponding binary combination and 1 for all other combinations.
NB: A maxterm can also be described as an inverted minterm M j  m j

e.g. m3  ABC  A  B  C  M 3

A Boolean function can be expressed algebraically from a A B C Q Q'

given truth table by forming the logical sum of all the 0 0 0 1 0
0 0 1 0 1
minterms that produce a 1 in the function. This expression is
0 1 0 1 0
called a sum of minterm. Consider the Boolean function Q 0 1 1 0 1
1 0 0 0 1
in the table.
1 0 1 1 0
1 1 0 0 1
1 1 1 1 0

The function Q is equal to 1 for each of the following combinations of the variables A , B and C : 000,
010, 101 and 111. These combinations corresponds to the minterms 0, 2, 5 and 7 and can be expressed as
Q  ABC  ABC  ABC  ABC = m0  m2  m5  m7 .This is abbreviated as Q A, B, C    m0,2,5,7 

where the symbol  means logical sum (Boolean OR) of the minterms and the numbers following it
represents the minterms of the function.

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The function Q  ABC  ABC  ABC  ABC is said to be in the standard sum of product form. It is a
simplified sum of minterms will have a reduced number of product terms and number of literals in the
terms.
Q  ABC  ABC  ABC  ABC

   
Q  AC B  B  AC B  B  AC 1  AC 1

Hence Q  AC  AC
The logic diagram of a sum-of-product form consists of a group of AND gates ORed together.
Consider the complement of the Boolean function, Q . Taking the logical sum of minterms of Q gives:

Q  ABC  ABC  ABC  ABC  m1  m3  m4  m6 . This is abbreviated as Q A, B, C    m1,3,4,6 .

NB: The minterm numbers for Q are the ones missing from the list of the minterm numbers of Q .

Since Q is the complement of Q , then;

Q  m1  m3  m4  m6  m1 .m3 .m4 .m6

 M 1 .M 3 .M 4 .M 6

  
 A BC A BC A BC A BC  
This is the product of sum and is abbreviated as Q A, B, C    M 1,3,4,6 where the symbol  denotes
the logical product (Boolean AND) of the maxterms numbers listed.

    
The function Q  A  B  C A  B  C A  B  C A  B  C is said to be in the standard product of sum
form. The logic diagram of a product-of-sum form consists of a group of OR gates ANDed together.

 Properties of minterms
There are 2n minterms for n Boolean variables. These minterms can be evaluated from the binary
numbers from 0 to 2n  1.
Any Boolean function can be expressed as a logical sum of minterms. The complement of a function
contains those minterms not included in the original function. A function that includes all the 2n
minterms is equal to 1.
Note that, a function that is not in the sum-of-minterms can be expressed in that form by use of a truth
table.

An example of a Boolean function expressed in the sum-of-minterm form is F  B  AC .

The truth table for this function is as below.

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 A B C F=B'+A'B' F'
0 0 0 1 0 The minterms are F  A, B, C    m0,1,2,4,5
0 0 1 1 0
0 1 0 1 0 The minterms for the complement are
0 1 1 0 1 F  A, B, C    m3,6,7 
1 0 0 1 0
1 0 1 1 0
1 1 0 0 1
1 1 1 0 1

With the sum-of-products method the design starts with a truth table that summarizes the desired input-
output conditions. The next step is to convert the truth table into an equivalent sum-of-products equation.
The final step is to draw the AND-OR network or its NAND-NAND equivalent.

A SOP equation in which each product (AND) term contains all input variables in either true or
complemented form is said to be in standard, normal or canonical form.
An equation in normal form will have one product term for each entry in the truth table for which the
output is 1.

Example
Draw the truth table for the function F  A, B, C   ABC  AC  AB hence express it in
(a) the standard SOP form
(b) the standard POS form
Solution This is implemented as

A B C ABC A'B' A'C' F

0 0 0 0 1 1 1
0 0 1 0 1 0 1
0 1 0 0 0 1 1
0 1 1 0 0 0 0 F
1 0 0 0 0 0 0
1 0 1 0 0 0 0
1 1 0 0 0 0 0
1 1 1 1 0 0 1 A
B
F  A, B, C   ABC  ABC  ABC  ABC C

(Standard sum of product form)

F  A, B, C    m0,1,2,7  or

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 F  A, B, C    m3,4,5,6 or

F  A, B, C   ABC  ABC  ABC  ABC

In terms of maxterms we get; F  A, B, C    M 3,4,5,6 or
   
F  A, B, C   A  B  C A  B  C A  B  C A  B  C  (Standard product of sums form).

Whereas the SOP equation is a series of A

products (ANDs) connected by addition

(OR), the POS is a series of sums
F
(Ors)connected by multiplication
(AND). This can be implemented as;

Example
Express the function F  AB  A B C  BC in the normal SOP form.

Solution
The first term is missing variable C while the last term is missing variable A. Therefore the equation is
not in normal form. For any given function, there exist only one equation in normal form.
An SOP equation is converted to its normal form by multiplying (ANDing) by 1 to the term with a
missing input variable. This will not change a product term. The function can be rewritten as:
F  AB1  A B C  BC 1
From the laws of Boolean algebra, ORing any variable with its complement always equals 1:

A  A  1
Thus we can rewrite the previous equation as:
 
F  AB C  C  A B C  BC A  A  
This provides the missing input variables for the product terms. Simplifying the equation yields:
F  ABC  ABC  A B C  ABC  ABC
Note that the first and last terms are the same hence one can be eliminated to give the normal form
equation as;
F  ABC  ABC  ABC  ABC

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Example
Simply the following expression in:
(i) Sum of Product.
(ii) Product of Sum.

F  X Z  Y Z  Y Z  XY
F  A C  B D  ABC  ABCD

   
F  A B  D A B C A B  D B C  D 
3.5.2 Karnaugh-Map (K-map) Simplification method
This method provides a clear procedure for simplifying Boolean functions of up to four variables. A K-
map is a diagram made up of squares, with each square representing one minterm of the function. It
therefore shows all possible ways a function may be expressed in standard form hence choose the
simplest expression (one with minimum number of terms and with the fewest number of literals per
term). This produces a two-level implementation having a logic circuit diagram with a minimum number
of gates and minimum number inputs to the gate. An n-variable Boolean function has 2n minterms.

 Two-variable K-Map
A two variable Boolean function has four minterms
hence the map consists of four squares each for one
minterm as shown below.

The variables A appears complemented in row 0 and

uncomplemented in row 1 while the variables B is
complemented in column 0 and uncomplemented in
column 1. A function of two variables can be represented
by marking the squares that correspond to the minterms of
the function as shown below.

AB is equal to minterm m3 hence a 1 is placed in the square corresponding to m3.

This map belongs to a function which is a logical sum of minterms m1 , m 2 and m 3

m1  m2  m3  AB  AB  AB  A  B
i.e.

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The simplified expression A  B is determined from the two-square area for the variable A in the second
row and the two-square area for B in the second column. These two areas enclose the three squares
belonging to A or B .

 Three-variable K-Map
It has 8 minterms hence 8 squares as shown below.
Note the sequence of the binary numbers.

m0 m1 m3 m2
m4 m5 m7 m6

Consider m 5 and m7 . The two lie in two adjacent squares. Variable B is complemented in m 5 and

uncomplemented in m7 , while variables A and C match in both squares. The logical sum of of two such
adjacent minterms can be simplified into a single product sum of two variables as;


m5  m7  ABC  ABC  AC B  B  AC 
Here the two squares differ in the variable B , which can be removed when the logical sum (OR) of the
two minterms is formed. Thus in a 3-variable K-map, any two minterms in adjacent squares that are
ORed together produce a product term of two variable.

Example
Using a K-map, simplify the Boolean function
F ( X , Y , Z )   m2,3,4,5

Solution
This function is;
F ( X , Y , Z )  XY Z  XYZ  X Y Z  X Y Z
First, denote with 1 each minterm that represents the
function as shown.
Next step is to explore collections of squares (called rectangles) on the map representing product terms to
be considered for the simplified expression. Note that the rectangles that correspond to product terms are
restricted to those numbers that are powers of 2. Our aim is to find the minimum number of rectangle that
contains all the minterms marked 1 (see figure above). From the lower rectangle, the product term is
X Y while from the upper rectangle the product term is XY .

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The logical sum of the two product terms gives the simplified expression for F as; F  XY  X Y
F ( X , Y , Z )  XY Z  XYZ  X Y Z  X Y Z  XY  X Y .

Example
F x, y, z   x y z  x yz  x yz  x y z  x y z  xy z The first group reduces to x (this is the only
term the four have in common), and the
second group reduces to z , so the final
minimized function is F x, y, z   x  z Note
that a Kmap with all 1s. Suppose we have the
The leftmost 1s in
following Kmap:
the first column can be grouped with the rightmost 1s
in the last column, because the first and last columns
are logically adjacent. The first and last rows of a
Kmap are also logically adjacent. The correct
groupings are as follows: The largest group of 1s we can find is a group
of eight, which puts all of the 1s in the same
group. To simplify this, we follow the same
rules.

 Four Variable K-Map

Before we move on to four variables, here are the rules/steps for Kmap simplification.
Step 1: Generate K-map. Put a 1 in all specified minterms and put a 0 in all other boxes (optional)
Step 2: Group all adjacent 1s without including any 0s. All groups (aka prime implicants) must be
rectangular and contain a ―power-of-2‖ number of 1s i.e. 1, 2, 4,...The groups must be as large as possible
while still following all rules. An essential group (aka essential prime implicant) contains at least 1
minterm not included in any other groups - A given minterm may be included in multiple groups.
Overlapping groups are allowed and Wrap around is allowed.
Step 3: Define product terms using variables common to all minterms in group. Use the fewest number
of groups possible.
Step 4: Sum all essential groups plus a minimal set of remaining groups to obtain a minimum SOP.
Extending the map simplification techniques to four variables, four variables give us 16 minterms, as
shown below. Notice the special order of 11 followed by 10 applies for the rows as well as the columns.

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Minterms and Kmap Format for Four Variables are as shown below.

Example
Minimize the function

F w, x, y, z   wx y z  wx yz  x yz  wx y z  wxy z  wx y z  w x yz  wx y z
Group 2 represents the ultimate wrap-around group:
It consists of the 1s in the four corners. Remember,
these corners are logically adjacent. The final result is
that F reduces to three terms, one from each group:
x y (from Group 1), x z (from Group 2), and wy z
(from Group 3). The final reduction for F is then
F w, x, y, z   x y  x z  wy z .
We are only concerned with the terms that are Occasionally, there are choices to make when
1s, so we omit entering the 0s into the map. performing map simplification as shown below.
Group 1 is a ―wrap-around‖ group, as we saw A Choice of Groups
previously. Group 3 is easy to find as well.

The first column should clearly be grouped. Also, the w x yz and wxyz terms should be grouped.

However, there is a choice as to how to group the wxy z term. It could be grouped with wxyz or with

wx y z (as a wrap-around). These two solutions are indicated below.

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The first map simplifies to F w, x, y, z   F1  y z  wyz  wxy . The second map simplifies to

F w, x, y, z   F2  y z  wyz  wx z .

The last terms are different. F1 and F2, however, are equivalent. They both have the same number of
terms and variables as well. If we follow the rules, Kmap minimization results in a minimized function
(and thus a minimal circuit), but these minimized functions need not be unique in representation.
Using these rules, let‘s complete one more example for a four-variable function. The example below
shows several applications of the various rules.

Example
Minimize the function

F w, x, y, z   F2  w x y z  w x yz  wx yz  wxyz  wx yz  wxyz  w x yz  w x y z

In this example, there is one group with a single element i.e. w x y z . Note there is no way to group this
term with any others if we follow the rules. The function represented by this Kmap simplifies to
F w, x, y, z   F2  yz  xz  w x y z

If there is a function that is not written as a sum of minterms, one can still use Kmaps to help minimize
the function. However, one has to use a procedure that is somewhat the reverse of what we have been
doing to set up the Kmap before reduction can occur.
Example of a function not represented as a sum of minterms.
Suppose you are given the function F w, x, y, z   wxy  w x yz  w x y z . The last two terms are minterms,

and we can easily place 1s in the appropriate positions in the Kmap. However the term wxy is not a
minterm. Suppose this term were the result of a grouping you had performed on a Kmap. The term that

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was discarded was the z term, which means this term is equivalent to the two terms wxy z  wxyz . You
can now use these two terms in the Kmap, because they are both minterms. We now get the following
Kmap:
So we know the function:
F w, x, y, z   wxy  w x yz  w x y z simplifies to

F w, x, y, z   wy

 Don’t Care Conditions

There are certain situations where a function may not be completely specified, meaning there may be
some inputs that are undefined for the function. For example, consider a function with 4 inputs that act as
bits to count, in binary, from 0 to 10 (decimal). We use the bit combinations 0000, 0001, 0010, 0011,
0100, 0101, 0110, 0111, 1000, 1001, and 1010. However, we do not use the combinations 1011, 1100,
1101, 1110, and 1111. These latter inputs would be invalid, which means if we look at the truth table,
these values wouldn‘t be either 0 or 1. They should not be in the truth table at all.
We can use these don’t care inputs to our advantage when simplifying Kmaps. Because they are input
values that should not matter (and should never occur), we can let them have values of either 0 or 1,
depending on which helps us the most. The basic idea is to set these don‘t care values in such a way that
they either contribute to make a larger group, or they don‘t contribute at all as shown in example below.

Example
Don‘t care values are typically indicated with an ―X‖ in the appropriate cell. The following Kmap shows
how to use these values to help with minimization. We treat the don‘t care values in the first row as 1s to
help form a group of four. The don‘t care values in rows 01 and 11 are treated as 0s.
This reduces to. F1 w, x, y, z   w x  yz There is another way these values can be grouped:

Using the above groupings, we end up with a simplification of F2 w, x, y, z   wz  yz . Notice that in
this case, F1 and F2 are not equal. However, if you create the truth tables for both functions, you should
see that they are not equal only in those values for which we ―don‘t care.‖

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 3.6 Two-level implementation
The implementation of a Boolean function with NAND gates is the simplest if the function is in sum-of
products form. This form corresponds to a two-level circuit. If AND gates and OR gate are used to
implement the circuit, we say that the AND gates are in the first level and the OR gates are in the second
level. For such two level circuit, inverter on the inputs to the AND gate and on the outputs of the OR
gates are not counted as levels.

 Procedure
 Simplify the function and express it in SOP form.
 Draw a NAND gate for each product term of the expression that has at-least two literals. The
inputs to each NAND gate are the literals of the term. This contributes to the first level gates.
 Draw a single gate using the AND-NOT or NOT-OR graphic symbol at the second level, with
inputs coming from outputs of the first level gates.
A term with a single literal requires a NOT at the first level. However, if the single literal is
complemented, it can be connected directly to an input of the second-level NAND gate.

Example
Implement the function Solution
F  ABC    m1,2,3,4,5,7  BC
OO O1 11 1O
i) Using AND gate and OR gate 0 1 1 1
A O AB
ii) Using NAND gates
1 1 1 1 0

AB C F  ABC   AB  AB  C

(i) Using AND-OR gates (ii) Using NAND gates

F  ABC   AB  AB  C   
F  ABC   AB AB C
A A
B B
F A
F
B
C C

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3.7 Conversion from SOP to POS using K-Map
What makes the various SOP expressions different is if they're formed by grouping ones on a map – that
is, if they're prime implicants – or if they're formed by grouping zeros on a map – that is, if they're prime
implicates.
If you group ones on a map, you've obtained an SOP To form the POS expression directly,
expression for the uncomplemented form. group the zeros on a map and reverse
If you group zeros on a map, you've implemented an SOP the standard convention for the
expression for the complemented form. correspondence between zeroes and
CD ones in the labels and complemented
OO O1 11 1O and uncomplemented literals.
OO 1 1 0 1
CD
AB O1 1 1 0 0 OO O1 11 1O
11 1 1 1 0 OO 1 1 0 1
1O 0 0 0 0 AB O1 1 1 0 0
11 1 1 1 0
Simplifying in SOP form, the final expression
1O 0 0 0 0
becomes; F  ABCD  A C  B C  A B D  ABD

Simplifying the above gives

F  ABCD  AB  AC D  BCD
In POS form, the final expression becomes
 
F  ABCD  A  B A  C  D B  C  D  

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 4. WEEK 6-7: DIGITAL MEMORIES
4.1 What is an Electronic Memory?
Recall that, the CPU is made of three components namely, the arithmetic logic unit (ALU), memory
unit, and the control unit. In addition to these, auxiliary storage/secondary storage devices are used to
store data and instructions on a long-term basis. The memory unit together with the secondary storage
is a major component of a digital computer and is in a large proportion for all digital systems. A
memory can be described as a collection of cells capable of storing binary information. In addition to
these cells, memory contains electronic circuits for storing and retrieving information.

Memories hold one or more bits of information in the form of:

(i) Data: This may be either; Integers, Real numbers or Text.
(ii) CPU Instructions: These are computer programs.
(iii) Memory Addresses: These are "Pointers" to data or instructions.

We should note that computers employ many different types of memories (either; semi-conductor
memory, magnetic disks and tapes, CD-ROMs etc.) to hold data and programs. Each type of memory
has its own characteristics and uses.
Memories in computers provide temporary and permanent storage for substantial amount of binary
information. In order to be processed, the information is first sent to the processing hardware consisting
of registers and combinational logic circuits, then back to memory through input/output devices.

4.2 Registers
A register is simply a group of flip-flops. A flip-flop can store one bit information. Therefore, an n-bit
register consists of a group of n flip-flops and is capable of storing any binary information/number
containing n-bits. The contents of a register can either be ―read‖ or ―written‖ very quickly, often in the
order of magnitude faster than the main memory and several orders of magnitude faster than disk
memory.

Different kinds of register are found within the CPU and classified either as general purpose or special
purpose registers.

I. The General Purpose Registers

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These are available for general use by the programmer. Such uses include passing parameters to
functions or storing return values, and intermediate values during computations. Unless otherwise, here
were shall use the term "Register" to refer to a General Purpose Register within the CPU. Most modern
CPU‘s have between 16 and 64 General Purpose Registers.

II. The Special Purpose Registers

As the name suggests have special uses and are either nonprogrammable and internal to the CPU or
accessed with special instructions by the programmer. These registers have particular names and store
state information about the machine/change state configuration. Examples of such registers include:
 Program Counter/Instruction Pointer Register (PC/IP)
 Instruction Register (IR)
 ALU Input & Output Registers
 Condition Code (Status/Flags) Register
 Stack Pointer Register (SP)

 Note that the binary information in a register can be moved from stage to stage within the
register or into or out of the register upon application of clock pulses. This type of bit movement
or shifting is essential for certain arithmetic and logic operations used in microprocessors and
gives rise to group of registers called shift registers (discussed earlier).
 In such registers, the Flip Flops are connected in such a way that, the output of one flip flop
serves as the input of the other flip-flop, depending on the type of shift registers being created.

4.3 Computer Memories

Computer memories are divided into two broad categories:
 Primary/main storage: This is closely connected to the CPU and used for temporary storage of
data and instructions during processing.
 Secondary/ auxiliary storage: This is relatively permanent but further away'' from the CPU.
Comparing the two storage devices we can say that;
 Primary storage is fast; secondary storage is slow (relatively).
 Primary storage is volatile (i.e. contents are lost when power is removed); secondary storage is
non-volatile.
 Primary storage is based on electronic technology; secondary storage is usually based on
magnetic (or optical) and mechanical technologies.

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 4.3.1 Primary Storage Devices
There are two main types of primary storage
 Read only memory (ROM)
 Random Access memory (RAM)

I. ROM (Read Only Memory).

A read only memory (ROM) is a device that includes both a decoder and OR gates within a single IC
package. It consists of n input lines and m output lines. Each bit combination of the input variables is
called an address. Each bit combination that comes out of the output lines is called a word. The number
of distinct addresses possible with n input variables is 2n

A ROM contains programs and/or data ``burned in'' at the time of manufacture. Commonly used to
contain programs to ``boot up'' the computer when it is switched on.Small programs called firmware are
often stored in ROM chips on hardware devices (like a BIOS chip), and they contain instructions the
computer can use in performing some of the most basic operations required to operate hardware devices.
ROM memory cannot be easily or quickly overwritten or modified.

Types of ROMs
The four types of ROM are: Masked ROM, PROM, EPROM, and Flash-PROM.

(i) Mask PROM

Most basic type of ROM is factory-programmed diode matrix as shown in the figure below. The diode
can be replaced by a multiple emitter transistor for each data word. During manufacture, a diode is placed
at those connections which are required by the customer. The complete transistor array is programmed
via fabrication mask. Those connections without diode cannot be changed later and vice-versa. This
memory is read-only. It is also highly economic when several thousand devices are needed.

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(ii) PROM (Programmable Read Only Memory).
 It is a ROM which is ``blank'' and into which programs and/or data can be written. The PROMs are
one time programmable. Once programmed, the information is stored permanent hence the memory
is read-only but only once. i.e. It allows user to store data or programs. This ROM device is
factory-programmed device and one need to tell fab plant which connections to make/skip.
 More useful solution would be to allow customer to program device in the field. This is by placing
a diode at every junction with nichrome fusible link in series.
 Any link can be blown by selecting its address and applying a high voltage to its data output. i.e.
passing around 20 to 50 mA of current for the period 5 to 20μs. The blowing of fuses is called
programming of ROM.

Advantage over ROM

 Device is ‗field-programmable‘: Customer can buy a blank PROM to programme or manufacturer
can made identical PROM for every customer, reducing cost

Disadvantages over ROM

 Need 2 voltages: The operating voltage and the programming voltage

(iii)EPROM (Erasable Programmable Read Only Memory)

An EPROM can be programmed in a similar manner to a PROM. It allows a user to erase the information
stored on the chip and reprogram it with new information. Each diode/fuse is replaced by 2-Gate MOS
transistor. High programming voltage injects electrons into transistor. Process can be reversed by
exposing device to UV light. The UV lightwave reforms conductive channel.
Advantage over ROM/PROM
 Device is field programmable plus the code can be re-written at a later date

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Disadvantages over ROM/PROM
 Still need 2 voltages
 Quartz crystal is expensive.

 UV-EPROM (Ultraviolet Erasable Programmable Read Only Memory) – This is a PROM in which
erasing of stored data is done by exposure the device to UV light through a transparent quartz
window above the chip. EPROMs use MOS circuitry. They store 1‘s and 0‘s as a packet of charge in
a buried layer of the IC chip. It is not possible to erase selective information. The chip can be
reprogrammed.

 EEPROM (Electrically Erasable Programmable Read Only Memory) - EEPROM also use MOS
circuitry. Unlike UV-EPROM, no UV light is required to erase memory. Data is stored as charge or
no charge on an insulated layer or an insulated floating gate that allows voltage to erase in the device.
EEPROM allows selective erasing at the register level rather than erasing all the information since the
information can be changed by using electrical signals. Program/Erase voltage generated on-chip and
a single VDD line is required.

Advantage over ROM/PROM/UV-EPROM

 Can be reprogrammed easier
 Only single power supply needed

Disadvantage over ROM/PROM/ UV-EPROM

 Thin gate insulator layer is damaged by erase/write operations.

(iv) Flash PROM (FLASH)

Flash memory stores information in an array of memory cells made from floating-gate transistors. The
floating gate may be conductive (typically polysilicon in most kinds of flash memory) or non-
conductive.

Flash Advantages
 Flash memory is improvement on EEPROM technology
 Lower operational voltage, program voltage

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 Flash Disadvantages
 As gate insulator is thinned, the number of times it can be written is reduced. Flash might have
1,000,000 write cycles
 Entire block(or page) must be erased at one time in flash,(byte can be erased in EEPROM)

II. RAM (Random Access Memory).

It‘s called ``RAM'' because any location in the memory can be directly accessed in the same amount of
time as any other location. It‘s a memory in which Read and Write operations can be carried out.

Types of RAMs
The two categories of RAMs are SRAM and DRAM

A. SRAM (Static RAM):

A memory circuit is said to be static if the stored data can be retained indefinitely, as long as the power
supply (VDD) is present, without any need for periodic refresh operation while Random Access imply any
location can read at a point in time (Doesn‘t need sequential addresses). This RAM uses flip flops as
storage elements and therefore store data indefinitely as long as dc power is applied. It requires a number
of transistors per bit. It is built using D-latch or 6-transistor CMOS RAM cell. One disadvantage is that it
is difficult to cost-effectively scale for larger memories.

There are two types of SRAMs

i) Asynchronous SRAMs
ii) Synchronous Burst SRAMs

B. DRAM (Dynamic RAMs):

This utilizes MOSFET capacitors as data bit storage elements and cannot retain data very long without
capacitors being recharged by a process called refreshing.

The DRAMs are categorized as:

i) Fast Page Mode DRAM,
ii) Extended Data Out DRAM(EDO DRAM),
iii) Burst EDO DRAM and
iv) Synchronous DRAM.

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 Note that the data flow in a
memory system is usually through
buses. A bus is a set of conductive
paths that interconnect two or
more functional components of a
system or several diverse systems.

 Memory Addressing
 Memory organization
Main computer memory can be considered to be organised as a matrix of bits. Each row represents a
memory location, typically this is equal to the word size of the architecture, although it can be a word
multiple (e.g. 2xWordsize) or a partial word (e.g. half the wordsize). For simplicity we here assume that
data within main memory can only be read or written a single row (memory location) at a time.

The memory is therefore specified as 2k  n where the address lines range from 0 to
2k  1 where k is the number of address line to address 2k words of the memory and n is the
wordsize in bits.

The selection of a specific word inside the

memory is done by applying the k-bit binary
address to the address lines. A decoder
accepts this address and opens the paths
needed to select the word specified.

For a 96-bit memory we could organise the memory as 12x8bits, or 8x12 bits or, 6x16 bits, or even as
96x1 bits or 1x96 bits. Each row also has a natural number called its address which is used for selecting
the row:

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  Byte-addressing
Main-memories generally store and recall rows, which are multi-byte in length (e.g. 16-bit word = 2
bytes, 32-bit word = 4 bytes). Most architecture however, makes the main memory byte-addressable
rather than word addressable. In such architectures the CPU and/or the main memory hardware is capable
of reading/writing any individual byte.
Here is an example of a main
memory with 16-bit memory
locations. Note how the memory
locations (rows) have even
addresses.

Byte Ordering
The content bytes within a multi-byte data item can be numbered either from Left-to-Right (Big-Endian)
or from Right-to-Left (Little-Endian). In the following example, table cells represent bytes, and the cell
numbers indicate the address of that byte in Main Memory.

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 (i) Big-Endian systems - here the most significant byte of a multi-byte data item has the lowest
address, while the least significant byte has the highest address.
(ii) Little-Endian systems - the least significant byte of a multi-byte data item has the lowest
address, while the most significant byte has the highest address.

 Note that, an N-character string value is not treated as one large multi-byte value, but rather as
N single character values, i.e. the first character of the string always has the lowest address
while the last character has the highest address. This is true for both big-endian and little-
endian.

 Example
Show the contents of memory at word address 24 if that word holds the number given by 122E 5F01H in
both the big-endian and the little-endian schemes.

Solution
By convention, we order the bytes within a memory word left-to-right for big-endian and right-to-left
for little-endian.

Word Alignment
Although main-memories are generally organised as byte-addressed rows of words and accessed a row at
a time, some architectures, allow the CPU to access any word-sized bit-group regardless of its byte
address.
We say that:
 accesses that begin on a memory word boundary are aligned accesses while,

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  accesses that do not begin on word boundaries are unaligned accesses.

Reading an unaligned word from RAM requires;

(i) Reading of adjacent words.
(ii) Selecting the required bytes from each word.
(iii)Concatenating those bytes together => SLOW
Writing an unaligned word is even more complex and SLOWER. For this reason some architectures
prohibit unaligned word accesses. e.g. On the 68000 architecture, words must not be accessed starting
from an odd-address (e.g. 1, 3, 5, 7 etc).

RAM Integrated Circuits (Chips)

The physical RAM chips can be organised in a variety of ways. The following 3 methods can be used to
form a 256x8 bit main memory.

(i) In the first case, Main memory is built with a single RAM chip.
(ii) In the second we use two RAM chips, one gives us the most significant 4 bits, the other, the least
significant 4 bits.
(iii)In the third we use 8 RAM chips, each chip gives us 1 bit - to read an 8 bit memory word, we
would have to access all 8 RAM chips simultaneously and concatenate (link) the bits.

Memory Banks
Main memories are normally bigger than the size of a single RAM chip. Therefore to access a memory
word the memory hardware has to read a row in several RAM chips simultaneously and then concatenate
the returned results from each RAM chip.

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The RAM chips that make up a main-memory system, are normally grouped into banks that are one
memory word wide:

Memory size
Computer memories vary greatly in size. The following units of measurement are used
 1 byte: 8 bits  gigabyte (230 ): (1 GB = 1024 MBs)
 kilo (210 ): (1 KB = 1024 bytes)  terabyte (240 ): 1040 (1 TB = 1024
 mega (220 ): (1 MB = 1024 KBs) GBs??

 Example
Given Main Memory = 1M x 16 bit (word addressable), and the available RAM chips/modules is 256K x
4 bit.
a) How many RAM modules make this memory?
b) How many BANKs will be formed?

Solution
The total number of RAM Chips is given by the ratio of the memory size to the chip size
No. of RAM chips = (1M x 16) / (256K x 4)
= 1M x 16 bit = (210K)x(4x4 bits)
= (16x256Kx4bits)/(256Kx4 bits)
= 16 RAM chips

Total No. of RAM chips 16

Total No. of BANKS = = =4
BANK size 4

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Memory Operations
These are the operations on memory data supported by the memory unit. Typically, read and write
operations over some data element (bit, byte, word, etc).

- The Read and Write operation

A write operation involves transfer of a new word to be stored into the memory. A write signal specifies
the transfer-in operation.
On the other hand, a read operation is a transfer of a copy of the stored out of memory hence a read
signal specifies the transfer-out operation. Both operations are high-cost operations, relative to in-
memory operations, so data bus must be carefully planned! Upon accepting one of these control signals,
the internal circuits inside memory provide the desired function.

The following are the Write operation process.

1. Apply the binary address of the desired word to the address lines.
2. Apply the data bits that must be stored in memory to the data input lines.
3. Activate the Write input

The memory unit will take the bits from the data input lines and store them in the word specified by the
address lines. The following steps are taken for the read operation.
1. Apply the binary address of the desired word to the address lines.
2. Activate the Read input
The memory will the take the bits from the words that has been selected by the address and apply the to
the data output lines. The content of the selected word are not changed by reading them. Commercial
memory chips sometimes provide the two control inputs for the read and write operations and may be in
different configurations. Most of the circuits provide at least a chip select that selects the chip to be read
from or written to, and a Read/Write that determines the particular operation to be executed. The
resulting memory operation is as shown below.

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The chip select is used to enable the particular RAM chip (s)
containing the word to be selected. When the chip select is inactive,
the memory chips are not selected, and no operation is performed.
When the chip select is active, the R/W input determines the
operation to be performed. While the Chip Select accesses chips, Chip symbol
another signal called Memory Enable is provided to access the
entire memory. Below is a symbol for a 64Kx8 RAM chip.

Sometimes the read or write enable line is defined as a clock with precise timing information (e.g. Read
Clock, Write Strobe). Otherwise, it is just an interface signal and Sometimes memory must acknowledge
that it has completed the operation.
 Why Not Store Everything in Main Memory?
 Costs too much: Cost of RAM is high compared to cost of the same amount of disk space, so
relatively small size and main memory is volatile.

4.3.2 Secondary Storage Devices

These storage devices are not directly accessible by the CPU. Computer usually uses its input/output
channels to access secondary storage and transfers the desired data using intermediate area in primary
storage.

Three major types of secondary storage devices:

 Hard Disks
 The hard disk drive is the main, and usually largest, data storage device in a computer.
 It can store anywhere from 160 gigabytes to more than 2 terabytes.
 Hard disk speed is the speed at which content can be read and written on a hard disk.
 A hard disk unit comes with a set rotation speed varying from 4500 to 7200 rpm.
 Disk access time is measured in milliseconds.
 Hard disks may be internal or external

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  Tertiary storage
 Typically it involves a robotic mechanism which will mount (insert) and dismount removable mass
storage media into a storage device.
 It is a comprehensive computer storage system that is usually very slow, so it is usually used to
archive data that is not accessed frequently.
 This is primarily useful for extraordinarily large data stores, accessed without human operators.

o Magnetic Tape
 Is a magnetically coated strip of plastic on
which data can be encoded.
 It is oldest, and originally the only, form of
secondary storage.
 Tapes for computers are similar to tapes used to
store music.

 Tape is much less expensive than other storage mediums but commonly a much slower solution that
is commonly used for backup.
 It is still used, mostly for backup or archival storage, and for batch processing.
 Data is stored on tracks on the tape - most tapes have 9 tracks.
 There are several varieties of magnetic tape:
- 14" reels of 1/2" wide tape (2400' long)
- Cartridges of 1/4" tape
- Cassettes (very similar to audio cassettes)
- Digital Audio Tape (DAT).
 Bytes of data (i.e. 8 bits) are stored across the width of the tape.
 The 9th bit is a parity bit that detect storage errors.
 Two types of parity can be used:
 Even parity: Parity bit is set so that the group of 9 bits has an even number of `1' bits.
 Odd parity: Parity bit is set so that the group of 9 bits has an odd number of `1' bits.
 Data is stored at different densities (e.g. 1600 and 6250 bpi, where ``bpi'' means ``bytes per inch'').

Advantages of magnetic tapes Disadvantages of magnetic tapes

 It is very inexpensive  only allows access to data sequentially and is
 It can store large amounts of data therefore relatively very slow in storage

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 It is relatively robust  Manual mounting/dismounting may be needed

o Magnetic Disks
This is the most common form of secondary storage used today. Magnetic disks come in two forms:
 hard disks
 floppy disks
Hard disks are (usually but not always) permanently mounted inside the computer. All magnetic disks
have a magnetizable iron oxide coating and read/write heads that can move over the surface of the
disk, which is spinning underneath it. The disk head works in a similar way to the head in an audio
tape recorder. The read/write head in a floppy disk drive actually contacts the magnetic disk, but that
in a hard disk ``flies'' a few thousandths of an inch above it.

o Magnetic Hard Disks

The figure below shows the structure of a magnetic hard disk. The structure consists of five major
components as;
i) Magnetic platter
ii) Spindle
iii) Read/write head
iv) Head actuator
v) Circuit board (PCB)

 Data on the disk surface is recorded on tracks (magnetic, not physical grooves!) which form
concentric circles on the disk. Each disk has a set number of tracks. Depending on type of disk drive,
there may be from 100 to over 10,000 tracks on the disk. Tracks with the same number on each disk
(recording) surface form a cylinder. The disks spin at a fixed speed, typically at 3600 rpm (IDE) or
7500 -15,000 rpm (SCSI). Tracks on a disk are organized into sectors. To get to a particular piece of
data on the disk a track number and a sector number are needed. Data is read/written when the
required sector on the track rotates into position under the read/write head (note that data can be
accessed from any track of the cylinder). The time taken to position the head over the correct

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 track/cylinder is called the seek time. The time needed for the sector to arrive (once the head is in
position over the correct track/cylinder) is called the latency time. Creating the magnetic tracks on a
previously blank disk is called formatting the disk. Formatting destroys any data that might have been
on the disk previously. Typical data access times for modern hard disks (i.e. latency + seek) are about
10-15 milliseconds
 Typical storage capacities today are:
o Microcomputer: 20 Mb - 240 Gb
o Mainframe: 240 - 800 Gb
 Magnetic hard disks are, in a mainframe environment, often referred to as DASD's - ``Direct Access
Storage Devices''.

o Optical Disc
Is any storage media that holds content in
digital format and is read using a laser
assembly is considered optical media. Optical
disks are becoming more common.
The most common types of optical media are:
Blu-ray (BD), Compact Disc (CD) and Digital
Versatile Disc (DVD).

o Off-line Storage Devices

Also known as disconnected storage or removable storage. It is a computer data storage on a medium or a
device that is not under the control of a processing unit. It must be inserted or connected by a human
operator before a computer can access it again.
Examples are: Floppy Disk, Zip diskette, USB Flash drive and Memory card.

Summary of memory Characteristics

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5. WEEK 8-9: INTERFACING
5.1 Analogue and Digital Signals
 Analog signals are quantities directly measurable in terms of some other quantity
Examples:
 Spring balance – spring extents as more mass is added
 Thermometer – mercury height rises as temperature rises
 Car Speedometer – Needle moves farther clockwise during acceleration
 Stereo – Volume increases as you turn the knob.
 Digital Signals have only two states. 0 and 1 (called binary states in digital computers)- ―1‖ for on,
―0‖ for off.
Examples:
 Light switch can be either on or off
 Door to a room is either open or closed
 Information can be true or false

5.2 Interfacing Process

Interfacing involves is simply a method of connecting or linking two systems for the purpose of adapting
the output and input configurations of the two electronic devices so that they can work together. Here it
involves linking the analogue and digital world.
Interfacing involves both A/D and D/A Conversions

During interfacing, Data is processed Analogue

Digital

Voice x[n] Digital

in one of two ways: analogue or Band ADC
Communication
Limiting
Filter Network
digital. Analogue to digital (ADC)
y[n]
involves sampling to give a discrete Voice Low Pass DAC
Filter
time signal and encoding to give the
Analogue
digital signal. A digital-to-analogue
converter (DAC) converts a digital
signal to analogue. An overall block
diagram for interfacing system is
illustrated below.

pkn@2023 Page 46
The diagram comprises the elements briefly described below:
1. Band Limiting Filter – This is also called the anti-aliasing filter and is required to limit the input
signal bandwidth to less than half the sampling frequency in order to comply with Shannon‘s
Sampling Theorem.
2. ADC – This comprises a sample-and–hold, quantiser and encoder and converts the sampled values to
digital values, x[n].
3. Digital Communications Network - performs operations on the digital signal which might include:
 Code conversion and formatting.
 Signal conditioning.
 Filtering.
 Modulation and demodulation.
 Mixing.
 Equalization.
 Transmission and reception, eg via landline, radio, satellite, optical fibre.
 Storage.
4. DAC –Digital-to-analogue to convert the received digital values, y[n], back to analogue.
5. Low Pass Filter – or recovery Filter – removes unwanted components in the recovered analogue
signal.

5.3 A/D Converters

An analog-to-digital converter (ADC or A/D) is an electronic circuit that converts continuous signals to
discrete digital numbers. Typically; an ADC is an electronic device that converts an input analog voltage
to a digital number/signal by taking samples of its current amplitude during a certain finite period of time
(sampling time). The digital output may be using different coding schemes, such as binary and two's
complement binary. A/D converters are therefore used to transform analog information (analog signals),
from measurements of physical variables (such as; sound, pressure, light, radio waves, temperature,
force, or shaft rotation) and transform it into a voltage that is proportional to the amplitude of that signal.
The operation required to convert the voltage generated by the sensor to its digital equivalent is
performed by the ADC. This might involve any of the following operations:
 processing by a computer or by logic circuits, including arithmetical operations, comparison, sorting,
ordering, and code conversion
 storage until ready for further handling,
 display in numerical or graphical form, and

pkn@2023 Page 47
 transmission

This process can be simplified as a two-stage process. i.e.

• Sampling and Holding
• Quantizing and encoding
This is as illustrated by the following diagram

 Sampling
 The first step (Stage 1 in the diagram) consists of taking an instantaneous ADC input voltage for the
duration of the conversion. This is the sampling part of the process, and it‘s performed by the Sample-
and-Hold (S/H), which is located directly at the input of the ADC. Operation of S/H is similar to that
of a camera i.e. capture the analog signal and hold its value until the ADC can process it.
 Holding signal benefits the accuracy of the A/D conversion
 The minimum sampling rate should be at least twice the highest data frequency of the analog signal.

S/H
M Level n Bit
Input Quantizer Binary
Encoder Output, x[n]
C n
M=2
n bits per sample

Sample Pulses
Sample Rate fS.

 The S/H briefly opens its aperture window to capture the input voltage on the rising edge of the clock
signal, and then closes it to hold its output at the newly acquired level. As shown in the diagram
above, the signal present at the output of the S/H (internal to the ADC and invisible from the outside)
has a staircase-like appearance. The S/H circuit illustrated below. The output level of the S/H is
updated on every rising edge of the ADC‘s clock input.

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The sample pulse closes the switch and samples the input. The sampled values charge up the capacitor,
C. When the switch opens, the capacitor retains ie ‗holds‘ the previous sample value in order to give time
for the quantiser and encoder to carry out their functions.

The sampling process is illustrated below:

Voice

Sample
Pulses tim
e
Discrete-time
value

Sampled
Values

The time to sample the signal should occur in a very short time interval in order to give an accurate,
‗instantaneous‘ value, ie the sample pulses are ideally very narrow. However the ADC requires time to
convert the analogue sample values to a digital value, (called the conversion time). Therefore the sample
values need to be ‗Held‘ in order to give the ADC time to do the conversion.

 Quantization
 The second step (Stage 2 in the diagram) assigns a numerical value to the voltage level present at the
output of the S/H. This process, known as quantization, and searches for the nearest value
corresponding to the amplitude of the S/H signal out of a fixed number of possible values covering its
complete amplitude range.
 The quantizer can‘t search over an infinite number of possibilities and must restrict itself to a limited
set of potential values.
 The size of this set corresponds to the range of the quantizer and is always a power of 2 (or 2 N, such
as 256, 512, 1024, and so on).
 Once the closest discrete value has been identified by the quantizer, it is assigned a numerical value
and encoded as a binary number.
 Since the value is necessarily contained in the complete set of 2N potential values, only N bits are
required to represent all the binary encoded numbers that can be generated by the quantizer.
 For this reason, ADCs are often referred to as N-bit ADCs, where N represents the number of bits
used by the ADC to encode its digitized values. By convention, N-bit is also used to denote

pkn@2023 Page 49
 the resolution of the ADC, since the quantization step (the distance between discrete quantization
levels) is equal to 1/2N.
 By its fundamental nature, the quantization and encoding process cannot be infinitely accurate and
can only provide an approximation of the real values present at the ADC‘s analog input. The higher
the resolution of the quantizer, the closer this approximation will be to the actual value of the signal.
 Nevertheless, the conversion process will always introduce systematic quantization errors, which will
fall within half the quantization step size (smaller than half a negative step if it rounds off to the
nearest value, or smaller than half a positive step if it truncates to the nearest value). Because this
error is normally distributed randomly from one digitized sample to the next, it‘s usually referred to
as quantization noise.
 There are multiple constraints that limit the resolution of an ADC, but most of these constraints are
related to the time required by the quantizer to determine the closest match for the signal at the output
of the S/H. Scanning a larger set of potential values obviously requires more time, so a variety
techniques have been developed (and continue to be developed) to accelerate this process. However
the final selection of one technique over the other is usually the result of a compromise between
resolution, sampling rate, cost, and power consumption.

 The Nyquist-Shannon sampling theorem.

This theorem states that; a continuous bandlimited signal (or function) can be completely defined or
reconstructed from an infinite sequence of samples defining it.

In other words, if we digitize a signal using an ADC with an infinite precision (not limited to N bits), and
we then convert the signal back to an analog format using a DAC, also having an infinite precision, we
will get an exact copy of the original signal. Nothing will have been lost. This process is shown in the

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above figure.Properly regenerating the analog signal requires the use of an output analog reconstruction
filter to smooth out the discrete steps present at the output of the DAC.

Note that, Shannon‘s Sampling Theorem requires that the analogue input signal is sampled at a rate twice
the highest frequency.
To ensure this, the input signal is first bandlimited (using a band limiting filter or anti-aliasing filter
circuit) to B Hz and the sample rate is set to: f s  2B Hz . This in effect means at least two samples per
cycle.
 If f s  2B Hz , aliasing occurs and the sampled values do not properly represent the analogue input.

 If f s  2B Hz , this is described as sampling at the Nyquist Rate.

For example, for audio signals the maximum frequency of interest is usually 20 kHz. In this case the
input analog must be sampled at a little over 40 kHz. Typically, 44 kHz is used.
Note that, if the analog signal does contain frequency components larger than (1/2)fsample, then there will
be an aliasing error. Aliasing is when the digital signal appears to have a different frequency than the
original analog signal.

Example:
 Consider 0-10V signals.
 Separate them into a set of discrete states with 1.25V increments.
 (How did we get 1.25V?)
The number of possible states that the converter can output is: N=2n
where n is the number of bits in the AD converter

For a 3 bit A/D converter, N=23=8. To encode, we assign the digital value
Analog quantization size: (binary number) to each state for the
Q=(Vmax-Vmin)/N = (10V – 0V)/8 = 1.25V computer to read.

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 ADC Parameters
o Step Size or Least Significant Bit (LSB)
This corresponds to the quantization interval and is the smallest step size in volts.
VRe f
Step Size or LSB = volts
2n  1
e.g. for example with VREF = 10 volts and n = 8 bits, the step size is given by
10 10
LSB    40 mV
2 1
8 255  1

o Resolution
Resolution is the LSB normally expressed as a percentage of the full digitisation range.
1
Resolution = n x 100%
2 1
1
E.g. for n = 8 bits, Resolution   100 %  0.4%
255
o Accuracy
Since the input analogue signal is ‗rounded‘ to the nearest quantisation level, the maximum error is half
the step size or ±½ LSB.
For a maximum amplitude input signal, (k=1), the accuracy, normally expressed as a percentage, is:

1 1 
Accuracy = ±  n   100 %
22 

E.g., for a maximum input signal, with n = 8 bits, the accuracy is ± 0.2 %

 Types of ADCs
ADCs fall into 4 general types of technique:
 Flash ADC (Parallel encoding):  Single or dual slope: slow; best
 fast; limited accuracy since needs potential accuracy
many parts (255 comparators for 8-bit  Input signal is averaged
ADC)  Greater noise immunity than other
 Lower resolution ADC types
 Expensive  High accuracy
 Large power consumption  High precision external components
required to achieve accuracy

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  Successive approx. (feedback):  Sigma-delta ADC.
 Capable of high speed  High resolution
 Medium accuracy compared to other  Need no precision external
ADC types components
 Good tradeoff between speed and cost  Slow due to oversampling
 slower at higher resolution
 Speed limited ~5Msps
 We shall describe the flash ADC.

The Flash ADC

It is also called ―parallel A/D‖ and uses a series of comparators as shown below.

 Consists of 2n-1 series of comparators, each one comparing the input signal to a unique
reference voltage through one of the 2n resistors.
 The comparator outputs connect to the inputs of a priority encoder circuit, which
produces a binary output

 Note: Flash ADC is the fastest of all ADC and require no clock. If propagation delay time is
zero, then the ideal conversion time is zero. And the practical conversion time is the sum of all
propagation delay of combinational circuit involved in flash type ADC

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How Flash ADC work
Each comparator compares Vin to a different reference voltage (Vref), starting with
1
Vref  LSB
2
Comparator is one use of an Op-Amp.
In its operation,
 If VIN> VREF, VOUT is High
If VIN< VREF, VOUT is Low

Flash converters have a resistive ladder that divides the reference voltage (VREF) into 2N equal parts. For
each part, a comparator compares the input signal (VIN) with the voltage supplied by that part of the
resistive ladder. The output of all the comparators is like a thermometer: the higher the input value, more
comparators have their outputs high from bottom to top. A "Priority Encoder" translates this gauge into a
binary code, which corresponds to the position of the last comparator with high output, counting from the
bottom up.

The Priority Encoder has to find the position of the last comparator with high output, starting from the
bottom. That means it should find the position where neighboring comparators have different outputs (all
below have output high and all above have output low). That can be simply done by XORing the outputs
of neighboring comparators and feeding their outputs to a digital encoder. Only one XOR has its output
active and the encoder will translate that position into a binary representation. If there are
2N comparators, the encoder outputs a N-bit number (resolution of the ADC).

 The OP-AMP
 A circuit is said to be linear, if there exists a linear relationship between its input and the output.
 If there exists a non-linear input/output relationship, the circuit is said to be non-linear.

 Op-amps can be used in both linear and non-linear applications.

 Some applications of op-amp include:

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  Inverting Amplifier
 Non-inverting Amplifier
 Voltage follower

 An inverting amplifier takes the input through its inverting terminal through a resistor R1, and
produces its amplified version as the output.
 Such amplifier not only amplifies the input but also inverts it (changes its sign)

 Op-Amp as an Inverting Amplifier

Note that for an op-amp, the voltage (potential) at the inverting input terminal is equal to the voltage at
its non-inverting input terminal.
• Physically, there is no short between those two terminals but virtually, they are in short with each
other.
• In the circuit shown above, the non-inverting input terminal is connected to ground. That means
zero volts is applied at the non-inverting input terminal of the op-amp.
• According to the virtual short concept, the voltage at the inverting input terminal of an op-amp
will be zero volts.

 The ratio of the output voltage V0 and the input

voltage Vi is the voltage-gain or gain of the
amplifier.
 Therefore, the gain of inverting amplifier is equal
to −Rf /R1.
 Note that the gain of the inverting amplifier is
having a negative sign. It indicates that there exists
a 1800 phase difference between the input and the
output.

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  Sammary of ADC comparison

ADC Resolution Comparison

Dual Slope
Flash
Successive Approx
Sigma-Delta

0 5 10 15 20 25
Resolution (Bits)

5.4 D/A Converters

A digital to analog converter (DAC) converts a digital signal to an analog voltage or current output.

In DACs switches, resistors, and op-amps are used to implement the conversion. Each binary number
sampled by the DAC corresponds to a different output level.

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DACs capture and hold a number, convert it to a physical signal, and hold that value for a given sample
interval. This is known as a zero-order hold and results in a piecewise constant output.

In general,
Analog input  K  Digital Output
where K is the proportionality factor, is constant value for a given DAC.
The analog output can be a voltage or current. If it is a voltage, K is given in voltage units, and when
the output is current, K is in given current units.
For a DAC of K  1 V , so that Vout  (1 V ) × digital input.

To calculate Vout for any value of digital input. For example, with a digital input of 11002  1210 , we

obtain Vout  1 V  12  12 V
Remember, the proportionality factor, K, will vary from one DAC to another.
Two main types are: Binary Weighted Resistor DAC and R-2R Ladder.

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 Binary Weighted Resistor DAC
 Utilizes a summing op-amp circuit
 Weighted resistors are used to distinguish each bit from the most significant to the least
significant
 Transistors are used to switch between Vref and ground (bit high or low)

Inverting summer circuit used in

Binary Weighted Resistor DAC.
V(out) is 180° ot of phase from V(in)

 Advantages and Disadvantages

Advantage Disadvantages
 Easy  Requirement of several different precise input resistor
principle/construction values: Requires large range of resistors (2048:1 for 12-
 Fast conversion bit DAC) with necessary high precision for low resistors
one unique value per binary input bit. (High bit DACs)
 Larger resistors ~ more error.
 Precise large resistors – expensive.

 The R-2R Ladder

This consists of resistor network and an Opamp as shown below.

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  Each bit corresponds to a switch:
 If the bit is high, the corresponding switch is connected to the inverting input of the op-amp.
 If the bit is low, the corresponding switch is connected to ground

 Conversion Equation

 1 1 1 1
Vout  Vref  b3  b 2  b1  b 0 
 2 4 8 16 
For general n-Bit R-2R Ladder or Binary Weighted Resister DAC
n

1
Vout   Vref b n i
i 1 2i
Example
 Convert 0001 to analog given that the reference voltage is Vref =10V
 1 1 1 1
Vout  Vref  b3  b2  b1  b0 
 2 4 8 16 

 1 1 1 1
Vout  10 0.  0.  0.  1.   0.0625V
 2 4 8 16 
Advantages Disadvantage
 Easily scalable to any desired number of bits  Lower conversion speed
 Only two resistor values (R and 2R) which make for than binary weighted
easy and accurate fabrication and integration DAC
 Does not require high precision resistors

Specifications of DACs
• Resolution
• Speed
• Linearity
• Settling Time
• Reference Voltages
• Errors

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  Resolution
Smallest analog increment corresponding to 1 Vref
Resolution  VLSB 
LSB change 2N
where N  number of bits
 An N-bit resolution can resolve 2N distinct
analog levels
Common DAC has a 8-16 bit resolution

Although resolution can be expressed as the amount of voltage or current per step, it is also
useful to express it as a percentage of the full-scale output.

Example Solution
A DAC has a maximum full-scale output of 15
V (when the digital input is 1111). What is its
percentage resolution for a step size of 1V.

 Speed
Rate of conversion of a single digital input to its analog equivalent
 Conversion rate depends on
 clock speed of input signal
 settling time of converter
 When the input changes rapidly, the DAC conversion speed must be high.

 Linearity
 The difference between the desired
analog output and the actual output over
Analog Output Signal

the full range of expected values.

 Ideally, a DAC should produce a linear
relationship between the digital input
0000 0001 0010 0011 0100 0101
and analog output. Digital Input Signal

 Settling time
The operating speed of a DAC is usually specified by giving its settling time. This is the time required for
the DAC output to go from zero to full scale as the binary input is changed from all 0‘s to all 1‘s. also

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defined as the time required for the output signal to settle within +/- ½ LSB of its final value after a given
change in input scale. Typical values for settling time range from 50 ns to 10 µs.

 Reference voltages
 Used to determine how each digital input will be assigned to each voltage division

 DAC Errorss:
 Gain error
 Also called Full-Scale Error
 Occurs when the slope of the actual
output deviates from the ideal output. i.e.
when the actual signal has both gain and
offset error Deviation from the ideal full
scale voltage due to a higher or lower
gain than expected.

 Offset error
 Occurs when there is a constant offset
between the actual output and the ideal
output

 Resolution error
 Poor representation of ideal output due to poor resolution

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 Size of voltage divisions affect the resolution

 Non-linearity error
Occurs when analog output of signal is non-linear.Two types are:
 The Differential – analog step-sizes changes with increasing digital input (measure of largest
deviation; between successive bits. It is the worst case deviation from the ideal V LSB step for an
increment of LSB.
 The Integral – amount of deviation from a straight line after offset and gain errors removed; on
concurrent bits. It is the worst case deviation from the line between the endpoint (zero and full
scale) voltages

 Non-monotonic error
 Occurs when an increase in digital input
results in a decrease in the analog output.
 A DAC is monotonic if its output
increases as the binary input is
incremented from one value to the next.
The staircase output will have no downward steps as the binary input is incremented from
zero to full scale.

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  Settling Time and Overshoot Error
 Settling Time – time required for the output to fall with in +/- ½ VLSB
 Overshoot – occurs when analog output overshoots the ideal output.

Some applications of DACs

DACs are used whenever the output of a digital circuit has to provide an analog voltage or current to
drive an analog device. Some of the most common applications are described in the following
paragraphs.
I. Control: The digital output from a computer can be converted to an analog control signal to
adjust the speed of a motor or the temperature of a furnace, to control a physical variable.
II. Automatic Testing: Computers can be programmed to generate the analog signals (through a
DAC) needed to test analog circuitry. The test circuit‘s analog output response will normally be
converted to a digital value by an ADC and fed into the computer to be stored, displayed, and
sometimes analyzed.
III. Signal Reconstruction: An analog signal is digitized in many applications, meaning that
successive points on the signal are converted to their digital equivalent and stored in memory.
This conversion is performed by an ADC. A DAC can then be used to convert the stored digitized
data back to analog-one point at a time-thereby reconstructing the original signal. This
combination of digitizing and reconstruction is used in digital storage oscilloscopes, audio
compact disk systems, and digital audio and video recording.

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 6. WEEK 10-12: INTEGRATED CIRCUITS
6.1 Combinational Logic Circuits
Combinational Logic Circuits are memoryless digital logic circuits whose output at any time depends
only on the combination of its current inputs state. This means that combinational logic circuits have no
feedback, and any change in the signals applied at the inputs will immediately effect the output. For a
combinational circuit, a binary code of n-bits (inputs) can represent m=2n distinct combinations (outputs
or unique cases).

Basically, combinational circuit can be depicted by diagram below:

Combinational Logic Circuits are designed and built from the basic logic gates (NAND, NOR or NOT
gate) by ―combining‖ or connecting them together to produce more complicated switching circuits. An
example of a combinational circuit is a decoder, which converts the binary code data present at its input
into a number of different output lines, one at a time producing an equivalent decimal code at its output.
These circuits can be very simple or very complicated and any combinational circuit can be implemented
with only NAND and NOR gates as these are classed as ―universal‖ gates.

The three main ways of specifying the function of a combinational logic circuit are:
1. Boolean Algebra – This forms the algebraic expression showing the operation of the logic
circuit for each input variable either True or False that results in a logic ―1‖ output.
2. Truth Table – A truth table defines the function of a logic gate by providing a concise list that
shows all the output states in tabular form for each possible combination of input variable that the
gate could encounter.
3. Logic Diagram – This is a graphical representation of a logic circuit that shows the wiring and
connections of each individual logic gate, represented by a specific graphical symbol, that
implements the logic circuit.
All these three logic circuit representations are shown below.

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As combinational logic circuits are made up from individual logic gates only, they can also be
considered as ―decision making circuits‖ and combinational logic is about combining logic gates together
to process two or more signals in order to produce at least one output signal according to the logical
function of each logic gate. Common combinational circuits made up from individual logic gates that
carry out a desired application include Multiplexers, De-multiplexers, Encoders, Decoders, Full and Half
Adders etc.

Generally, combinational circuits can be classified as follows:

One of the most common uses of combinational logic is in Multiplexer and De-multiplexer type circuits
where multiple inputs or outputs are connected to a common signal line and logic gates to decode an
address to select a single data input or output switch.
Let us first understand how these devices use these ―solid state switches‖ in their design.

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 6.1.1 Arithmetic circuits
These are the fundamental combinational circuits used in arithmetic units of digital computers e.g. XOR,
Half Adders (H.A) and Full Adders (F.A)

 Adders
 Half Adder
This circuit adds two binary numbers giving the sum and a possibility of a carry. It has two inputs and
two outputs. One output implements the sum while the other implements the carry. It add bits in the same
column e.g.

Truth table Logic circuit

A B Carry Sum A
Carry
0 0 0 0 B

1 0 0 1
0 1 0 1 Sum
1 1 1 0

 Full Adder
This circuit adds three bits at a time giving the sum and a possibility of a carry. It has three inputs and
two outputs. A combination of two half adder gives a full adder e.g.

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 Truth Table Logic Circuit
A B C

A B C Carry Sum
0 0 0 0 0
0 0 1 0 1
Carry
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0 Sum

1 1 1 1 1

Adding here can be done in serial version (i.e. bit by bit) or parallel (i.e. bits added simultaneously)

 Parallel operation of a full adder (F.A)

The adder is used in adding multi-digit binary numbers e.g.
C₃ C₂ C₁
A₃ S₂ A₁ A₀
B₃ B₂ B₁ B₀
C₀ S₃ S₂ S₁ S₀

B1 A1 B0 A0
B2 A2
B1 A1

H.A H.A H.A

H.A
C11 C1
C21 C2
C11
H.A
H.A
H.A

C22 C12
C12 S1 S0
S2
C0 S1

 Subtractors
A subtractor is used to subtract one number from another. Because we are dealing with binary digits, the
1s complement and 2s complement of the numbers are used to achieve this. Three bits are involved in
performing the basic subtraction: the minuend (X), the subtrahend (Y) and the borrow (Bi), which is input
from the previous bit. The outputs are the difference (D) and the borrow bit (Bout).

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  Half Subtractor
When a subtraction is done between just two bits a half subtractor is used, similar to the half adder. The
half subtractor's combinational circuit is represented in this image as well as the half subtractor table:

X Y D = (X-Y) Bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
This gives the following Boolean functions and circuit
implementation.
 D = X'Y + XY'
 Bout = X'Y

 Full Subtractor
The circuit full subtractor performs a subtraction operation on three bits, the minuend, the subtrahend,
and the borrow-in bits. The circuit generates two outputs comprising of the calculated difference, D and
the borrow-out.

D = X'Y'Bin + X'YBin' + XY'Bin' + XYBin

Bout = X'Y'Bin + X'YBin' + X'YBin +
XYBin

 These circuits can be implemented using decoders as shown in the following example.

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 6.1.2 Code Converters
We have discussed various codes in the chapter named codes. The converters, which convert one code
to other code are called as code converters. These code converters basically consist of Logic gates
mostly XOR gates

 Binary code to Gray code converter

Gray code is a reflected non-weighted binary code. Note:
The binary number 1101 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 = 8 + 4 + 0 + 1 = 13 So, binary code is a
weighted code but gray code is non-weighted.
Gray codes possess unit distance property since any two successive numbers differ by one bit only.

To convert binary to gray code,

 check the MSB (=1) and write it down.
 perform and XOR operation to each successful bits starting from the MSB of the binary number to
obtain the other code bits.

Let us implement a converter, which converts a 4-bit binary code WXYZ into its equivalent Gray code
ABCD.

The following table shows the Truth table of a 4-bit binary code to Gray code converter.
From Truth table, we can write the Boolean functions for
each output bit of Gray code as below.
A=∑m(8,9,10,11,12,13,14,15)
B=∑m(4,5,6,7,8,9,10,11)
C=∑m(2,3,4,5,10,11,12,13)
D=∑m(1,2,5,6,9,10,13,14)
Let us simplify the above functions using 4 variable K-
Maps.

The following figure shows the 4 variable K-Map for simplifying Boolean function, A.

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 There are two groups of 4 adjacent ones. After grouping, we
By grouping 8 adjacent ones, we
will get B as
got A=WA=W.
B=W′X+WX′=W⊕XB=W′X+WX′=W⊕X
The following figure shows the 4
Similarly, we will get the following Boolean functions for C
variable K-Map for
& D after simplifying.
simplifying Boolean function, B.
C=X′Y+XY′=X⊕YC=X′Y+XY′=X⊕Y
D=Y′Z+YZ′=Y⊕ZD=Y′Z+YZ′=Y⊕Z

The following figure shows the circuit diagram of 4-bit binary code to Gray code converter.

Since the outputs depend only on the present

inputs, this 4-bit Binary code to Gray code
converter is a combinational circuit. Similarly,
you can implement other code converters.

 Parity Bit Generator

There are two types of parity bit generators based on the type of parity bit being generated. Even parity
generator generates an even parity bit. Similarly, odd parity generator generates an odd parity bit.

 Even Parity Generator

Now, let us implement an even parity generator for a 3-bit binary input, WXY. It generates an even
parity bit, P. If odd number of ones present in the input, then even parity bit, P should be ‗1‘ so that the
resultant word contains even number of ones. For other combinations of input, even parity bit, P should
be ‗0‘.

The following table shows the Truth table of even parity generator.

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 From the Truth table, we can write the Boolean function for even
parity bit as
P=W′X′Y+W′XY′+WX′Y′+WXYP=W′X′Y+W′XY′+WX′Y′+WXY
⇒P=W′(X′Y+XY′)+W(X′Y′+XY)⇒P=W′(X′Y+XY′)+W(X′Y′+XY)
⇒P=W′(X⊕Y)+W(X⊕Y)′=W⊕X⊕Y⇒P=W′(X⊕Y)+W(X⊕Y)′
=W⊕X⊕Y

The following figure shows the circuit diagram of even parity generator.

This circuit consists of two Exclusive-OR gates having two inputs each. First ExclusiveOR gate having
two inputs W & X and produces an output W ⊕ X. This output is given as one input of second
Exclusive-OR gate. The other input of this second Exclusive-OR gate is Y and produces an output of W
⊕ X ⊕ Y.

 Odd Parity Generator

If even number of ones present in the input, then odd parity bit, P should be ‗1‘ so that the resultant
word contains odd number of ones. For other combinations of input, odd parity bit, P should be ‗0‘.
Follow the same procedure of even parity generator for implementing odd parity generator. The circuit
diagram of odd parity generator is shown in the following figure.

The above circuit diagram consists of XOR gate in first level and XNOR gate in second level. Since the
odd parity is just opposite to even parity, we can place an inverter at the output of even parity generator.
In that case, the first and second levels contain an XOR gate in each level and third level consist of an
inverter.

 Parity Checker
There are two types of parity checkers based on the type of parity has to be checked. Even parity
checker checks error in the transmitted data, which contains message bits along with even parity.

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Similarly, odd parity checker checks error in the transmitted data, which contains message bits along
with odd parity.

 Decoders
A decoder is a combinational circuit that converts binary information from the n binary lines into 2 n (or
less) unique output lines. E.g. a 3-to-8 line decoder has 3 inputs decoded to 8 output or minterms.
The truth table for a 3-to-8 line decoder is as shown
3-to-8
below Decoder 0
1
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 A0 20
0 0 0 0 0 0 0 0 0 0 1
2
3
0 0 1 0 0 0 0 0 0 1 0 A1 21
0 1 0 0 0 0 0 0 1 0 0 4
0 1 1 0 0 0 0 1 0 0 0 5
A2 22
1 0 0 0 0 0 1 0 0 0 0 6
1 0 1 0 0 1 0 0 0 0 0 7
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

D0 = A2 A1 A0
For each possible input, there are
seven possible outputs equal to 0
D1 = A2 A1 A0
and only one output equal to 1.
A0
D2 = A2 A1 A0
The output variable equal to 1
A1 D3 = A2 A1 A0 represent the minterm equivalent
to the binary number that is
D4 = A2 A1 A0
A2
applied to the input lines.
D5 = A2 A1 A0
Decoders can also be constructed
D6 = A2 A1 A0 using NAND gates instead of

D7 = A2 A1 A0
AND gates. This reduces the cost
and delay of NOT gates.
Most decoders are constructed with an extra one or more Enable inputs to control the operation of the
circuit and cascading. The figure below shows a 2-to-4 line decoder with an enable input.

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Logic Diagram

Decoder are used to implement any combinational

cicuits ( fn ), For example the truth table for full
Truth Table
adder is S (x,y,z) = ∑ m( 1,2,4,7) and C(x,y,z)= ∑m
(3,5,6,7). This can be implemented with decoder as
shown above.

 Task:
Read on BCD TO Seven-segment decoder

 Encoders
An encoder is a digital circuit that performs the inverse operation of a decoder. It has 2n input lines and n
output lines. In encoder the output lines generate the binary code corresponding to the input value.

Generally encoders produce 2-bit, 3-bit or 4-bit code. An n-bit encoder has 2n input lines.

If one of the four input lines is active encoder produces the binary code corresponding to that line.
If more than one of the input lines will be activated or all the output is undefined, we solve the problem
by using priority encoder.
A priority encoder is an encoder circuit that includes priority function. It means if two or more inputs are
equal to 1 at the same time, the input having higher subscript number, is considered as a higher priority.

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  Multiplexer (Mux)
This is a combinational circuit that switch/selects binary information from one of the several input lines
and directs it to a single common output line by application of a control signal.
Usually there are 2n input lines and n select lines (S) whose bit combinations determine which input line
is selected. For example for 2-to-1 multiplexer if selection S is zero then I0 has the path to output and if S
is one I1 has the path to output.

I0
2n:1
n
:1
I1
inputs Y output
I2

n
IIn-1
2 -1

strobe o G

S0 S S2 S
1 n-1

select lines

A strobe is G is provided to allow for cascading. The strobe is active low hence performs its intended
function when it is low.

In order to use a multiplexer, either a truth table or

one of the standard form of logic expression must
be available.

The following design procedure is used;

 Identify the decimal number corresponding to each minterm in the expression.
 The input line corresponds to these numbers are to be connected to logic 1.
 All other input lines are connected to logic 0 (zero).
 The inputs are to be applied to select input lines.

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Example
Implement the expression To use the 8:1 Mux, we have design as shown below:
F ( A, B, C , D)   m(0,2,3,6,8,9,12,14) A B C D F
0 0 0 0 1
Using; (a) 16:1 multiplexer and (b)8:1 0 0 0 1 0 F=D' 0
0 0 1 0 1
multiplexer. 0 0 1 1 1 F=1 1
0 1 0 0 0
0 1 0 1 0 F=0 2
0 1 1 0 1
Solution 0 1 1 1 0 F=D' 3
1 0 0 0 1
Since there are 4-variables, a multiplexer with 4 1 0 0 1 1 F=1 4
1 0 1 0 0
select lines are required, hence a 16:1 mux is 1 0 1 1 0 F=0 5
1 1 0 0 1
appropriate for the circuit. 1 1 0 1 0 F=D' 6
1 1 1 0 1
1 0 1 1 1 1 0 F=D' 7
0 1 D’
0
1
2 0
3 1
4
2
3 8:1
5 16:1 4
6 5 MUX F
7 MUX 6
F
8 7
9
G S S S
10 2 1 0
11
12
13 A B C
14
15
G S S S S
3 2 1 0

A B C D

6.2 Technology and Characteristics of ICs

6.2.1 What is an Integrated Circuit?
Digital circuits are constructed with ICs. An integrated circuit (IC) is just a packaged electronic circuit. A
more detailed, an IC is a complete electronic circuit in which both the active and passive components are
fabricated on a tiny single chip of silicon.
Active components are those which have the ability to produce gain. Examples are: transistors and FETs.
Passive components or devices are those which do not have the said ability. Examples are: resistors,
capacitors and inductors. ICs are produced by the same processes as are used for manufacturing
individual transistors and diodes etc. Each IC has a number indicated on its surface for identification, and
has a pin out diagram and information provided by the manufacturer.

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 6.2.2 Classification of ICs by structure
Structurally speaking, ICs can be classified into the following three types.
1. Monolithic Integrated Circuits: The word ‗monolithic‘ means ‗single stone‘ or more appropriately
‗a single-solid structure‘. In this IC, all circuit components (both active and passive) are fabricated
inseparably within a single continuous piece of silicon crystalline material called wafer (or substrate).
All components are atomically part of the same chip. Transistors, diodes and other passive
components are fabricated at appropriate spots in the substrate using epitaxial diffusion technique.

Component interconnections are provided on the surface of the structure and external connecting wires
are taken out to the terminals. It is a complete circuit requiring no ‗add ons‘. Despite some of its distinct
disadvantages, monolithic ICs are in wide use because for mass production, monolithic process has been
found to be the most economical.

2. Thick and Thin-Film ICs. These ICs are not formed within a silicon wafer but on the surface of an
insulating substrate such as glass or a ceramic material. Moreover, only passive components
(resistors, capacitors) are formed through thick or thin-film techniques on the insulating surface. The
active elements (transistors, diodes) are added externally as discrete elements to complete a functional
circuit. These discrete active components are frequently produced by using the monolithic process.
The essential difference between thick-film and thin-film ICs is not their relative thickness but the
method of depositing (forming) passive components and the metallic conduction pattern. i.e. vacuum
deposition, cathode sputtering or silk-screen printing techniques.
3. Hybrid or Multichip ICs. As the name implies, such circuits are formed either by inter-connecting a
number of individual chips or by a combination of film and monolithic IC techniques. In such ICs,
active components are first formed within a silicon wafer (using monolithic technique) which is
subsequently covered with an insulating layer such as SiO2. Film techniques are then employed to
form passive components on the SiO2 surface. Connections are made from the film to the monolithic
structure through ‗windows‘ cut in the SiO2 layer.

6.2.3 Advantages of ICs

As compared to standard printed circuits which use discrete components, ICs have the following
advantages:

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 1. Extremely small physical size. Often the size is thousands of times smaller than a discrete circuit.
The various components and their interconnections are distinguishable only under a powerful
microscope.
2. Very small weight. Since many circuit functions can be packed into a small space, complex
electronic equipment can be employed in many applications where weight and space are critical,
such as in aircraft or space-vehicles.
3. Reduced cost. It is a major advantage of ICs. The reduction in cost per unit is due to the fact that
many identical circuits can be built simultaneously on a single wafer—this process is called batch
fabrication. Although the processing steps for the wafer are complex and expensive, the large
number of resulting integrated circuits make the ultimate cost of each IC fairly low.
4. Extremely high reliability. It is perhaps the most important advantage of an IC and is due to many
factors. Most significant factor is the absence of soldered connections. Another is the need for
fewer interconnections—the major cause of circuit failures. Small temperature rise due to low
power consumptions of ICs also improves their reliability. In fact, an IC logic gate has been found
to be 100,000 times more reliable than a vacuum tube logic gate and 100 times more reliable than a
transistor logic gate. Obviously, higher reliability means that ICs will work for longer periods
without giving any trouble—something most desirable from both military and consumer application
point of view.
5. Increased response time and speed. Since various components of an IC are located close to each
other in or on a silicon wafer, the time delay of signals is reduced. Moreover, because of the short
distances, the chance of stray electrical pickup (called parasitic capacitance) is practically nil.
Hence it makes them very suitable for small signal operation and high frequency operation. As a
result, the response time or the operating speed of the system is improved.
6. Low power consumption. Because of their small size, ICs are more suitable for low power operation
than bulky discrete circuits.
7. Easy replacement. ICs are hardly ever repaired because in case of failure, it is more economical to
replace them than to repair them.
8. Higher yield. The yield is the percentage of usable devices. Because of the batch fabrication, the
yield is very high. Faulty devices usually occur because of some defect in the silicon wafer or in
the fabrication steps. Defects in silicon wafer can occur because of lattice imperfection and strains
introduced in crystal growth, cutting and handling of the wafers. Usually such defects are
extremely small, but their presence can ruin devices built on or around. Reducing the size of each
device greatly increases the chance for a given device to be free of such defects. The same is true
for fabrication defects such as the presence of a dust particle on the photolithographic mask.

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 6.2.4 Drawbacks of ICs
The integrated circuits suffer from the following drawbacks:
1. coils or inductors cannot be fabricated,
2. ICs function at fairly low voltages,
3. they handle only limited amount of power,
4. they are quite delicate and cannot withstand rough handling or excessive heat. However, the
advantages of ICs far outweigh their disadvantages or drawbacks.

6.2.5 Levels of integrated circuits

Due to the technology improvement, the number of gates per chip has increased for a few to thousands or
millions. Each IC pack is hence classified as either a small-, medium-, or very-scale integrated device.
Small Scale Integration or (SSI) - In this case, the number of circuits contained in one IC package is less
than 12 (or number of components is less than 50). Contain up to 10 transistors or a few gates within a
single package such as AND, OR, NOT gates. The inputs and outputs to the gates are connected directly
to the pins in the package.
Medium Scale Integration or (MSI) - number of circuits per package is between 13 and 99 (or number of
components is between 50 and 5000). Has between 10 and 100 transistors or tens of gates within a single
package and perform digital operations such as adders, decoders, counters, flip-flops and multiplexers.
Large Scale Integration or (LSI) - In this case, circuit density is between 100 and 9,999 (or component
density is between 5000 and 100,000). Has between 100 and 1,000 transistors or hundreds of gates and
perform specific digital operations such as I/O chips, memory, arithmetic, logic units, and small μP.
Very-Large Scale Integration or (VLSI) - Here the number of circuits per package is between 10,000 to
99,999 (or number of components is between 100,000 – 1,000,000). i.e has between 1,000 and 10,000
transistors or thousands of gates to perform computational operations such as processors, large memory
arrays and programmable logic devices.
Super-Large Scale Integration or (SLSI) - between 10,000 and 100,000 transistors within a single
package and perform computational operations such as microprocessor chips, micro-controllers, basic
PICs and calculators.
Ultra large scale integration (ULSI). In this case, the circuit density is between 100,000 to 999,999 (or
component density is between 1,000,000 – 10,000,000).
Giga scale integration (GSI). Here the number of circuits per package is 1,000,000 or more (or number
of components are over 100,000,000).
Other levels include System-on-Chip or (SOC)

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 6.2.6 Integrated circuit families
Most digital systems are designed by combining various logic functions earlier. All these logic circuits
are available in IC modules and are divided into many ‗families‘. Each family is classified by
abbreviations which indicate the type of logic circuit used. Each family has its own basic electronic
circuit upon which more complex circuits and operations can be developed. The following are the most
important families.
1. Resistance-transistor logic (RTL): it was the first family group of logic circuits to be developed and
packaged in IC form in early 1960s;
2. Diode-transistor logic (DLT) : It followed RTL in late 1960s;
3. Transistor-transistor logic (TTL) OR (T2L): was introduced in the early 1970 s;
4. Schottky TTL: was introduced to improve the speed of TTL;
5. Emitter-coupled logic (ECL) : It is fastest logic line currently available;
6. Integrated-injection logic (I2L): It is one of the latest of the bipolar types of logic;
7. Complementary metal-oxide semiconductor (CMOS): It has the lowest power dissipation of the
currently-available logic circuits.
8. Bipolar complementary metal oxide semiconductor (BiCMOS)
9. Gallium-Arsenide (GaAS)

 The TTL "74" Sub-families

The TTL bipolar transistor technology forms the basis of the prefixed "74" family of digital logic IC's,
such as the 7400 (Quad 2-input AND gate) or the 7402 (Quad 2-input OR gate). Sub-families of the 74xx
series IC's are available relating to the different technologies used to fabricate the gates and they are
denoted by the letters in between the 74 designation and the device number. There are a number of TTL
sub-families available that provide a wide range of switching speeds and power consumption such as the
74L00 or 74ALS00 AND gate, were the "L" stands for "Low-power TTL" and the "ALS" stands for
"Advanced Low-power Schottky TTL" and these are as listed below.
1. 74L00 series—the letter L standing for low power consumption. It has an average power
dissipation of 1 mW per gate but an average propagation delay of 33 ns.
2. 74H00 series—the letter H standing for higher speed. It has a propagation delay of 6 ns but
averge power dissipation of 23 mW/gate.
3. 74S00—the letter S representing Schottky. It has the highest speed because its
averagepropagation delay is just 3 ns per gate. However, its average power dissipation is 23
mW/gate.

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 4. 74LS00—It is called low-power Schottky TTL. It has an average propagation delay of 9.5 ns and
an average power dissipationof 2 mW.
5. 74AS00 series—The letter A representing Advanced and S stnading for schottky. It is called
advanced schottky TTL series. It is the fastest TTL series.
6. 74ALS00 series—It is called Advanced Low-power Schottky TTL series. The 74ALS series has
the lower speed-power product and the lowest gate power dissipation of all the TTL series.
7. 74F00 series —The letter F standing for fast. This logic family uses a new IC fabrication
technique to reduce inter-device capacitances to achieve reduced propagation delays. It has a
propagation delay of 3 ns and a power consumption of 6 mW.

6.2.7 IC Operational properties

The following are the most important operational properties to consider when characterizing digital logic
families;

1. DC Supply Voltage: The standard value of the dc supply voltage for TTL (i.e., transistor-
transistor logic) and CMOS (i.e., complementary metal-oxide semiconductor) device is + 5V. For
simplicity, the dc supply voltage is usually omitted from the logic circuits. But in practice, it is
connected to the VCC or VDD pin of an IC package and the ground is connected to the GND pin of
an IC package. Both the voltage and ground are distributed internally to all the logic gates with
the package

2. Loading and Fan-out: When the output of any logic gate is connected to one or more inputs of
other logic gates, a load on the driving gate is created. In any logic family, there is a limit to the
number of load gate inputs that a given logic gate can drive without impairing its performance
(normal operation). This limit is called the fan-out of the logic gate. Loading (Fan-in): Is the
number of inputs connected to the gate without any degradation in the voltage level.

3. Noise immunity: The noise immunity of a logic circuit refers to the circuit‘s ability to tolerate
noise without causing a false change in its output voltage. The noise voltage is produced by stray
electric and magnetic fields on the connecting wires between logic circuits. Sometimes, too much
noise voltage cause the voltage at the input of the logic circuit to drop below VIH (min) or rise
above VIL (max). This could produce unpredictable operation in a logic circuit.

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 4. Noise- margin: A quantitative measure of a circuit‘s noise immunity. Is the maximum noise
voltage added to an input signal of a digital circuit that does not cause an undesirable change in
the circuit output. It is expressed in volts.

5. Power dissipation: Is a measure of power consumed by the gate when fully driven by all its
inputs (power supply). All logic gates draw current from the dc supply voltage for its normal
operation. When the logic gate is in the HIGH output state, it draws an amount of current, ICCH,
and when in LOW output state, it draws an amount of current ICCL. The power dissipation of a
logic gate is given by the product of the dc supply votage (VCC) and the amount of current drawn
from the suppy (i.e., ICCH or ICCL). Thus power dissipation is given by: PD = (VCC) ICCH or PD =
(VCC) ICCL depending on whether the gate is in H or L output state. For TTL PD = 10mW.

6. Propagation delay time: When a signal passes (i.e., propagates) through a logic circuit, it always
experiences a finite time delay i.e. the change in output level occurs after a short time, (called the
propagation delay time), later than the change in input level that caused it. It is the average
transition delay time for the signal to propagate from input to output when the signals change in
value either from H to L or from L to H. It is expressed in ns. For a TTL, Pdt = 10ns. The
propagation delay time of a logic gate limits its maximum operating frequency.

7. Compatibility: TTL circuits are said to be compatible since the output of one can be used as an
input to another. The TTL circuit used as an input to another TTL is known as the driver while
the circuit getting the input is the load.

TTL TTL
Driver Load

8. Operating temperature: Is the temperature in which the performance of the IC is effective. All
gates or semiconductor devices are temperature sensitive in nature. Operating temperature of the
IC vary from 00C to 700C.
 NB: The advantages of TTL circuits are that they are fast, inexpensive and easy to use.

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 Task:
1. Explain the following operation propertuies of transistor logic families; DC supply voltage, Noise
immunity, Power dissipation, Propagation delay, Loading and fan-out, compatibility.
2. Describe the three main structural classes of integrated circuits
3. Explain advantages of integrated circuits over the standard printed circuits which use discrete
component.

Example
Simplify the following function hence implement them using NAND gates and show their circuit layout
(using 74xx ICs). F  A, B, C , D   BC D  AB D  AC D  ABCD

Solution NAND gates implementation

K-Map minimization F  B D  ABC

F  F  B D  ABC

  
CD
AB 00 01 11 10  B D ABC
00 1 1
01
11 1 1 BD B
U1
10 1 1 D
U3 F
A
ABC
B U2
F ( A, B, C , D)  B D  ABC C
Circuit Design

`
7. WEEK 13-15: REVISION AND EXAMS

SUCCESS

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