LAB MANUAL FOR

DIGITAL COMPUTER FUNDAMENTALS LAB- 3137

SEMESTER:3
COMPUTER ENGINEERING
 Program : Diploma in Computer Engineering / Computer Hardware Engineering

Course Code : 3137 Course Title: Digital Computer Fundamentals Lab

Semester : 3 Credits: 1.5

Course Category: Program Core

Periods per week: 3 (L:0 T:0 P:3) Periods per semester: 45

Course Objectives:

● Understand digital systems and data representation.

● Understand digital ICs and their operations.
● Design simple combinational and sequential circuits.
Course Prerequisites:

Course
Topic Course name Semester
code
Basic Knowledge of resistors, diodes, Fundamentals of Electrical and 2
transistors etc Electronics

Course Outcomes :On completion of the course student will be able to:

Duration Cognitive
COn Description (Hours) Level
CO1 Construct gates using universal gates. 7 Applying
Minimize and Implement combinational logic
CO2 functions. 7 Applying

CO3 Develop combinational logic circuits. 11 Applying

CO4 Develop Sequential logic circuits. 17 Applying

Lab Exam 3

CO – PO Mapping:

Course PO 1 PO 2 PO 3 PO 4 PO 5 PO 6 PO 7
Outcome
s
CO1 3
 CO2 3
CO3 3
CO4 3 3 3 3

3-Strongly mapped, 2-Moderately mapped, 1-Weakly mapped

Course Outline

Duration Cognitive
Name of Experiment
(Hours) Level
CO1 Construct gates using universal gates
Show the logic behavior of gates by using gate 4
M1.01 Understanding
ICs
M1.02 Construct gates using Universal Gates 3 Applying

CO2 Minimize and Implement combinational logic functions.

Make use of Boolean algebra and the Karnaugh
M2.01 Map method for the implementation of logic Applying
4
functions in SOP.
Make use of Boolean algebra and the Karnaugh
M2.02 Map method for the implementation of logic 3 Applying
functions in POS.
Lab Exam - I 1½
CO3 Develop combinational logic circuits.
Construct half adder, full adder circuits by using
M3.01 3 Applying
basic, XOR gates and NAND gates
Construct the Combinational Circuit that
M3.02 generates parity bit to follow even parity from 3 Applying
four message bits
Design and implement a combinational circuit
M3.03 3 Applying
that converts a 4-bit Gray code to binary
Interpret the pin-out of parallel adder IC and
M3.04 Develop a four-bit binary Adder-Subtractor using 2 Applying
the IC
CO4 Develop Sequential logic circuits.
Construct Latches and Flip flops using logic gate
M4.01 4 Applying
ICs and infer their working
Demonstrate the pin-outs and functions of JK
M4.02 2 Understanding
and D Flip flop ICs
Construct a 4 bit ripple counter using JK FF IC
M4.03 2 Applying
and infer the working
 Construct synchronous counters like 3 bit binary
M4.04 counter, decimal counter etc using JK FF ICs and 3 Applying
infer the working
M4.05 Open Ended Experiments - ** 6 Applying
Lab Exam II 1½

** - Suggested Open Ended Experiments

(Not for End Semester Examination but compulsory to be included in Continuous Internal
Evaluation. Students can do open ended experiments as a group of 2-3. There is no duplication in
experiments between groups. Open ended experiments should include Combinational and/or
Sequential logic)

1. Develop a circuit that converts a 4 bit binary number to display its hexadecimal
equivalent in a 7 segment display

2. Develop a 4 bit synchronous counter that counts a given sequence in a seven segment
display

Text / Reference:

T/R Book Title/Author

T1 M. Morris Mano & Michael D. Ciltti, Digital Design, Pearson Education, 5th
Edition
R2 A. Anand Kumar, Fundamentals of digital circuits, PHI Learning Pvt. Ltd.,
2003
R3 Malvino & Leach, Digital Principles and Applications, McGraw-Hill

Online Resources:

Sl.No Website Link

1 http://www.asic-world.com/digital/tutorial.html
2 https://www.geeksforgeeks.org/digital-electronics-logic-design-tutorials/
3 https://www.digitalelectronicsdeeds.com/
4 https://en.wikipedia.org/wiki/Digital_electronics

5 https://www.iitg.ac.in/cseweb/vlab/Digital-System-Lab/experiments.php
DATE:
EXP NO:1 FAMILIARISATION OF LOGIC GATES

AIM
Familiarization of logic gates and to verify the truth table for different Ices.

COMPONENTS AND EQUIPMENTS REQUIRED

Digital trainer kit, digital IC tester,IC 7400,7402,7404,7408,7432,7486 and connection wires.

THEORY

The logic functions frequently involved in the design of digital systems are AND, OR, NAND, NOR,
NOT and EX-OR. NOT circuit performs a logical invertion. The AND gate performs a logical
multiplication. The OR gate perform logical addition. The NAND gate is a contraction of NOT-AND
and implies a NAND function with a complimented output. The NOR gate is a contraction of NOT-OR
and implies a NOR function with a complimented output. The EX-OR gate is widely used logic
function for special arithmetic operations. In this if any one of the input is high output also high.

PROCEDURE

 Check the IC using a digital IC tester.

 Place the IC on the kit and switch on the kit.
 Check the output by applying different combination of input.
 Repeat the procedure for all the given ICs.
OR GATE (7432) SYMBOL TRUTH TABLE

AND GATE (7408) SYMBOL TRUTH TABLE

NOT GATE (7404) SYMBOL TRUTH TABLE

 NAND GATE (7400) SYMBOL TRUTH TABLE

NOR GATE (7402) SYMBOL TRUTH TABLE

EX-OR GATE (7486) SYMBOL TRUTH TABLE

RESULT
Familiarized the logic gates and verified the truth table for different ICs.
DATE:
EXP NO: 2 REALISATION OF GATES USING NOR GATE & NAND GATE

AIM
To verify the universal property of NOR gate and NAND gate.

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7402, IC 7400, digital trainer kit and connecting wires.

THEORY
The NOR gate and NAND gate are called universal gates because using this gates we can implement all the
basic gates.

USING NOR
NOT using NOR: NOR gate can be transferred as NOT gate by shorting inputs.
AND using NOR: For making a AND gate from NOR gate, we have to use three NOR gates .Short input of
two gates and then connect the output of this to the input of third gate. Then output of third gate gives the
AND gate
NAND using NOR: For making a NAND gate from NOR gate, the output of AND using NOR is then give to a
NOT gate which created by shorting inputs.
OR using NOR: NOR gate is basically a combination of NOT and OR gate. So OR gate can be made from NOR
gate by adding another NOT gate at the output of NOR gate.

USING NAND
NOT using NAND: NAND gate can be converted to NOT gate by shorting the inputs.
AND using NAND: NAND gate is basically a combination of NOT and AND gates. SO a NAND gate can be
converted into AND gate by adding a NOT gate at the output of NAND gate.
OR using NAND: For making OR gate from NAND, we have to use three gates. Short the inputs of two
gates and connect its output to the input of the third gate. Then output of third gate gives the OR gate
NOR using NAND: For making a NOR gate from NAND, gate, the output of OR using NAND is then give
to a NOT gate which created by shorting inputs.

PROCEDURE
 Test all IC using IC tester.
 Make the circuit on trainer kit.
 Observe the output in each condition of input.
GATES USING NOR GATE

GATES USING NAND GATE

NOT GATE AND GATE

1 1 4
3 3 6
2 2 5

7400 7400 7400

OR GATE
1 NOR GATE
3 1
2 3
13 2
7400 11 1 10
12 7400 3 8
2 9
10 7400 U2:A
8 1 7400 7400
9 3
2
7400
7400

TRUTH TABLES

RESULT
Verified the universal property of NOR gate and AND gate.
DATE:
EXP NO: 3 IMPLEMENTATION OF LOGIC FUNCTIONS IN SOP & POS USING K-MAP
REDUCTION METHOD

AIM
To Study the Simplification of Boolean Functions SOP & POS forms (Demonstrates the relationship
between a Boolean Function and the corresponding logic diagram – using K-map reduction method).

Plot the following Boolean function in a Karnaugh map as well as implement in alogic diagram
F= A’D + BD +B’C + AB’D

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7408, IC 7404, IC 7432,digital trainer kit and connecting wires.
748,7404,7432

THEORY

• Convert the given function in Standard SOP Form., Enter into K-Map and reduce it.
• Convert the given function in Standard POS Form., Enter into K-Map and reduce it.
• Verify that (a) and (b) is equal.

Convert the given function in to Standard SOP Form

F= A’D + BD +B’C + AB’D
Since it is in SOP convert to Standard SOP
• Add the variable B for the missing terms
A’D=A’D(B+B’)=A’DB+A’DB’
• Add the variable A for the missing terms
BD=BD(A’+A)=A’BD+ABD
B’C=B’C(A’+A)=A’B’C+AB’C
• Add the variable C for the missing terms
A’DB=A’DB(C’+C)=A’DBC’+A’DBC
A’DB’=ADB’(C’+C)=ADB’C’+ADB’C
A’BD=A’BD(C’+C)=A’BDC’+A’BDC
ABD=ABD(C’+C)=ABDC’+ABDC
 AB’D=AB’D(C’+C)= AB’DC’+ AB’DC
• Add the variable D for the missing terms
A’B’C=A’B’C(D’+D)= A’B’CD’+ A’B’CD
AB’C=AB’C(D’+D)= AB’CD’+AB’CD
• Combine the above four variable terms all together
F=A’BC’D+A’BCD+A’B’C’D+A’B’CD+A’BC’D+A’BCD+ABC’D
+ABCD+AB’C’D+AB’CD+A’B’CD’+ A’B’CD +AB’CD’ +AB’CD

F= m(1,2,3,5,7,9,10,11,13,15)
f=M(0,4,6,8,12,14)
Enter into K-map and minimize

SOP F min= D+B’C POS F max=(C+D)(B’+D)

Truth table for Sop F min=D+B’C

C B D B’C D+B’C
0 0 0 0 0
0 0 1 0 1
0 1 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 1
1 1 0 0 0
1 1 1 0 1

POS F max=(C+D)(B’+D)

C B D C+D B’+D (C+D)(B’+D)

0 0 0 0 1 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 1 1 1
1 1 0 1 0 0
1 1 1 1 1 1
The above Truth table shows both are equal but in SOP minimized equation needs 3 gates
and POS minimized equation needs 4 gates; so here SOP minimized equation is more economical.
PROCEDURE

• Connections are made as per the circuit diagram

• Switch on the power supply
• Apply different combinations of inputs and observe the outputs; comparethe outputs with
the truth tables

RESULT
Studied the Simplification of Boolean Functions SOP & POSforms using K-map reduction method)
DATE:
EXP NO: 4 HALF ADDER AND FULL ADDER

AIM
To design, construct, and test a half-adder & a full-adder.

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7486, IC 7408, IC 7400 and IC 7432, digital trainer kit and connecting wires.

THEORY

Half adder: circuit needs two binary inputs and two binary outputs. The input variables designate the
augend and addend bits; the output variables produce the sum and carry. We assign symbols x and y to
the two inputs and S (for sum) and C (for carry) to the outputs. The truth table for the half adder is
listed in Table
Full adder : A full adder is a combinational circuit that forms the arithmetic sumof three bits. It
consists of three inputs and two outputs. Two of the input variables, denoted by x and y, represent
the two significant bits to be added. The third input,Cin (for Carry in) represents the carry from the
previous lower significant position.
HALF ADDER USING NAND GATE
FULL ADDER USING NAND GATE

PROCEDURE

• Connections are made as per the circuit diagram

• Switch on the power supply
• Apply different combinations of inputs and observe the outputs.
• Compare the outputs with the truth tables

RESULT
Realised the half adder and full adder.
DATE:
EXP NO: 5 PARITY BIT GENERATORS

AIM
To design, construct, and test circuit that generates parity bit from four message bits.

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7486, digital trainer kit and connecting wires.

THEORY
A parity bit is an extra bit included with a binary message to make the number of 1’s either
odd or even. The message, including the parity bit, istransmitted and then checked at the receiving
end for errors. An error is detected if the checked parity does not correspond with the one
transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator.

Circuit diagram and truth table

 A B C D P
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

PROCEDURE

• Connections are made as per the circuit diagram

• Switch on the power supply
• Apply different combinations of inputs and observe the outputs.
• CompareThe outputs with the truth tables

RESULT
Realized the circuit that generates parity bit from four message bits.
DATE:
EXP NO: 6 CODE CONVERSIONS

AIM
To design and set up a binary to gray code and gray to binary code convertor.

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7486, trainer kit and connecting wires.

THEORY
To convert a gray into corresponding binary, the following rules are applied

 The MSB of binary is the same as the corresponding digit in gray code . I.e. G3=B3
 By exor the G3 & G2, we will get B2.
 By exor the B2 & G1, we will get B1.
 By exor the B1 & G0, we will get B0.

PROCEDURE

 Test all ICs using IC tester.

 Found all the input bit combinations and note down corresponding output.
 Setup grey to binary code converter and found all input combinations and note down corresponding
grey codes.
 GRAY-BINARY
1
3
2

7486

1
RAY 3
2 BINARY
7486

1
3
2

7486

RESULT:
Designed and set up grey to binary converter and verified the truth table.
DATE:
EXP NO: 7 PARALLEL ADDER, FOUR- BIT BINARY ADDER- SUBTRACTOR

AIM

To study the implementation of parallel adder, Adder- Subtractor using IC 7483.

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7404, IC 7408, IC 7483, trainer kit and connecting wires.

THEORY

Parallel adder : IC type 7483 is a four‐bit binary parallel adder. The pin assignment is shown in Fig..
The 2 four‐bit input binary numbers are A1 through A4 and B1 through B4 . The four‐bit sum is
obtained from S1 through S4, C0 is theinput carry and C4 the output carry.
Adder–Subtractor: Two binary numbers can be subtracted by taking the 2’s complement of the
subtrahend and adding it to the minuend. The 2’s complement can be obtained by taking the 1’s
complement and adding 1. To perform A - B, we complement the four bits of B, add them to the
four bits of A, and add 1 through the input carry.

The combinational circuit can be implemented with the 7404 and 7408 ICs. Construct the
comparator circuit and test its operation. Use at least two setsof numbers for A and B to check
each of the outputs x, y, and z.

Parallel adder
 Adder - subtractor

PROCEDURE

 Test all ICs using IC tester.

 Found all the input bit combinations and note down corresponding output.
 Setup parallel adder using IC 7483 and note down corresponding outputs.
 Setup adder-subtractor using using same IC and note down corresponding outputs.

RESULT
Studied the implementation of parallel adder, Adder- Subtractor using IC 7483.
DATE:
EXP NO: 8 LATCHES AND FLIP FLOPS

AIM

To study the Construction and the working of SR Latch, D Latch, Master-Slave Flip-Flop, Edge-
Triggered Flip-Flop, IC Flip-Flops.

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7476, IC 7474, IC 7400, IC 7402, I9C 7404, trainer kit and connecting wires.

SR Latch,: The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled
NAND gates, and two inputs labeled S for set and R for reset. The SR latch constructed with two
cross-coupled NOR gates is shown in Fig. . The latch has two useful states. When output Q = 1
and Q_ = 0, the latch is said to be in the set state . When Q = 0 and Q_ = 1, it is in the reset state .
Outputs Q and Q_ are normally the complement of each other. However, when both inputs are
equal to 1 at the same time, a condition in which both outputs are equal to 0 (rather than be
mutually complementary) occurs. If both inputs are then switched to 0 simultaneously, the device
will enter an unpredictable or undefined state or a metastable state.

D Latch : This latch has only two inputs: D (data) and En (enable). The D input goes directly to
the S input, and its complement is applied to the R input. As long as the enable input is at 0, the
cross-coupled SR latch has bothinputs at the 1 level and the circuit cannot change state regardless
of the value of D . The D input is sampled when En = 1. If D = 1, the Q output goes to 1, placing
the circuit in the set state. If D = 0, output Q goes to 0, placing the circuit in the reset state. The D
latch receives that designation from its ability to hold data in its internal storage.

Master-Slave Flip-Flop,: Observe that the master changes when the pulsegoes positive and the
slave follows the change when the pulse goes negative.

Edge-Triggered Flip-Flop: The construction of a D flip-flop with two D latches and an inverter
is shown in Fig. The first latch is called the master and the second the slave. The circuit
samples the D input and changes its output Q only at the negative edge of the synchronizing or
controlling clock (designated as Clk ). When the clock is 0, the output of the inverter is 1. The
slave latch is enabled, and its output Q is equal to the master output Y . The master latch is
disabled because Clk = 0. When the input pulse changes tothe logic-1 level, the data from the
external D input are transferred to the master. The slave, however, is disabled as long as the clock
remains at the 1 level, because its enable input is equal to 0. Any change in the input changesthe
master output at Y, but cannot affect the slave output. When the clock pulse returns to 0, the
master is disabled and is isolated from the D input. At the same time, the slave is enabled and the
value of Y is transferred to the output of the flip-flop at Q . Thus, a change in the output of the
flip-flop can be triggered only by and during the transition of the clock from 1 to 0. C

Flip-Flops(using IC 7476, and 7474): IC type 7476 consists of two JK master–slave flip‐flops
with preset and clear. The pin assignment for each flip‐flop is shown in Fig IC type 7474 consists
of two Dpositive‐edge‐triggered flip‐flops with preset and clear. The pin assignmentis shown in
Fig.
 SR LATCH

D- LATCH
EDGE TRIGGERED FLIP FLOP

PROCEDURE
• Connections are made as per the circuit diagram
• Switch on the power supply
• Apply different combinations of inputs and observe the outputs;
• Compare the outputs with the truth tables.
RESULT

Studied the Construction and the working of SR Latch, D Latch, Master-Slave Flip-Flop, Edge-
Triggered Flip-Flop, IC Flip-Flops.
DATE:
EXP NO: 9
4 -BIT ASYNCHRONOUS UP COUNTER & DOWN COUNTER (RIPPLE COUNTER)

AIM
To set up 4 bit asynchronous up counter and down counter(ripple counter)and verify their truth
table using IC 7476.

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7476(2 Nos) ,trainer kit and connecting wires.

THEORY
A counter is a circuit that produces a set off unique output combinations in relation to the
number of applied inputs pulses. The number of unique outputs of a counter is known as its
modulus or mod number.
In asynchronous counters, the flip flops are not given the clock simultaneously. Therefore the
propagation delay increases with the number of flip flops used. Four JK FFs must be used in
toggle mode tocount 16 states.
4 bit binary up counter (Ripple counter): In the circuit, all FFs are clocked by the Q output of
the preceding FF. JK inputs of all the FFs are connected to a high state. 7476 is a dual JK Master
Slave FF with preset and clear. A ripple counter comprising of n FFs can be used to count up to
2n pulses. A circuit with four FFs gives a maximum count of 2n =16. The counter gives a natural
binary count from 0 to 15 and resets to initial condition on 16th input pulse.
With the application of first clock pulse Q0 changes from 0 to 1. Q1,Q2 and Q3 remains
unaffected. With second clock pulse, Q0 becomes 0 and Q1 becomes 1. At the arrival of 15th
clock pulse all Q outputs will become 1. At the 16th clock pulse all Q outputs will reset and the
cycle repeats.
4 bit binary down counter (Ripple counter): In this circuit, the succeeding FFs are clocked by
the Q bar output of preceding FFs. The outputs are taken from Q outputs. Initially all Q outputs
are set. At the arrival of 16th clock pulse all Q outputs become reset and cycle continues.

PROCEDURE

 Collect the required components and check it.

 Connections are to be made as per the diagram.
 Give the input conditions to the circuit.
 Verified the outputs.
 -7476 pin diagram-
4 bit binary up
counter

TRUTH TABLES
UP COUNTER DOWN COUNTER
4 bit binary down counter

RESULT
Constructed the 4 bit asynchronous up counter and down counter(ripple counter) and verified the
truth table.
DATE:
EXP NO: 10
RING COUNTER AND JOHNSON COUNTER (SYNCHRONOUSCOUNTER)

AIM
To set up Ring counter and Johnson counter (synchronous counter)and verify their truth table
using IC 7476.

COMPONENTS AND EQUIPMENTS REQUIRED

IC 7476(2 Nos) ,trainer kit and connecting wires.

THEORY
Ring counter and Johnson counter are basically shift registers. A register is simply a group of
FFs that can be used to store a binary number. A shift register is nothing but a register which
accepts a binary number and shifts it. The data can be entered to the shift register either in serial
or parallel. Similarly, the output can be taken from it either serial or in parallel.
Ring counter:
It is made by connecting Q&Q’ output of one JK FF to J&K input of next FF respectively. The
output of final FF is connected to the input of first FF. To start the counter the first FF is set by
using preset facility and the remaining FF are reset input. When the clock arrives the set
condition continues to shift around the ring.
As it can be seen from the truth table there are four unique output stages for this counter.
The modulus value of a ring counter is n, where n is the number of flip flops. Ring counter is
called divided by N counter where N is the number of FF
Johnson counter (Twisted ring counter)
The modulus value of a ring counter can be doubled by making a small change in the ring
counter circuit. The Q’ and Q of the last FFS are connected to the J and K input of the first FF
respectively. This is the Johnson counter
Initially the FFs are reset. After first clock pulse FF0 is set and the remaining FFs are reset.
After the eight clock pulse all the FFS are reset. There are eight different conditions creating a
mode 8 Johnson counter. Johnson counter is called a twisted ring counter or divide by 2N
counter.

PROCEDURE
1. Set up the ring counter and set clear Q outputs using PRESET and apply mono pulse.
2. Note down the state of the ring counter on the truth table for successive clock 0.

3. Repeat the steps for Johnsons counter

Ring counter
Johnson counter (Twisted ring counter)

RESULT
4-bit ring counter and the Johnson counter(synchronous counter) were set up using the JK FFand
verified the truth table.
EXP NO:11

4-BIT SYNCHRONOUS COUNTER INTERFACED WITH 7 SEGMENTED

DISPLAY

AIM:
To set up 4 bit asynchronous up counter and down counter and verifytheir truth table using IC
7476.

COMPONENTS AND EQUIPMENTS REQUIRED:

IC 7476(2 Nos) ,trainer kit and connecting wires.

THEORY:
Synchronous Counters are so called because the clock input of all theindividual flip-flops
within the counter are all clocked together at the same time by the same clock signal

Unlike asynchronous counters whose output of one stage is connected directly to the clock input
of the next counter stage in the chain. The synchronous counter has its stages all clocked together
at the same time.

The problem with Asynchronous counters is that they suffer from what is known as
“Propagation Delay” in which the timing signal is delayed a fraction through each flip-flop.

However, with the Synchronous Counter, the external clock signal is connected to the clock
input of EVERY individual flip-flop within the counter so that all of the flip-flops are clocked
together simultaneously (in parallel) at the same time giving a fixed time relationship. In other
words, changes in the output occur in “synchronisation” with the clock signal.

The result of this synchronisation is that all the individual output bits changing state at exactly
the same time in response to the common clock signal with no ripple effect and therefore, no
propagation delay.
 PIN DIAGRAM OF 7476

Binary 4-bit Synchronous Up Counter

It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to
each of the JK flip flops in the counter chain and that both the J and K inputs are all tied together
in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH,
logic “1” allowing the flip-flop to toggle on every clock pulse. Then the synchronous counter
follows a predetermined sequence of states in response to the common clock signal, advancing
one state for eachpulse.

The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop
FFA, but the J and K inputs of flip- flops FFC and FFD are driven from separate AND
gates which are also supplied with signals from the input and output of the previous stage. These
additional AND gates generate the required logic for the JK inputsof the next stage.
If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs
(Q) are “HIGH” we can obtain the same counting sequence as with the asynchronous circuit but
without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same
time.

Then as there is no inherent propagation delay in synchronous counters, because all the counter
stages are triggered in parallel at the same time, the maximum operating frequency of this type of
frequency counter is much higher than that for a similar asynchronous counter circuit.

4-bit Synchronous Counter Waveform Timing Diagram

Because this 4-bit synchronous counter counts sequentially on every clock pulse the
resulting outputs count upwards from 0 ( 0000 ) to 15( 1111 ). Therefore, this type of counter
is also known as a 4-bit Synchronous Up Counter.

However, we can easily construct a 4-bit Synchronous Down Counter by connecting the
AND gates to the Q output of the flip-flops as shown to produce a waveform timing diagram the
reverse of the above. Here the counter starts with all of its outputs HIGH ( 1111 ) and
it counts down on the application of each clock pulse to zero, ( 0000 )before repeating again.

TRUTH TABLES

UP COUNTER DOWN COUNTER

Binary 4-bit Synchronous Down Counter

As synchronous counters are formed by connecting flip-flops together and any number of flip-
flops can be connected or “cascaded” together to form a “divide-by-n” binary counter, the
modulo’s or “MOD” number still applies as it does for asynchronous counters so a Decade
counter or BCD counter with counts from 0 to 2n-1 can be built along with truncated sequences.
All we need to increase the MOD count of an up or down synchronous counter is an additional
flip-flop and AND gate across it.

SEVEN SEGMENT DISPLAY

Seven segment displays are the output display device that provides a way to display information
in the form of images or text or decimal numbers which is an alternative to the more complex
dot matrix displays. It is widely used in digital clocks, basic calculators, electronicmeters, and
other electronic devices that display numerical information.It consists of seven segments of
light-emitting diodes (LEDs) which areassembled like numerical 8.
Working of Seven Segment Displays:
The number 8 is displayed when the power is given to all the segments and if you disconnect
the power for ‘g’, then it displays the number 0. In a seven-segment display, power (or voltage)
at different pins can be applied at the same time, so we can form combinations of display
numerical from 0 to 9. Since one seven-segment displays cannot form numbers from 10 we
could use two displays that can form numbers from 0 to 99. So we can easily count numbers
for a 4 –bit counter from0 to 15 upward and down ward.
COUNTER INTERFACED WITH 7 SEGMENTED DISAPLAYS
PROCEDURE:

 Collect the required components and check it.

 Connections are to be made as per the diagram.
 Give the input conditions to the circuit.
 Verified the outputs of up counter and down counter.
 Connect the output of up counter and down counter to 7 segmentdisplays.
 Verify both outputs according to clock pulses.

RESULT:
Constructed the 4 bit asynchronous up counter and down counter and verified the truth
table.