Scribd
Upload
30 views

Mohan-Vamsi-Devalraju-Design-Verification-vlsi

VLSI verification

Uploaded by

204ec18028
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
30 views

Mohan-Vamsi-Devalraju-Design-Verification-vlsi

VLSI verification

Uploaded by

204ec18028
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

MOHAN VAMSI SEETHARAM DEVALRAJU

Mobile: +91-6301270276 | E-mail: mohanvamsidevalraju@gmail.com | GitHub URL | LinkedIn URL | Bengaluru

Aspired Digital Design and Verification Engineer - VLSI

Education
Bachelor of Technology in Electronics and Communication Engineering, CGPA: 7.55
K L University, Vijayawada April 2023
◦ B.Tech Coursework: Digital Electronics, Electromagnetism, Computer Organization and Architecture,
Analog Electronics, Embedded Systems, Internet of Things (IoT), RTL Design, Semiconductor Physics

Professional Training and Experience


Advanced VLSI Design and Verification Trainee April 2024
Maven Silicon VLSI Training Centre, Bengaluru | Certificate
◦ Generated Verilog RTL Design of RISC-V 32-bit Multi-Stage Pipe-line Processor. GitHub Link
◦ Directed 39 base integer instructions, sequential execution, control signals, and higher throughput.
◦ Verified 3 pipe-lined stages with Questasim, Xilinx, and Riviera Pro for linear TB validation and synthesis.
VLSI Design Online Training June 2021
Tessolve Semiconductors Pvt Ltd and K L University | Certificate
◦ Fabricated and evaluated CMOS inverter with Sky130 PDK, Xschem, Ngspice, Magic, Netgen.
◦ Enhanced simulation accuracy of electrical parameters, by 20% with SPICE and Sky-water. GitHub Link
◦ Attained precise layouts, optimized W / L ratios, 100% LVS match, and Analog Design integrity.

Technical Skills
VLSI Domain Skills | Domain: ASIC / FPGA / IP / CPU / SoC Digital Front-end Design and Verification

◦ Hardware Description and Verification: Verilog HDL (IEEE 1364), SystemVerilog HVL (IEEE 1800)
◦ Programming Languages: C / C++, Object-Oriented Programming OOPs
◦ Test Bench Methodology / Frameworks: Universal Verification Methodology (UVM) 1.2
◦ Verification Methodologies: Constraint Random Coverage Driven (CR CDV), Regression,
Assertions based (SVA), Formal Verification, Register-Transfer Level (RTL) Synthesis
◦ Wired Communication / Interfaces / Bus Protocols: AMBA AHB, APB, AXI, SPI, I2C, UART
◦ Refined ancillary skills over 6 months: Static timing analysis (STA), CMOS, FPGA, and Aptitude.
◦ Subordinates: Network theory, Microprocessors, Low Power, Cache, Memory Systems

EDA / CAD Tools Used in Hardware Design Flow:

◦ Design / Synthesis: Intel FPGA Quartus Prime, Xilinx ISE, Vivado, Cadence Virtuoso
◦ Simulation: Mentor Graphics ModelSim, QuestaSim, Synopsys Design Compiler and VCS
◦ Functional and Code Coverage / Assertions: Aldec Riviera-PRO | Linting: SpyGlass Lint
◦ Scripting / Automation: Perl, TCL | Debugging: Verdi | Formal Verification: Synopsys VC Formal
◦ Operating Systems: Windows 10, Linux Ubuntu 22.04.03 LTS | Project Version Control: GitHub

Projects
AHB2APB Bridge IP Core Verification | SystemVerilog, UVM, Functional Coverage, Riviera Pro April 2024
◦ Elevated data transfer efficiency with a protocol converter between 2 buses - faster AHB, slower APB.
◦ Devised UVM environment, achieved 90% coverage against Verification plan. GitHub Link
◦ Verified scenarios of 2 types- Single and Burst, READ/ WRITE operations, improved 20% data throughput.
Projects

Router 1x3 - RTL Design and Verification | Verilog, SystemVerilog, Questasim, Xilinx ISE February 2024
◦ Engineered a block-level 8-bit port router, directing data packets to 3 destinations. GitHub Link
◦ Designed, synthesized, and validated the router, with more than 10 test scenarios of full coverage.
◦ Accomplished RTL verification sign-off with 90% functional and code coverage.

Health Monitoring System with IoT | Embedded Systems, Wi-Fi 802.11, UART, I2C, SPI, IoT March 2023
◦ Crafted smart health monitoring with Arduino UNO R3 (UART), ESP8266 2.4 GHz Wi-Fi, and Cloud API.
◦ Designed with Arduino IDE system ensuring precise data measurement (pulse rate ±1 bpm, SpO2 ±2%,
humidity, temperature ±0.1°C) deploying MAX30100 (I2C) and generic sensors. GitHub Link
◦ Augmented real-time data logging and remote trend analysis with 16x2 LCD (SPI), ThingSpeak API.

Bank Management System C++ | OOP, File Handling, Algorithm Design, STL, CodeBlocks, Git April 2024
◦ Upgraded a C++ Banking System with a menu-driven interface, supporting up to 200 accounts.
◦ Customized 8 real-time functions for 100+ transactions and 50 user inputs per session. GitHub Link
◦ Computed with control structures, STL, strengthened data encapsulation and retrieval time under 2s.

Co-curricular Activities
◦ Sculpted multi-media (videos / 3D motion graphics) with Cinema 4D and After Effects, with ingenuity.
◦ Accelerated ECE Fest and led a social media team of 16 at KL University with communication prowess.
◦ Earned 2nd place in State Science Quiz on ETV Telugu Champion Show, with perseverance and insight.
◦ Pioneered a routine by dedicating 2 hours to avid reading, strategy gaming, art, and science exploration.

Languages Known
Navigated in 4 languages, including Native Telugu, Professional English, Fluent Hindi, and Basic Tamil.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy