HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY -VNU.

HCM
Faculty of Computer Science & Engineering

LABORATORY MANUAL
Digital Systems
Experiment 6 (Lab exam)

Ho Chi Minh City, November 2024

A. General Guidelines
- This “Lab Exam” can be considered Lab 6 and therefore
will be carried out exactly like other lab sessions. You
will be working in your assigned group and you will need
to submit the preparation report on LMS before the start
time of the session.
- The IC models that are available in the lab are: 7402,
7408, 7432, 7474, 7473, 74151, 7400, 7404, 7476,
7486, 74138, 7483 and 74157.
- A total of 10.5 marks can be earned, but the maximum
score is just 10 marks.
- You should write your preparation report with care and
show your work step-by-step, as it will be under more
scrutiny for the exam.
- Do not copy from other groups or let your report be
copied. You can discuss the problems with others, but
work presented in your group’s report should be that of
your own group’s only.

B. Problem 1: Boolean Algebra & Combinational

Logic (2.5 marks)
Task: Identify the given Boolean expression from the
statement (if needed) and simplify them (if possible). Then
design, simulate and implement the circuits for them using
1- or 2-input logic gates.
a. F=( AB+C) .( A+ B+C )
b. It is often said that the “triangle of life” involves
leisurely time (T), money (M), and health (H). At a
given point in life (L), one may
only have exactly 2 of the aforementioned 3.
Suppose that output L(H, T, M) is only HIGH
when its inputs satisfy the piece of wisdom
given above, find the appropriate Boolean
expression.

Questions:
(Answer in your report)
1. What is the SOP form of F?
2. When one is young, they have health and leisurely time,
but no money. When one is an adult, they have money
and health, but no free time. When one is old, they
have leisurely time and money, but no health.
Then for L(H, T, M), what minterms are the
equivalence of being young, being an adult, and
being old, respectively?
 3. According to the piece of wisdom, then what is life not
like? (In other words, what’s L(H, T, M)?) Give your
answer in POS form.

Grading:
- Your preparation report (maximum 1 mark).
- Correctly implementing F (0.5 marks).
- Correctly implementing L(H, T, M) (0.5 marks).
- (Bonus) Your design and implementation of F uses only 2
one- or two- input logic gate ICs of any kinds that are
available in the lab (0.5 marks).
Answer:
1.
 Minimized expression:
F=( AB+C) .( A+ B+C )
F=( A . B+C). A . B . C
F=( A . B+C). A . B . C
F= A . B+C + A . B . C
F= A . B+C + A . B
 Karnaugh map:

 SOP form: F (A , B , C)=∑ m(0 ,1 , 3 , 6 ,7 , 8).

2.
 Expression:
L(H , T , M )=H . T . M + H .T . M + H .T . M
 Karnaugh map:

 SOP form: L(H , T , M )=∑ m(3 ,5 , 6).

So,
- m(6) the equivalence of being young.
- m(5) the equivalence of being an adult.
 - m(3) the equivalence of being old.
3.
 Expression:
L(H , T , M )=H . T . M + H .T . M + H . T . M
¿ H .T . M . H . T . M . H . T . M
¿(H + T + M ).(H + T + M ). ¿)
 Karnaugh map:

 POS form: L(H , T , M )=∏ M (3 , 5 , 6).

4. Problem 2: Multifunctional counter (6 marks)
Task: Design, simulate and implement a MOD-16 counter
using D flip-flops (7474) and other 7400-series IC. The
counter should also have the following functionalities:
- Up/DOWN mode select: Should be connected to one of
the switches of your DS-KIT. If this input in 1, your
counter should count up,
incrementing by 1 each time; if this input is 0, your
counter should
countdown, decrementing by 1 each time. When this
signal changes between 0 and 1, it is acceptable for
the value of the counter to
asynchronously change.
- Asynchronous active-low CLR signal: Should be
connected to KEY_0 of your DS-KIT. As long as this input
is held LOW, your counter should
immediately return to and stay at 0.
- Active-high HOLD signal: Should be connected to KEY_1
of your DS-KIT. While this input is held HIGH, your counter
will not count up or down
(it can still be asynchronously cleared or changed).
When this input is back to LOW, counting will resume.
Answers :
1. Fill in the following truth table for the counter, where
COUNT is the current count and COUNT+ is the next
count. a in the table is the decimal value of COUNT.
CLR HOLD CLK U/D COUNT COUNT +
L X X X X 0
H H ↑ X a mod a mod 16
16
H L ↑ L a mod a-1 mod
16 16
H L ↑ H a mod a+1 mod
16 16
2. With COUNTA as the MSB, COUNTD as the LSB and X
denoting “don’t care”, complete the timing diagram
below. You may use the included
.drawio file and the draw.io service to complete this
question.

Grading:
- Your preparation report (maximum 3 marks).
- Your implementation can count up and down through
2 whole cycles each (0.25 marks if only up or down,
0.75 marks for both).
 - The modulus of your implementation (0.25 marks
for MOD-4, 0.75 marks for MOD-16).
-Your implementation is asynchronously cleared when
KEY_0 is pressed (0.25 marks) and stays at 00002 when
the button is held down (0.5 marks).
- Your implementation can hold the current count when
KEY_1 is held down (0.25 marks) and resume counting
when KEY_1 is released (0.25 marks). Clearing the
counter should also work while KEY_1 is held down
(0.25 marks).
 Design:

 Stimulate:

3. Problem 3: Finite state machine (2 marks)

Task: Consider the FSM in the figure below, with 0002 as the
starting state. The binary number preceding the slash is
the encoding for the state, while the number after the slash
is the output of the FSM while it is in that state.
 Answers :
(Answer in your report. Have your Logisim files readily
open on your device for this portion of the lab.)
1. Complete the following truth table with S2 S1 S0 as the
current state, I as the input to the FSM that determines the
¿
+¿ S ¿
state change, 0 as the output of the FSM, and S2 ¿ as the next
¿

state. Use “don’t care” wherever possible (0.5 marks).

Input/current stage Output/next stage
+¿ ¿ +¿ ¿ +¿ ¿
S2 S1 S0 I S 2 S1 S0 O

0 0 0 0 1 0 0 0
0 0 0 1 0 1 1 1
0 0 1 0 0 0 1 1
0 0 1 1 1 0 0 0
0 1 0 x x x x x
0 1 1 0 0 1 1 1
0 1 1 1 1 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 1 1
1 0 1 x x x x x
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 1 1 1 1
1 1 1 1 0 0 0 0
2. Give explanations and reasonings for your design of this
FSM (0.5 marks).

Karnaugh maps Minimized expression

+¿ ¿ +¿=S2 . S1+ S2 .S0 . I +S2 . S0 . I+ S2 . S0 . I ¿

S2 S2

+¿ ¿ +¿=S2 . S1+ S2 .S1 +S2 . S0 . I+ S2 . S0 . I ¿

S1 S1

+¿ ¿ +¿=S0 . I+ S0 . I ¿
S0 S0

O O=S 0 . I + S 0 . I

3. Simulate your design for this FSM in Logisim using D flip-

flops and logic gates (0.5 marks).
4. Based on the symbolic design in your previous answer,
create a wiring diagram with relevant ICs using Logisim and
create a netlist (0.5 marks).