Q.1 What is meant by hardwired control? Draw and explain typical hardware control unit.

Ans - Hardwired control refers to a type of control unit design where the control signals are
generated by combinational logic circuits, which are hardwired or fixed. This means the
instructions in the control unit are implemented directly with physical circuits. This approach is
typically faster than microprogrammed control but less flexible.
Here’s a simplified look at a typical hardware control unit:
1. Instruction Register (IR): Stores the current instruction.
2. Instruction Decoder (ID): Decodes the instruction to determine the control signals required.
3. Control Logic Generator: Generates the appropriate control signals based on the instruction.
4. Timing and Control Unit: Synchronizes the operations and ensures correct sequencing.
These components work together to direct the various parts of the CPU to perform the desired
operations based on the instructions.

Q.2 What are the differences between hardwired and micro programmed control units?
Ans -
Feature Hardwired Microprogrammed
Speed Faster Slower
Flexibility More flexible Less flexible
Complexity More complex to design for Simpler to design and modify
large instruction sets
Cost Potentially higher due to Potentially lower, changes are
hardware complexity software-based
Implementation Implemented with fixed, pre- Implemented with a sequence
designed circuits of microinstructions stored in
memory
Modifications Requires hardware redesign Can be modified by updating
microinstructions
Q.3 Write down advantages and disadvantages of Hardwired control units.
Ans - Advantages of Hardwired Control Units :
1. Speed: Hardwired control units are typically faster because the control signals are generated
using fixed, direct pathways.
2. Efficient Execution: They execute instructions more efficiently due to the minimal delay in
control signal generation.
3. Lower Latency: Reduced latency in instruction processing since the hardware pathways are pre-
defined.
4. Optimized for Specific Tasks: Highly optimized for specific tasks, making them ideal for
applications where speed is critical.

Disadvantages of Hardwired Control Units :

1. Inflexibility: Hard to modify or update once built, as changes require redesigning and re-wiring
the hardware.
2. Complex Design: Designing the control unit becomes more complex with an increase in
instruction set size.
3. High Cost: Potentially higher cost due to the intricacies involved in designing and building the
hardware circuits.
4. Scalability Issues: Less scalable since adding new instructions or features necessitates physical
changes to the hardware.

Q.4 What is Pipelining? What are the major characteristics of a Pipeline? What are the
various stages in a Pipeline execution?
Ans - Pipelining is a technique used in computer architecture to improve the overall performance of
the processor. It works by dividing the execution of instructions into separate stages, allowing
multiple instructions to be processed simultaneously, but at different stages of completion.

Major Characteristics of a Pipeline:

1. Concurrency: Multiple instructions are processed at the same time, each in a different stage of
execution.
2. Throughput: Increased overall instruction throughput, as more instructions are completed in a
given amount of time.
3. Latency: Slight increase in the latency of individual instructions due to the overhead of managing
stages.
4. Efficiency: Improved utilization of processor resources by overlapping the execution phases.

Various Stages in a Pipeline Execution:

1. Fetch: The instruction is fetched from memory.
2. Decode: The fetched instruction is decoded to understand what action is required.
3. Execute: The decoded instruction is executed; the necessary operations (like arithmetic) are
performed.
4. Memory Access: Memory operations, if any, are performed here (like loading or storing data).
5. Write Back: The result of the execution is written back to the register file.

Q.5 What are the types of pipeline hazards? Define structural, data, and control hazard.
Ans - Pipeline hazards are conditions that prevent the next instruction in the pipeline from
executing during its designated clock cycle. There are three main types of pipeline hazards:

1. Structural Hazards
These occur when two or more instructions require the same hardware resource simultaneously,
leading to a conflict. For example, if two instructions need to access memory at the same time, and
the pipeline does not have separate hardware paths for them, a structural hazard occurs.
2. Data Hazards
These happen when instructions depend on the results of previous instructions, causing delays.
There are three types of data hazards:
1. RAW (Read After Write): An instruction needs to read a value that hasn't been written yet by a
previous instruction.
2. WAR (Write After Read): An instruction needs to write a value, but a previous instruction hasn't
read it yet.
3. WAW (Write After Write): Two instructions need to write to the same location.

3. Control Hazards
Also known as branch hazards, these occur when the pipeline makes incorrect guesses about the
path of execution, often due to branch instructions. If the pipeline incorrectly predicts the path, it
must flush and reload with the correct instructions, causing delays.

Each of these hazards can lead to stalls or bubbles in the pipeline, reducing efficiency and
performance. But modern processors use various techniques to mitigate these hazards, such as
branch prediction, pipeline interlocking, and out-of-order execution. What's next on your plate?

Q.6 List two conditions when processor can stall. List the techniques used for overcoming
hazard.
Ans - Conditions When a Processor Can Stall:
1. Data Hazard:
When a subsequent instruction depends on the result of a previous instruction that hasn’t completed
yet.
2. Control Hazard:
When the pipeline encounters a branch instruction and the outcome (whether the branch is taken or
not) is not yet known, causing uncertainty about which instruction should be fetched next.

Techniques to Overcome Hazards:

1. Pipeline Interlocking:
The control unit inserts stall cycles into the pipeline to ensure that the dependent instruction waits
until the hazard is resolved.
2. Branch Prediction:
The processor guesses the outcome of a branch instruction to keep the pipeline filled. If the guess is
wrong, the pipeline is flushed, but overall performance improves with correct predictions.
3. Forwarding (Data Hazard):
Also called "bypassing," this technique passes the result of an instruction directly to a subsequent
instruction that needs it, without waiting for the result to be written back to the register.
4. Speculative Execution:
The processor executes instructions ahead of a conditional branch, based on a prediction. If the
prediction is correct, the work is useful; if not, the results are discarded.

Q.7 Explain instruction pipelining.

Ans - Instruction pipelining is like an assembly line for computer instructions. Instead of processing
one instruction at a time, a pipeline divides the instruction processing task into several stages and
processes different parts of multiple instructions simultaneously.

Breakdown of Instruction Pipelining:

1. Fetch Stage: The instruction is fetched from memory.
2. Decode Stage: The fetched instruction is decoded to determine what actions are needed.
3. Execute Stage: The necessary operations, like arithmetic or logical operations, are performed.
4. Memory Access Stage: If needed, the instruction accesses memory to read or write data.
5. Write Back Stage: The results of the executed instruction are written back to the registers.

Q.8 What is branch hazard? Describe the method for dealing with the branch hazard?
Ans - A branch hazard, or control hazard, occurs when the pipeline makes incorrect predictions
about the path of execution due to branch instructions (like if-else statements or loops). This leads
to delays as the pipeline has to flush incorrect instructions and load the correct ones.
Methods to Deal with Branch Hazards
1. Branch Prediction: The processor guesses the outcome of a branch. If the guess is correct, the
pipeline continues smoothly. If incorrect, the pipeline flushes incorrect instructions and reloads with
the correct path.
2. Branch Target Buffer (BTB): This is a small, special cache that stores the destination of recently
taken branches, helping to predict and fetch the correct instruction.
3. Delayed Branch: The compiler rearranges instructions so that useful work is done during the
delay caused by a branch instruction. This mitigates the impact of control hazards.
4. Pipeline Interlock: The control unit stalls the pipeline until the branch decision is made, avoiding
incorrect instructions being processed.
5. Speculative Execution: The processor executes instructions ahead of a conditional branch based
on a prediction. If the prediction is correct, the results are used; if not, they are discarded.

Q.9 What is data hazard? Explain the methods for dealing with data hazard?
Ans - Data hazard occurs when instructions that are close together in the pipeline depend on each
other, leading to incorrect execution if not handled properly. It's like trying to build a tower of
blocks when you haven't finished stacking the previous layer—it gets messy.

Methods for Dealing with Data Hazards:

1. Forwarding (Bypassing): This technique passes the result of one instruction directly to a
subsequent instruction that needs it, without waiting for the result to be written back to the register.
2. Pipeline Interlocking (Stalling): The control unit detects the hazard and stalls the pipeline until
the data dependency is resolved, ensuring the instructions are executed in the correct order.
3. Operand Forwarding: Similar to forwarding, this technique moves the required operand data to
the next stage to be used before the write-back stage is completed.
4. Out-of-Order Execution: Instructions are executed out of order to optimize resource use and
resolve dependencies sooner. This requires sophisticated hardware to track and reorder instructions
correctly.
5. Register Renaming: It eliminates false dependencies by assigning different physical registers to
the same logical register used by multiple instructions, thus avoiding WAW and WAR hazards.