AMD Versal AI Edge Series Gen 2

Product Selection Guide

Versal AI Edge Series Gen 2
Product Selection Guide
 AMD Versal AI Edge Series Gen 2 – Resources
2VE3304 2VE3358 2VE3504 2VE3558 2VE3804 2VE3858
AI Engine-ML v2 Tiles 24 24 96 96 144 144
AI Engine AIE-ML v2 Data Memory (Mb) 12 12 48 48 72 72
AIE-ML v2 Shared Memory (Mb) 48 48 96 96 288 288
#APU Cores / #RPU Cores 4/4 8 / 10 4/4 8 / 10 4/4 8 / 10
Application Processing Unit Arm® Cortex®-A78AE, 64 KB I w/parity & D w/ECC L1 Cache, 512 KB L2 Cache, 1 MB L3 Cache (per 2-core cluster), CMN600 w/4 MB Last-Level Cache (shared)
Processing Real-Time Processing Unit Arm Cortex-R52, 32 KB L1 Cache w/ECC, 128 KB TCM w/ECC
System Memory 2 MB On-Chip Memory w/ECC
High-Speed Connectivity PCI Express® Gen5 x4, USB 3.2, DisplayPort 1.4, 10G Ethernet, 1G Ethernet, UFS 3.1
General Connectivity CAN/CAN-FD, SPI, UART, USB 2.0, I2C/I3C, GPIO
System Logic Cells 206,920 206,920 492,188 492,188 1,188,040 1,188,040
LUTs 94,592 94,592 225,000 225,000 543,104 543,104
Programmable
DSP Engines 184 184 700 700 2,064 2,064
Logic
NoC Master / NoC Slave Ports 4 4 7 7 24 24
Distributed RAM (Mb) 2.9 2.9 6.9 6.9 16.6 16.6
Total Block RAM (Mb) 5.0 5.0 13.6 13.6 47.2 47.2
UltraRAM (Mb) 13.2 13.2 3.4 3.4 33.2 33.2
Memory Total PL Memory (Mb) 21.1 21.1 23.9 23.9 97.0 97.0
DDR Memory Controllers 3 3 4 4 5 5
DDR Bus Width 96 96 128 128 160 160
GPU (4-core Arm Mali -G78AE) 1 1 1 1 1 1
Video and
Video Codec Unit (VCU) - 1 - 1 - 1
Imaging IP
Image Signal Processor - 1 - 3 - 3
GTYP (PL only) 4 4 12 12 20 20
Transceivers
GTYP (PS only) 4 4 4 4 4 4
Integrated PCI Express (PLPCIE5) 1 x Gen5 x4 1 x Gen5 x4 3 x Gen5 x4 3 x Gen5 x4 4 x Gen5 x4 4 x Gen5 x4
Connectivity IP 100G Multirate Ethernet MAC 1 1 1 1 3 3
Ordering Extended Temp1 -1MSE, -1LSE, -2MSE, -2MLE, -2LSE, -2LLE
Information Industrial Temp1 -1MSI, -1MLI, -1LSI, -1LLI, -2MSI, -2MLI, -2LLI

1. In2extended
| and industrial temperature grades, some ordering combinations can operate for a limited time with a junction© Copyright
temperature 2024 Advanced
of 110°C. Microadhere
Timing parameters Devices, Inc. speed file at 110°C as they do below 110°C, regardless of operating
to the same XMP505 (v1.3)
voltage. Operation at 110°C Tj is limited to 3% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does not exceed 3% of device lifetime.
 AMD Versal AI Edge Series Gen 2 – Packaging
2VE3304 2VE3358 2VE3504 2VE3558 2VE3804 2VE3858
X5IO DDR Only, X5IO DDR+PL, X5IO PL Only
Package
Package Footprint Ball Pitch (mm) HDIO, MIO
Dimensions (mm)
GTYP (PL Only), GTYP (PS Only)
176, 48, 32 176, 48, 32
SFVA1089 27 x 27 0.8 22, 78 22, 78
4, 4 4, 4
168, 64, 32 192, 136, 0
SFVA1440 31 x 31 0.8 44, 78 88, 78
4, 4 4, 4
168, 64, 32 168, 64, 32 192, 136, 0 192, 136, 0
SBVA1440 31 x 31 0.8 44, 78 44, 78 88, 78 88, 78
4, 4 4, 4 4, 4 4, 4
232, 152, 0 232, 152, 0 208, 272, 32 208, 272, 32
SSVA2112 37.5 x 37.5 0.8 44, 78 44, 78 44, 78 44, 78
12, 4 12, 4 20, 4 20, 4

3 | © Copyright 2024 Advanced Micro Devices, Inc. XMP505 (v1.3)

 AMD Versal Device Ordering Information

Device Name Device Attributes Package Definition

XC 2 V E 3558 -1 M S E S B V A1444
Device Grade Generation(1) Architecture Series Name Device Number Speed Grade Voltage Static Screen Temp Grade Ball Pitch Lid RoHS6 Code (3) Footprint
XC: Commercial 2: Gen 2 Versal E: AI Edge Digits 1-3: -1: Slowest L: Low S: Standard E: 0 to 110°C(2) V: 0.92 mm, S: Lidless, V: Pb-free Ball
XA: Automotive C: AI Core Value Identifier -2: Mid M: Mid L: Low Static I: –40 to 110°C(2) w/LSC w/Stiffener Ring Q: Eutectic Ball
XQ: Defense M: Prime Digit 4: # of -3: Highest H: High Q: –40 to +125°C N: 0.92 mm, F: Lidded R: Ruggedized,
P: Premium Primary Cores M: –55 to +125°C no LSC B: Lidless, Eutectic Ball
H: HBM S: 0.8 mm no Stiffener Ring
R: RF L: 1.0 mm H: Lidded
Overhang
I: Lidless,
w/Stiffener Ring &
Overhang

Note:
1. This character is only present in second generation Versal devices.
2. Operation at 110°C Tj is limited to 3% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does not exceed 3% of device lifetime—except -1E and -3E (standard 0–100°C).
3. All packages have Pb-free bumps.

4 | © Copyright 2024 Advanced Micro Devices, Inc. XMP505 (v1.3)

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© Copyright 2024 Advanced Micro Devices, Inc. All rights reserved. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Versal, and other designated brands
included herein are trademarks of Advanced Micro Devices, Inc. DisplayPort and the DisplayPort logo are trademarks owned by the Video Electronics
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