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Planar Transformers With Near-Zero Common-Mode Noise for Flyback and

Forward Converters

Article in IEEE Transactions on Power Electronics · March 2017

DOI: 10.1109/TPEL.2017.2679717

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 1

Planar Transformers with Near Zero Common

Mode Noise for Flyback and Forward Converters
Mohammad Ali Saket, Student Member, IEEE, Martin Ordonez, Member, IEEE, Navid Shafiei, Student
Member, IEEE

Abstract—Flyback and Forward converters are two com- these topologies highly depends on the characteristics of trans-
monly used topologies for isolated low power applications. former, which is a key part of these converters. Fig. 1 (a) shows
These converters are simple and cost effective and provide topology of a Flyback converter and provides a list of important
galvanic isolation which make them desirable for low power challenges in designing high-efficiency, high power-density Fly-
levels. In order to enhance the performance of these con- back converters. The transformer leakage inductance significantly
verters, planar transformers (PT) can be used that feature affects the performance of Flyback and Forward power converters,
lower height, considerably lower leakage inductance, excellent especially for the Flyback topology. Large leakage inductances that
thermal characteristics, and repeatability. Selecting a proper are present in the traditional wire-wound transformers cause large
winding arrangement for PT is a significant challenge, in voltage spikes on the switch, leading to the selection of switches
particular given the large capacitances involved in flat struc- with higher rated voltage. Beside, large voltage spike creates large
tures. While interleaved structures significantly reduce the AC dv/dt which creates Common-Mode (CM) noise in the switch
resistance and leakage inductance of PTs, they also lead to very parasitic capacitance [4] and transformer inter-winding capacitance.
large inter-winding capacitance, which produces significant The transformer form factor also significantly affect the overall
levels of undesired common-mode (CM) noise that causes EMI height and size of the converter as usually it is the tallest and
problems. Reducing inter-winding capacitance by using non- bulkiest part of the circuit. Due to their high height, traditional
interleaved structures is not an ideal solution to the CM cores cannot be used in certain low profile applications like Flat
noise problem because of its side effects. Instead, this paper TVs or portable devices. Higher height also is a disadvantage from
tackles the problem by proposing the concept of paired layers. heat transfer point of view, as it leads to high thermal resistance.
According to this concept, there are layers in the primary Fig. 1 (b) summarizes the aforementioned drawbacks of wire-
and secondary sides that have the same dv/dt and, therefore, wound transformers. Some of these problems can be resolved using
their overlapping does not generate CM noise. These layers planar transformers (PT), which are well suited to flat implement
can be used to design highly interleaved structures that not slim-profile power converters. They provide extremely low leakage
only have very low AC resistance and leakage inductance, inductances that cannot be attained using traditional wire-wound
but also generate almost zero CM noise, although they may transformers and elaborated interleaved structures can be imple-
have a very large inter-winding capacitance. In addition, a mented easily in PTs in such a way as to minimize AC resistance
detailed parasitic capacitance model of PTs is proposed which [5, 6]. PTs also offer exceptionally low thermal resistance (due to
analytically validates the proposed concept and method. The their higher surface to height ratio), repeatability and manufacturing
experimental results show that the proposed PTs not only simplicity [7–11]. Despite these advantages, PTs have extremely
have very low AC resistance and leakage inductance, but also high inter-winding parasitic capacitance, due to the proximity of
generate extremely low levels of CM noise. Considering that the the layers and their significant overlap, and this generates large
proposed PT has inter-winding capacitance equal to 700pF , it levels of Common-Mode noise leading to serious EMI problems
is very interesting to see that it generates significantly less [12–20]. In general, CM noise is created by the displacement
CM noise than does a traditional wire-wound transformer current that flows from the voltage pulsating nodes in the circuit
that has only 10pF parasitic capacitance. Therefore, the to the protective earth (PE) though the parasitic capacitance [20].
proposed method gives designers the opportunity to minimize Fig. 1 (a) shows how CM noise currents are generated in the
AC resistance and leakage inductance by using highly inter- parasitic capacitances and circulate in the circuit. According to this
leaved structures, without having to worry about CM noise figure, transformer parasitic capacitances play a major role in CM
caused by large inter-winding capacitance. noise generation. These parasitic capacitances not only generate
CM noise, but also provide a path for secondary side parasitic
Index Terms - Common-mode (CM) noise, Planar capacitances and lead to the the generation of CM noise currents
Transformer (PT), Parasitic Capacitance Model, Paired in these parasitic capacitances. While interleaved structures that
Layers, Flyback have many intersections between primary and secondary windings
can significantly reduce AC resistance and leakage inductance and
enhance the efficiency of the transformer, they also lead to very
large parasitic capacitance, which increases the level of CM noise
I. I NTRODUCTION
generated. Higher levels of CM noise require more attenuation to
Flyback and Forward converters are traditional topologies com- comply with standards and regulations, and this requires the use of
monly used for low to medium power isolated applications [1– larger CM choke filters at the input of the converter. To date, no
3]. The efficiency, performance, power-density, and form factor of method of reducing winding capacitances can reduce AC resistance
 2

2 2 1
Challenges: 1 Transformer Effects:
1 EMI C14 icm-14
Inter-winding Capacitance
2 Efficiency C13 icm-13
Llk Rac 1 EMI (CM noise)

3 Form Factor Leakage Inductance

4 Heat Extraction LISN 1 EMI (Large dv/dt over switch)
2 Efficiency (Snubber Loss)
C24 icm-24
CS-G
C23 icm-23 AC resistance
1 Efficiency (Conduction Loss)

1
Csw
i CM i CM 2iCM
PE

(a)
Wire-Wound Transformer Proposed PT
4
Small area for Excellent Heat
2 Large (dv/dt) as 4 heat extraction 2 extraction capability
a result of Llk
Small (dv/dt) as
a result of low Llk
3
Low
3 VSw profile
High profile
VSw t (50-60% less)
t

12
Ext
Extremely low
1 levels of CM noise
Large Levels
CM noise

(b) (c)
Fig. 1: a) Topology of Flyback converter along important challenges in designing power Converters. Leakage inductance and transformer
parasitic capacitance are major causes of CM noise. b) The main drawbacks of wire-wound transformer including high levels of noise,
high leakage inductance, high height, and high thermal resistance. c) The problems of traditional transformers can be resolved using the
proposed PTs which not only have very low leakage inductance and AC resistance, but also generate almost zero levels of CM noise.

and leakage inductance [10]. This problem is considered thoroughly cannot provide an enough low impedance path to shunt away all
in this paper, and a solution is proposed to attain very low CM noise the noise. Regarding the transformer structure, mitigation methods
and high efficiency simultaneously for PTs. Fig. 1 (c) presents the can be classified into two groups. In the first group, additional
advantages of the proposed PTs in this paper. The proposed PTs layers are added to the transformer structure to either shunt away or
not only have very low AC resistance and leakage inductance (as inject anti-phase displacement currents to reduce the noise. These
a result of highly interleaved structures), but also have near zero methods are applicable on both wire-wound and PTs and include
CM noise emission. Indeed, while the proposed PTs have a very using Faraday shield [20–22], introducing out of phase displace-
large inter-winding capacitance, they generate close to zero CM ment currents [23–25] and integrating Y-cap in the structure of the
noise due to the paired layers concept, which significantly reduces transformer [12]. While these methods are successful in reducing
the size of the required CM choke filters. the noise, they cannot be used in highly interleaved structures, as
many additional layers are required. The second group of methods
The effect of parasitic capacitance of transformer on the CM target the source of CM noise and mitigate the CM noise without
noise for Flyback and Forward converters have been considered adding extra layers. Reducing the inter-winding capacitance [8, 13],
in the literature, and interesting methods have been presented to is the most straightforward method in reducing the CM noise and
mitigate CM noise owing to the transformer parasitic capacitance. can be done in both wire-wound transformers and PTs. This can
Adding a Y-cap between primary and secondary is one way to be done using a non-interleaved structure or avoiding the overlap
shunt away the transformer noise. However, the application of Y- between the primary and secondary windings. However, doing this
Cap is always limited by safety standards [24] and this method
 3

dramatically increases the AC resistance and therefore conduction This paper is organized into six sections. In section II, the
losses. Recently, the winding cancellation method for wire-wound requirements of Full CM noise cancellation (which also is called no
transformers have been presented in a number of papers [16, 19] CM noise generation through the paper) for Flyback and Forward
and [27–30]. This method minimizes the amount of CM noise converters are proposed. Section III proposes a detailed parasitic
generated, not by reducing the inter-winding capacitances, but by capacitance model and develops the concept of paired layers as
reducing the dv/dt these capacitances are exposed to and, therefore, criteria for PT structures that achieve full CM noise cancellation.
it does not produce the side effects of other methods, such as higher Section IV is dedicated to the implementation of the proposed
winding resistance or extra eddy current loss. As the problem of method for different turn ratios. Section V provides experimental
parasitic capacitance is more significant with PTs, having a similar results and, finally, the conclusion is presented in Section VI.
method that can attenuate the CM noise without requiring extra
components or leading to additional loss and increased complexity II. T HE R EQUIRED C ONDITION FOR N O CM N OISE
is highly beneficial. Therefore, there is a significant opportunity
to develop winding cancellation technique for PTs to achieve high
G ENERATION IN F LYBACK AND F ORWARD C ONVERTERS
efficiency PTs with minimum CM noise generation. This paper In order to achieve no generation of CM noise in the transformer
investigates winding cancellation technique for PTs and shows that of Flyback and Forward converters, these topologies should be real-
PTs are the best candidate for winding cancellation technique and ized using the right configuration. In addition, transformer lumped
can provide almost zero generation of CM noise which is hard to parasitic capacitances should also satisfy a certain condition. In this
achieve with wire-wound transformers. section, the required configuration of the aforementioned topologies
This paper develops a winding cancellation technique for PTs is proposed, and an equation that describes the required relationship
that are used in Flyback and Forward converters, and the analysis between the transformer lumped parasitic capacitances has been
presented finally eliminates the trade-off between EMI problems proposed. This equation is used in the next section to find winding
(inter-winding capacitance) and high efficiency performance (low arrangements that generate no CM noise.
AC resistance and leakage inductance). The proposed method relies The level of CM noise that is generated due to the transformer
on the concept of paired layers that matches the layers with similar inter-winding capacitance depends on the voltages at the trans-
dv/dt and shows which layers can overlap without generating former terminals. Both Flyback and Forward converters have a
CM noise. Once this concept is employed, highly interleaved static terminal in each side, which is not affected by the switching
structures with low AC resistance and leakage inductance that of the converter. The remaining two terminals have pulsating
have near zero CM noise generation are possible for Flyback
and Forward converters. In developing the technique, this paper
employs a step-by-step approach. First, the required conditions C14 i14
for achieving no CM noise generation in Flyback and Forward v1 C13 i13 v3
V nV
converters are provided. In addition, the following models and iCM
dv1 1 3 dv3
methods are proposed in this paper. dt Vδ(t) dt nVδ(t)
C12 C
34
1) The proposed comprehensive parasitic capacitance model
v2 v4
of PTs: In order to establish a theoretical basis for the iCM 2 C24 i24 =0 4
proposed method, an in-depth parasitic capacitance model dv2 dv4
of PTs is developed using energy method [31]. dt i23 dt
2) Systematic development of the paired layers concept: The C23
capacitance model developed in the previous part is used
(a)
to propose the concept of paired layers, which defines the
criteria for PT structures that generate no CM noise. i14
C14
3) Implementation of the proposed method for different
turn ratios: The proposed method has no limitation re- v1 C13 i13 v3
V nV
garding turn ratios and can be applied under all conditions. iCM 1 3
dv1 dv3
However, depending on the number of turns, there are two dt Vδ(t) dt nVδ(t)
C12 C
different ways of implementing the method, and these are 34

explained using examples. v2 v4

iCM 2 C24 i24 =0 4
In order to show the validity of the paired layers concept, a dv2 dv4
dt dt
PT has been realized using the method and compared with a wire-
wound transformer. Since the proposed PT uses a highly interleaved C23 i23= i13+i14
structure, it has a very low leakage inductance and AC resistance. (b)
Regarding the generated CM noise, it is interesting to observe that
the proposed PT, which has a very large inter-winding capacitance Fig. 2: Transformer CM Noise cancellation requirement for Fly-
of 700pF, generates significantly lower CM noise than does the back and Forward converters using six capacitance model of
wire-wound transformer that has an inter-winding capacitance of the transformer. Both Flyback and Forward converters have one
only 10pF. In other words, although the inter-winding parasitic static point and one swinging point in each side. a) Swinging
capacitances of proposed PTs are very large, they generate almost points change in the opposite directions (wrong condition) and b)
zero CM noise, as dv/dt over the parasitic capacitance is almost swinging points change in the same direction (right condition). In
zero. Since these parasitic capacitances do not conduct current, order to achieve no CM noise generation, the swinging terminals
they do not resonate with other circuit elements and, therefore, should change in the same direction and so have the same polarity
they have no effect on the converter’s performance. of dv/dt.
 4

voltages that change relative to each other. In order to show what

i14 =0 v1 Vd
condition is required to achieve CM noise cancellation for the C14
transformer, Figures 2 (a) and (b) show two different conditions C13 i13 v2 a
that can occur in the aforementioned power converters. The whole
effect of transformer inter-winding capacitance on CM noise can 1 3 v3 Vo
be modeled using four lumped capacitors between terminals of the
2 4 v4 na
primary and secondary. These two figures are only different in the
way that voltages in the swinging terminals change relative to each Vd C24 i24
dv1
other. From the continuity of the current in the green cut-set of Fig. C23 i23 dt
aδ(t)
2 (a), (1) can be derived. dv2
dt aδ(t)
dv3
2iCM = i13 + i14 + i23 + i24 (1) dt naδ(t)
dv4
dt
The expressions for the displacement currents have been pre- naδ(t)
sented in (2). (a)
dv1 dv3

i13 = C13 −
dt dt v1 Vd
dv1 dv4
dv1 C14 i14 =0
i14 = C14 − = C14
dt dt dt C13 i13 v2 a
(2)
dv2 dv3
dv3
i23 = C23 − = −C23 3
v
dt dt dt 1 3 na
dv2 dv4
2 4 v
i24 = Cac − =0 4
dt dt Vd C24 i24 dv1 aδ(t)
No CM noise generation means that the iCM should be equal C23 i23 dt
dv2 naδ(t)
to zero. In order to achieve this, i13 , i14 , i23 , and i24 should dt
cancel one another out and make the total CM noise equal to zero. dv3
Equating iCM to zero in (1) and using (2), the required conditions dt
dv4
for achieving full CM noise cancellation for Flyback and Forward dt
converters can be obtained, and are presented in (3).
(b)
dv1
dv3

C13 + C14 = C13 + C23 (3) Fig. 3: a) Flyback converter configuration with pulsating voltages
dt dt
that change in opposite directions (wrong configuration) and b)
Equation (3) can be achieved only if dv1 /dt and dv3 /dt have the Flyback converter configuration with pulsating voltages that change
same sign. When this condition is met, it means that the voltages in in the same direction (right configuration).
the swinging terminals change in the same direction. Otherwise, all
of the displacement currents will have the same direction and will
be unable to cancel each other out. This explanation is conceptually
depicted in Figs 2 (a) and (b). Fig. 2 (a) shows the condition 4 (b). In this configuration, the pulsating voltages change in the
in which the voltages are changing in opposite directions. In same direction and, therefore, the condition required for no CM
this case, the displacement currents all have the same direction noise generation is obtained. It should be mentioned that while the
and, therefore, they cannot cancel each other out. In contrast, the configurations that are shown in Figs. 3 and 4 do not have snubber
pulsating voltages in Fig. 2 (b) change in the same direction. circuits, the proposed method is also applicable for Flyback and
Under this condition, one of the displacement currents flows in Forward converters that have passive snubber circuits.
the opposite direction of the other two currents and, therefore, it While employing the right configuration for Flyback and For-
can cancels them out. Therefore, no CM noise generation for the ward converters is essential for winding cancellation method, it
Flyback and Forward converters requires that the pulsating voltages is not the only required condition. Full CM noise cancellation
change in the same direction. also requires that the transformer satisfy a certain condition. The
following analysis explains the conditions that the transformer must
Figures 3 (a) and (b) show two different configurations of Fly- satisfy in order to achieve no CM noise generation. If the coupling
back converter. For the Flyback converter, the right configuration between the primary and secondary windings is strong, dv1 /dt and
is the traditional one, which is shown in the Fig. 3 (b). In this dv3 /dt can be related to each other according to (4).
configuration, the pulsating voltages change in the same direction.
The other configuration of Flyback converter can be constructed by dv1 dv3
=k (4)
placing the diode in the return path, and is presented in Fig. 3 (a). In dt dt
this case, the pulsating voltages change in opposite directions and Where k is the transformer turn ratio (n2 /n1 ). Using this relation-
create significant levels of CM noise. Two possible configurations ship, (3) can be simplified and the following condition for achieving
of the Forward converter are shown in Figures 4 (a) and (b). no CM noise generation can be found.
For the Forward converter, the traditional configuration that is
shown in the Fig. 4 (a) cannot provide the required condition, (1 − k)C13 + C14 = kC23 (5)
as the pulsating voltages change in opposite directions. In order
to resolve this issue, the diode D1 and output filter inductance Therefore, if the transformer’s parasitic capacitances follow (5),
Lf are moved to the return path, which is shown in the Fig. displacement currents cancel each other out, and the net CM current
 5

is equal to zero. Equation (5) states the conditions necessary in a PT of the transformer should also satisfy the CM noise cancellation
to achieve no CM noise generation in the transformer of Flyback requirement of equation (5). In order to enable the design of PTs
and Forward converters. This equation will be used in the next that meet this requirement and result in zero CM noise for Flyback
sections to find winding arrangements that lead to zero CM noise and Forward converters, this section discusses a detailed parasitic
generation. capacitance model for the PTs. The model relates the distributed
In this section, the principles of CM noise cancellation for capacitance of layers to the lumped parasitic capacitances, and
Flyback and Forward power converters have been presented. In shows how different winding arrangements affect the value of each
order to use the proposed method, it is essential that Flyback lumped capacitance. In other words, the model discussed here fills
and Forward converters are realized using the right configurations. the gap between the microscopic distributed capacitances and the
Otherwise, the proposed method is not applicable. While using transformer lumped capacitance model. This model will then be
the right configuration is essential, there are also other required used to find a general winding method that satisfies the requirement
conditions. The transformer winding arrangement should also be for no CM noise generation that is expressed in (5), in order to
designed in such a way that parasitic capacitances satisfy (5). This obtain PTs that have almost no generation of CM noise.
requirement is used in the next sections to find interleaved winding
arrangements that generate close to zero CM noise.
A. Parasitic Capacitance Model for PTs
In this part, a general parasitic capacitance for the PTs is
III. T HE P ROPOSED S OLUTION F OR ACHIEVING NEAR discussed. The analysis starts with the capacitance model of two
overlapping layers, and will then be extended to create a complete
ZERO CM N OISE G ENERATION IN PT S
winding. Fig. 5 (a) shows two overlapping layers in the PTs. Since
In the previous section, the conditions necessary for no CM the terminations of different windings are usually on different sides
noise generation in the transformer for Flyback and Forward of the PTs, Fig. 5 (a) represents a typical interface of two layers
converters were presented. The correct configuration for these that belong to different windings (i.e one for the primary and the
power converters must be employed, and the parasitic capacitances other for secondary). There are four terminals corresponding to
these layers, which are shown as 1, 2, 3, and 4. Like the behaviour
of the transformer, the capacitive behaviour of this system can be
modeled with six lumped capacitances that are connected between
C14 i14 =0 v1 Vd the terminals of these layers. Three different voltages are needed to
b
C13 i13 v
a
c describe the electrostatic behavior of this system. These voltages
2 are shown in Fig. 5. V1 and V2 are defined as the voltage between
1 3 v3 na nc the terminals of the top and bottom layers, respectively. Vo is the
2 4 D1 nb offset voltage between two layers. Using this voltage definition,
v4 the voltage across each capacitor can be found. Energy method
Vd C24 i24 Lf
dv1 will be used here to find the parasitic capacitance model of this
C23 i23 dt a δ(t) system. According to energy method, the total electrostatic energy
dv2
dt b δ(t) c δ(t) of the system is equal to the energy that is stored in the lumped
dv3 nb δ(t) ncδ(t) capacitances. In order to calculate the energy of Fig. 5 (a), the
dt
dv4 na δ(t) layers should be straightened, while the voltage gradient between
dt them should be preserved. Since the directions of the layers are
(a) different, there is a discontinuity in the voltage gradient of the two
layers (which is indicated by the split line in Fig. 5 (a)). Therefore,
two straightened surfaces are required to model each layer. Fig. 5
C14 i14 v1 Vd (b) shows these surfaces. Since in these surfaces the voltage is
b
C13 i14 =0 v
a
c changing in just one direction, the voltage distribution of these
2 surfaces can be represented by a linear function that varies in one
1 3 v3 Vo dimension. The voltage distribution for the yellow and blue layers
2 4 D1 na nb are presented in (6).
v4 nc
Vd C24 i23 Lf
(
dv1 V1 Vo + V22 − VL2 x 0 < x < L2
C23 i24 dt Vy (x) = x Vb (x) = 3V2 V2 L
dv2 a δ(t) L Vo + 2 − L x 2
<x<L
dt bδ(t) c δ(t) (6)
dv3 Where L and W are the length and width of the layers in Fig. 5
dt
dv4 na δ(t) (a). When the voltage distribution is known, the total energy of the
dt
nb δ(t) nc δ(t) system can be found by (7).
(b) ZL
1 W
Fig. 4: a) Two possible configurations for Forward topology and Wt = 0 r (Vy − Vb )2 dx =
the voltage waveforms at the terminals of the transformer for each 2 d
0
configuration. a) Forward converter configuration with pulsating C0
voltages that change in opposite directions (wrong configuration) (4V12 − 7V1 V2 − 12V1 V 3 + 4V22 + 12V2 V3 + 12V32 )
and b) Forward converter configuration with pulsating voltages that 24
change in the same direction (right configuration).
(7)
 6

5C0
V1 24
V1
0
2
2 2 V1 7C0
2 V1
1
t li
ne 1 1 24 3
S pli
V2 V2+Vo -C0 -C0
+ Vo V1 V2
2 6 Vo 6
d V2 4 V2
Vo Vo + V3
4 0 L
3 2 2 7C0
24
4
W
3 2
x di x di 5C0
rect rect
ion L ion
2 L 24

(a) (b) (c)

Fig. 5: Electrostatic behavior model of two overlapping layers that belong to different windings: a) 3D model of the system along
terminals and voltage directions, b) the overlapping layers are straightened while the voltage gradient between overlapping layers is
preserved and c) the electrostatic model of the system

In the above equation, C0 is the static capacitance between the capacitance are presented in (10).
layers, and can be found by using the parallel plate capacitor
−C0
formula which is presented in (8). C12 = C34 =
6
W ×L 7C0
C0 = 0 r (8) C13 = C24 = (10)
d 24
5C0
C14 = C23 =
24
A similar analysis can be done for a case where the direction
The energy of the system also can be found by using lumped of the layers is the same. Fig. 6 (a) shows two overlapping
capacitors. The total energy of the system based on the lumped layers that have the same direction. This condition usually occurs
capacitance model is presented in (9). when the overlapping layers belong to the same winding (i.e
1 1 1 1 both belong to either primary or secondary). In order to extract
Wt = C12 V12 + C34 V22 + C24 Vo2 + C14 (V1 − Vo )2 the capacitance model of this condition, the overlapping layers
2 2 2 2
1 1 (9) should be straightened and the voltage gradient between the layers
+ C23 (V2 + Vo ) + C13 (V1 − Vo − V2 )2
2
should be preserved. Fig. 6 (b) shows these layers when they
2 2
are straightened. The voltage distributions of these surfaces are
presented in (11).
Equations (7) and (9) both represent the total electrostatic energy
V1 V2
of the system and therefore they are equal. Equating similar terms Vy (x) =x Vb (x) = V3 + x (11)
in these two equations, the value of the six lumped capacitors L L
can be found based on the static capacitance. These capacitors are When the voltage distribution is known, the electrostatic energy of
shown in Fig. 5 (c), and the describing terms based on the static the system can be found. Following the same procedure that was

C0
V1 0
6
C0
2 C0
1 1 3
3
2 V3 -C0 -C0 4
V2 1 V1
6 6 1 4
4
2 4
V3 3 V2+V3 C0
C0
3
4 3 6

(a) (b) (c) (d)

Fig. 6: Electrostatic behaviour model of two overlapping layers that belong to the same windings: a) 3D model of the system along
terminals and voltage directions, b) the overlapping layers are straightened while the voltage gradient between overlapping layers is
preserved, c) the electrostatic model of the system and d) the electrostatic model of the system if the overlapping layers are the successive
turns of the same winding.
 7

used in the previous ca=se, the capacitive model of this condition distributed parasitic capacitances of Fig. 7 (b) to the six capacitance
is shown in Fig. 6 (c), and the describing terms based on the static model of the transformer, one of the transformer terminals in each
capacitance are presented in (12). side is selected as a reference point. For the case that is presented
in Fig. 7 (b), the voltage at the terminals of primary layer are equal
−C0
C12 = C34 = to b×V1 and a×V1 , where b and a are defined as a ratio of voltage
6 at these terminals to the total voltage of primary. For instance, if
C0 the winding has eight turns, the values of a and b for the third
C13 = C24 = (12)
3 turn (layer) of the winding are equal to 3/8 and 2/8, respectively.
C0 These values for the last turn are equal to 8/8=1 and 7/8. A similar
C14 = C23 =
6 explanation is considered true for the parameters c and d on the
If the layers of Fig. 6 (a) are successive layers of the same secondary side. These parameters represent the ratio of voltage
winding, points 2 and 3 are connected and the capacitance model at the terminals of each secondary layer to the total voltage of
can be simplified. Under this condition, the equivalent capacitance secondary. Given this definition, it is possible to use energy method
between point 1 (start of the first layer) and point 4 (end of the to transfer the parasitic capacitance network of each overlapping to
second layer) is equal to C40 , which is shown in Fig. 6 (d). the terminals of the transformer, as shown in Fig. 7 (c). This can
be done by considering that the total electrostatic energies of Fig.
After developing the parasitic capacitance model for two over- 7 (b) and (c) are equal. The total energy of Fig. 7 (b) is presented
lapping layers, the parasitic capacitance model of two layers should in (13).
be extended to a complete transformer. Fig. 7 (a) shows a PTs with −1 C0 1 C0
an interleaved structure. Briefly, V1 and V2 represent the voltage Wt = (aV1 − bV1 )2 − (cV2 − dV2 )2
across the primary and secondary voltages. In other words, V1 and 2 6 2 6
1 7C0 1 7C0
V2 are the voltage between the beginning of first turn and the end + (aV1 − cV2 − Vo )2 + (bV1 − dV2 − Vo )2
of last turn of the primary and secondary windings, respectively. 2 24 2 24
1 5C0 1 5C0
The parasitic capacitance model of one intersection of primary and + (aV1 − dV2 − Vo )2 + (bV1 − cV2 − Vo )2
secondary is shown in Fig. 7 (b), which is similar to the parasitic 2 24 2 24
(13)
capacitance model of Fig. 5 (a). In this figure, every layer is shown
with a grey rectangle, and a series connection of these rectangles
constitutes the winding. As is shown in Figs. 7 (a) and (b), there are This equation is equal to (9), which represents the total energy
two terminals for each layer (one at the beginning of the layer and in Fig. 7 (c). Equating similar terms in these equations, the required
one at the end), and each of these terminals experiences a different equations for transferring parasitic capacitances to the winding
pulsating voltage. The voltage waveforms at the terminals of each terminals are presented in Table I. Table I shows that the value
layer depend on the position of that layer. In order to relate the of transferred capacitances depends on the parameters a, b, c,

V2 C13
1 3 V1 1 3 V2

V1
C14

} 7C0
aV1 24 cV2

.. -C0
6 5C0 5C0
-C0
6 C12 C24

. bV1
24 24

dV2
7C0
24

C23

2 4
Vo 2 C24 4

Vo

(a) (b) (c)

Fig. 7: The relationship between distributed parasitic capacitances and the six capacitor model of the transformer: a) an arbitrary
interleaved structure of a PT, b) the parasitic capacitance model of two overlapping layers of different windings relative to the terminals
of the transformer and c) transferring the same parasitic network to the terminals of the transformer.
 8

TABLE I: Equations for transferring the distributed capacitances to the transformer terminals

Capacitor T ransf er Equation

C0
 
C13 24 5ad + 7bd + 7ac + 5bc
C0
 
C14 24 12a + 12b − 5ad − 7bd − 7ac − 5bc
C0
 
C23 24 12c + 12d − 5ad − 7bd − 7ac − 5bc
C0
 
C24 24 24 + 5ad + 7bd + 7ac + 5bc − 12a − 12b − 12c − 12d
C0
 2 2

C12 24 8a + 8b + 8ab − 12a − 12b
C0
 2 2

C34 24 8c + 8d + 8cdb − 12c − 12d

and d which depend on the layers that are overlapping. The

transfer equations that are presented in Table I should be used (1 − k)C13 + C14 = kC23 →
to transfer the parasitic capacitance network of each overlapping
to the terminals of the transformer. Once that has been done for C0  
(1 − k) 5ad + 7bd + 7ac + 5bc
all of the intersections, there will be be six different groups of 24
capacitors that are connected between the transformer terminals. C0   (14)
+ 12a + 12b − 5ad − 7bd − 7ac − 5bc
Each group consists of the number of capacitors that are connected 24
in parallel. Under this condition, the equivalent capacitance of each C0  
=k 12c + 12d − 5ad − 7bd − 7ac − 5bc
group can be found by adding the capacitors of that group, as 24
all of the capacitors of each group are connected in parallel. For The solution for (14) is presented in (15).
example, the equivalent parasitic capacitance between terminal 1
and terminal 3 of transformer in Fig. 7 (b) is equal to sum of all of a + b = k[c + d] (15)
transferred parasitic capacitances that are connected between these
terminals. Therefore, in the end, there would be only six capacitors The final solution is very simple and elegant. Equation (15)
between the terminals of the transformer, which is equal to the six shows which layers can be overlapped to achieve zero CM noise
capacitance model of the transformer. generation as defined in (5). In other words, any two layers that
Although these equations may seem complex, they provide an satisfy (15) can be placed next to each other and their overlapping
elegant solution for satisfying the condition in (5) and achieving will not create any CM noise problems. These layers are called
no CM noise generation in PTs. These equations will be used in paired layers in this paper. In order to achieve zero CM noise
the next part to find a general winding method to achieve no CM generation, only paired layers should meet each other in the
noise generation in the transformer and solve the EMI problem of transformer structure. The use of layers that are not paired should
PTs. be avoided in the intersections. Therefore, the next step is to find
layers that satisfy (15). Fortunately, there is a simple solution to
this problem. The physical meaning of this solution is that if there
B. The Proposed Criteria for Winding Arrangement to are n1 turn in the primary and n2 turns in the secondary (n1 > n2 ),
the first n2 turns of the primary have a corresponding pair on the
Achieve No CM noise Generation secondary side. The remaining turns of the primary do not have a
In the previous part, a comprehensive parasitic capacitance pair on the secondary side and, therefore, they have to be avoided in
model for PTs was proposed that can be used to find winding the intersections. This explanation also works for step-up turn ratios
arrangements that satisfy (5) and achieve zero CM noise generation (n1 < n2 ). In this case, the first n1 turns of the secondary side
in PTs. This model is used in this part to find the condition that have a corresponding pair on the primary side. The remaining turns
leads to (5) and, consequently, to solve the CM noise problem on the secondary side do not have a pair and should be avoided in
caused by the PTs’ parasitic inter-winding capacitances. the intersections. This explanation is clearly illustrated in Fig. 8,
The requirements for achieving zero CM noise in the transform- which shows an arbitrary step-down transformer. It is clear that all
ers have been proposed in (5). According to the proposed parasitic of the paired layers satisfy (15). If only paired layers meet each
capacitance model in the previous section, while the capacitance other in the transformer, the conditions necessary for full CM noise
network of every two layers is the same, the overall effect of each cancellation (5) are achieved and the net CM current will be equal
overlapping on the six lumped capacitors depends on the positions to zero.
of the facing layers. Table I shows the relationship between the The above explanation is based on the lumped capacitance model
position of the layer and the effect on the lumped capacitors. These of the transformer. It is also interesting to employ a microscopic
equations can be used to find a proper winding arrangement that look to understand why the overlapping of the paired layers does
satisfies the CM noise cancellation requirement of (5). Substituting not lead to CM noise generation. A closer look at the paired layers
C13 , C14 , and C23 in (5) with their equivalent expressions in table reveals that they have the same dv/dt in their terminals. Fig. 9
I, the condition for achieving zero CM noise generation can be shows the condition when two paired layers overlap each other. For
found which is shown in (14). this condition, the total CM noise can be found by adding together
 9

Primary Winding

2Vs 2Vp

b=2/n1 a=3/n1
P(1) P(2) P(3) ... P(n2) ... P(n1-1) P(n1)

Paired Layers Layers with no Pair

P(1) P(2) P(3) ... P(n2)
d=2/n2 c=3/n2

2Vs

Secondary Winding

Fig. 8: Physical realization of the CM noise cancellation requirement. The number of paired layers is always equal to the number of
turns in the winding with fewer turns. This figure shows that paired layers which satisfy (15), have similar dv/dt on their terminals. In
order to satisfy (15) and achieve zero CM noise generation, only paired layers should overlap each other.

all the displacement currents. According to Fig. 9, currents i13 Considering the above explanations, the proposed solution for
and i24 are equal to zero, as the voltage across the corresponding CM noise can be explained in two different ways:
capacitors is zero. Since the other two currents are equal but flow 1) Through lumped Capacitance Circuit: With the proposed
in the opposite direction, they cancel each other out and so the solution, the displacement currents in the four inter-winding
total CM noise is equal to zero. Therefore, the overlapping of two parasitic capacitances of the transformer cancel each other
paired layers creates no CM noise. out and lead to net CM noise equal to zero.

v2
v1

a b

1 2
... P (m-1) P (m) P (m+1) ...

i23 = i14 i13 =0 i24 =0 i14 = i23

Paired Layers 5C0 7C0 7C0 5C0

24 24 24 24

... S (m-1) S (m) S (m+1) ...

v3
3 4 v4

a b

Fig. 9: Investigation of CM noise between paired layers. Paired layers have similar dv/dt between their terminals. This figure clearly
shows why no CM noise will be generated as a result overlapping of paired layers. Therefore, these layers can be placed next to each
other to achieve interleaved structures, without being worry about the CM noise.
 10

2) Through Distributed Capacitance Model: With the pro- P7

posed solution, the overlapping layers have the same dv/dt.
Therefore, no displacement current will be induced in the
distributed parasitic capacitances. As a result, there would
P6
P5
} Layers with no pair
on the secondary

be no CM current in the transformer (which can be called P4 S4

no CM noise generation). P3 S3
The above explanations also confirm the validity of the proposed Paired Layers
P2 S2
capacitance model as it provides results that are consistent with P1 S1
physical observation.
In this section, a detailed parasitic capacitance model for PTs (a)
has been proposed and has then been used to find a means to
achieve zero CM noise generation. Based on the model developed, P7 S1 P5
it has been shown that there are certain layers on the primary P4 P1 P1
and secondary sides that can be placed next to each other without S4 P5 S1
creating a CM noise problem. These layers are called paired layers, S3 P2 S2
and it has been proven that any structure that uses only paired layers P3 S2 P2
in the intersections of primary and secondary does not generate CM P6 S3 P6
noise. Using the proposed concept, it is possible to design highly P2 P3 P3
interleaved PTs for Flyback and Forward converters that not only S2 P6 S3
have low AC resistance and leakage inductance, but that do not S1 P4 S4
create CM noise despite their very large inter-winding capacitance. P1 S4 P4
P5 S4 P7
P4 P2
IV. I MPLEMENTATION OF THE P ROPOSED M ETHOD FOR
P6 S2
D IFFERENT T URN R ATIOS P3 S1
In the previous section, the concept of paired layers was S3 P3
proposed and it was proven analytically that the overlapping of S2 P5
the paired layers does not generate CM noise. While employing P2
the concept of paired layers leads to the generation of almost P7
zero CM noise, reducing AC resistance and leakage inductance P1
requires proper interleaved winding structures. In this section, S1
the concept of paired layers is employed along with interleaving
methods to develop PTs for Flyback and Forward converters that (b) (c) (d)
not only generate almost zero CM noise, but also have very low Fig. 10: Interleaved winding arrangement with low AC resis-
AC resistance and leakage inductance. tance/leakage inductance and no CM noise generation for a 7 : 4
The implementation of the proposed idea depends on the number PT: a) Paired layers in the primary and secondary windings. b)
of turns in the primary and secondary. For low voltage applications Windings realization using 8 layers for the primary and 4 layers
like telecoms, the number of required turns is not too high and, for the secondary. In this case, each turn is realized using one layer.
therefore, one-turn copper foils can be connected in series to make c) Windings realization using 12 layers for the primary and 8 layers
a complete winding. Under this condition, the proposed method can for the secondary. For this case, there are two layers for each turn of
be implemented easily, as all layers consist of one turn. However, the secondary to reduce resistance. Since each of these layers needs
if the input (or output) voltage is high, such as for adapters with a pair in primary, the corresponding turns in the primary are also
universal input voltages (85-265 AC), then a large number of realized using two layers. Parallel layers have the same name and
turns is required. Under this condition, it is not possible to use are indicated using small rectangles of the same color. d) Windings
a one turn copper foil for every layer, as the space in the core is realization using 10 layers for the primary and 6 layers for the
very limited and cannot accommodate many copper layers. In this secondary. Parallel layers have the same name and are indicated
case, a combination of PCB and one turn copper foils is used to using small rectangles of the same color. All of these arrangements
implement the proposed idea. In this section, both conditions are satisfy both the no CM noise generation criteria and the low AC
considered and a procedure for implementing the proposed idea resistance requirement.
for both scenarios is proposed. By following the procedure that is
presented for these transformers, high efficiency PTs with no CM
noise generation property can be designed.
connected in parallel (to reduce resistance), the number of layers
will be more than the number of turns. The focus of this part of
A. Implementation of the Proposed Method for PTs with the paper is on showing the applicability of the proposed CM noise
Small Number of Turns cancellation method to PTs with a small number of turns. In order
The number of turns is directly proportional to the applied to explain how the proposed idea can be applied to these PTs, the
voltage. For low voltage applications such as telecoms, there are idea is implemented for different turn ratios.
few turns and, therefore, windings can be made using one-turn Fig. 10 explains how the proposed CM noise cancellation
copper foils that are connected in series. In this situation, the method can be applied on a 7 : 4 transformer. Fig. 10 (a) shows
number of layers for each winding is at least equal to the number the paired layers on the primary and secondary sides and shows
of turns, as each layer consists of only one turn. If some layers are that there are four turns in the primary side that have a pair
 11

S1
S1
P1
P1
P4
P4
P2
P2
S2
S2
S3
S3
P6 P3

}
P3
Layers with no pair P6
P5 on the secondary P6
P3 P3
P4 S3
S3
S2 S2
P3 S3
P2 P2
P2 S2 P5 Secondary View
Paired Layers P5
P1 S1 P1 P1
S1 S1
Primary View
(a) (b) (c)

Fig. 11: Employing the proposed method for a 6 : 3 PT to achieve low AC resistance/leakage inductance and no CM noise generation at
the same time. a) The proposed structure, which has two layers for each secondary turn. The corresponding paired turns in the primary
are also realized using two layers in parallel. Parallel layers have the same name and are indicated using small rectangles of the same
color. b) A 3D model of the structure from both sides, and c) current densities in the transformer layers captured using FEA. As this
transformer has a highly interleaved structure, it has a very low leakage inductance of 130nH and ratio of AC to DC resistance equal
to (22mΩ/16mΩ). These values are valid for 200 kHz and for copper layers with the thickness equal to 0.125 mm.

in the secondary side. The remaining three turns of the primary 2) Legal intersections (overlapping between paired layers)
side do not have a pair in the secondary side and, therefore, should be used wisely to design interleaved structures that
they should be avoided in the intersections. Any structure that minimize leakage inductance and AC resistance.
satisfies this condition will lead to no generation of CM noise. 3) If parallel layers are used in the winding, they should have
Fig. 10 (b) shows one simple structure that satisfies this condition. similar positions in terms of proximity effect. Otherwise, one
As it is clear, only paired layers overlap with each other in this of the conductors will carry most of the current.
structure. In this structure, the seven layers of the primary are
Following the above criteria for PTs will lead to the creation
connected in series to make a seven-turn winding. The four layers
of high efficiency PTs that do no produce CM noise, in despite of
of the secondary are also connected in series to make a four-turn
their very large inter-winding capacitance. The above rules can be
secondary winding. Therefore, there are no parallel layers in this
applied to transformers with different turn ratios, and have no limi-
structure. However, if the core window can accommodate more
tation regarding turn ratio. Fig. 11 (a) shows an optimized winding
layers, it is desirable to add more layers in parallel and reduce the
arrangement which satisfy the no noise generation requirement and
resistance. Adding more layers also makes it possible to do more
low AC resistance for a 6:3 PT. In this figure, parallel layers are
interleaving and, consequently, to achieve better AC resistance and
also identified using small rectangles of the same color. In order
leakage inductance. Fig. 10 (c) shows the same transformer with
to illustrate the structure better, a three dimensional model of this
more layers. In this arrangement, the secondary has eight layers
structure is shown in Fig. 11 (b). From Figs. 11 (a) and (b), it is
(two layers per turn, connected in parallel). Since each layer of
clear that the above rules are applied on this structure. Therefore,
the secondary requires a pair in the primary side (to achieve noise
it is expected that this transformer generates no CM noise and at
cancellation), there should be eight paired layers in the primary.
the same time achieves low AC resistance and leakage inductance.
In other words, each of the first four turns of the primary (which
In order to confirm this claim, this transformer has been simulated
have a pair in the secondary) are made using two layers in parallel,
using Finite Element Analysis (FEA). Fig. 11 (c) shows the current
while the unpaired turns are realized using only one layer. The
density in different layers of the transformer and confirm that the
above explanation can be seen in Fig. 10 (c), as the layers with
current is shared equally between parallel layers. According to
same name are connected in parallel. In this figure, parallel layers
the FEA results, the total leakage inductance from primary side
are also identified using small rectangles of the same color. It is
is equal to 130 nH and the ratio of AC to DC resistance is equal
apparent that this arrangement meets the requirements for noise
to (22mΩ/16mΩ). A PT with this structure is prototyped in the
cancellation, as only paired layers overlap each other.
next section to validate the proposed method through experimental
The key requirements in implementing the proposed CM noise tests.
cancellation measures while at the same time minimizing AC
In this part, the proposed CM noise cancellation method has
resistance are as follows:
been implemented for PTs with few turns on each side. The typical
1) Only paired layers of primary and secondary should overlap application of these PTs are in low voltage Flyback and Forward
each other. The layers that do not have a pair in the other converters that are used in telecom industry. Windings in such PTs
winding should not be placed in the intersections. This can be realized using one-turn copper foils that are connected in
ensures that no CM noise will be generated. series. It has been shown that the proposed idea can be implemented
 12

easily for different turn ratios. In addition to implementing the B. Implementation of the Proposed Method for PTs with
proposed CM noise cancellation method, the criteria for achieving Large Number of Turns
low AC resistance and leakage inductance have been provided.
Therefore, the resulting PTs not only generate no CM noise but If the voltage level is higher, the number of turns should also
also have very low AC resistance and leakage inductance which increase to limit the flux density within the core. For instance, given
improve the performance and efficiency of Flyback and Forward the relatively small size of the cores that are used in low power
converters. transformers, the transformers that are used in Flyback adapters
with universal voltage range (85-260 Vac) should have a large

P36

}
P35
P24
.
P23
.
.
P5
} Layers with no pair
on the secondary
.
P6

P5
Layers with no pair
on the secondary

P4 S4 P4

P3 S3 P3 S3
Paired Layers
P2 S2 P2 S2
Paired Layers
P1 S1 P1 S1

S1

P1

S1 P4-P14

P2
P1

S2
P5-P14
S3
P2
P3

S2 P15-P25

S3 P3

S3
P3
S2
P15-P24
P2
P4
P26-P36

P1
S4
S1

(a) (b)

Fig. 12: Implementation of the proposed method for PTs with large turn ratios: Implementation of the method for a) a 24 : 4 PT and
b) a 36 : 3 PT. Both of these structures satisfy the requirement of no CM noise generation (as only paired layers overlap) and low AC
resistance criteria (placing parallel layers in symmetrical positions from both ends).
 13

number of turns in the primary side. If the number of turns in V. E XPERIMENTAL R ESULTS
a winding is high, it is not possible to make that winding using
one-turn copper foils. This is mainly due to the limited space in In order to confirm the validity of the proposed techniques,
the core, which cannot accommodate many layers. In addition, a extensive experimental tests have been done. Fig. 13 (a) shows the
large number of turns requires many terminations, which is not prototype of a PT that is realized using the proposed method. The
possible in the small width of the core. In this situation, spiral structure of this transformer is similar to Fig. 11. The specifications
PCB designs can facilitate the creation of many turns in one layer. of this transformer are also presented in table II. Since this
Since the proposed model only works if the paired layers of two transformer has a highly interleaved structure, the value of leakage
windings meet, for this case, the turns that have a pair on the other inductance and AC resistance is extremely low. On the other hand,
winding are realized using one turn copper foils, while the turns since primary and secondary overlap each other several times (as
with no pair are made using PCB. In other words, implementing a result of interleaving) and the overlapping layers are tightly
the proposed method for this condition requires a combination of placed next to each other, the value of parasitic capacitance is
one-turn layers and spiral PCBs. This will be explained in detail a very large value of 700 pF which is large enough to make
using two examples. serious EMI problems. However, since this transformer has been
manufactured using the proposed method, it will be shown that
Fig. 12 (a) shows the implementation of the proposed method this transformer generates extremely low levels of CM noise. In
for a PT with a 24 : 4 turn ratio. Under this condition, only the order to show the effectivity of the proposed method, the result
first four turns of the primary have a pair on the secondary side. of the proposed planar transformer with 700 pF inter-winding
The remaining 20 turns do not have a pair on the secondary and, capacitance is compared with a wire-wound transformer which
therefore, should not overlap with the secondary winding. In order only has parasitic capacitance of 10 pF (70 times less). The
to implement the proposed idea, the first four turns of the primary specifications of the wire-wound transformer are presented in table
are realized using one-turn layers. These four layers can overlap II. In this part, we will show that the proposed PT generates
with their pair on the secondary side. The remaining 20 turns are significantly less CM noise than this transformer, although its
realized using two double layer PCBs. Each PCB has 10 turns parasitic capacitance is 70 times more.
(five on each side), and PCBs are placed between the layers of The first test intends to separate and visualize the common mode
the primary side in order to hide them from secondary winding. current caused by the transformer’s inter-winding capacitance, and
On the other hand, the secondary consists of four one turn copper proves that the proposed PTs generate very little CM noise. Since
foils that are connected in series. Therefore, only paired layers meet the measurements made using the standard method of measuring
each other in the structure of Fig. 12 (a) and so, this structure does conducted mode noise at the input side cannot separate the noise
not generate any CM noise. of different elements, the circuit that is shown in Fig. 13 (b) is
Fig. 12 (b) shows the implementation of the proposed method used as a test circuit for observing only the CM noise that is
for a PT with a 36 : 3 turn ratio. The first three turns of the generated owing to the inter-winding capacitance of the transformer
primary side have a pair on the secondary. These turns are realized [16]. As there is one terminal with static voltage and another
using one turn copper foils, and the remaining 33 turns are made terminal with swinging voltage, the transformer’s voltage is similar
using PCBs. Each PCB has 11 turns and PCBs have been placed to that in Flyback and Forward converters. Therefore, transformer’s
between the layers of the primary so as not to overlap with the behavior in terms of CM noise generation is similar to its behavior
secondary winding. Examining the structure that is proposed in when used in Flyback and Forward converters There are two
Fig. 12 (b) confirms that only paired layers meet each other in this sources of CM noise in Fig. 14 (b). The first one is the parasitic
structure. In addition, the parallel layers in the secondary side are capacitance between the drain and heatsink of the switch. Another
placed symmetrically from both ends, which ensures even current source of CM noise is the parasitic capacitance of transformer.
sharing and low AC resistance. Therefore, this structure also does Since the secondary side is open, no current is induced in the
not create CM noise and provides very low AC resistance and secondary winding through magnetic coupling and the current
leakage inductance. at the secondary side consist of only CM noise currents of the
In this section, the concept of paired layers has been employed transformer. As is shown in Fig. 14 (b), the CM noise currents of
along with interleaving methods to achieve winding structures with the switch and transformer propagate in the circuit and return to
very low AC resistance/leakage inductance and close to zero CM their source through parasitic capacitances. As mentioned above,
noise generation. It has been shown that the proposed solution does the CM noise that is measured at the input includes all of the
not have any limitation regarding turn ratio, and can be applied noise, and the CM noise of the transformer cannot be examined
to transformers with both large and small numbers of turns. If alone. In order to separate the transformer CM noise, a resistor
the number of turns is small, the solution can be implemented
using one-turn copper foil layers. If the number of turns is large, a
TABLE II: Experimental Platform Prameters
combination of one-turn copper foils and two layers PCBs can be
used to implement the idea. Therefore, the proposed method can Flyback Circuit Planar Transformer Wire-Wound
be implemented for any turn ratio. The guidelines presented in this
section are general and can be used to design interleaved structures Vi n 72V Np /Ns 6/3 Np /Ns 6/3
that result in no generation of CM noise for any turn ratio. While Vo 24V Copper 0.125 mm Wire Litz
implementing the proposed method adds a bit of complexity to the
design of the PT structure, the benefits of employing the method are P 100W Core ER 32/6/25 Core RM 12
very significant and make using the method worthwhile. Once the f 150 kHz Cinter 700 pF Cinter 10 pF
winding structure is found for a given turn ratio, the implementation Lm 42µH Llk−p 130 nH Lleak 1µH
of the method is simple and can be done either using multi-layer
PCBs or copper stamps. RAC−p 23 mΩ
 14

S1 C14 i14 High Impedance Path-

Most of Trans CM noise
C13 i13 ReturnsThrough Resistor

1 3

Vd
2 i24 4
S2 C24
i23 i≈0 i≈0
C23 iCM-tr
Cp` Cp
Csw +
VR 10 kΩ
iCM-sw
-
Cps=700 pF Cps=10 pF

Low Impedance Path-

Voltage over R visualizes
transformer CM noise

(a) (b)
Fig. 13: a) The prototype of the proposed PT along with a traditional wire-wound transformer. The structure of PT has been shown in Fig.
11. The proposed PT has significantly smaller AC resistance and leakage inductance, but at the same time its inter-winding capacitance
is 70 times that of the wire-wound transformer. b) The circuit that is used to signify the CM currents caused by the inter-winding
capacitance.

Wire-wound with 10pF inter-winding Cap The proposed Planar Transformer with 700pF inter-winding Cap

100 100
Switching Moment V/div Switching Moment V/div

VR= R*ICM
10 10
VR= R*ICM V/div V/div

CM currents Very low CM currents

(a) (b)
Fig. 14: Waveforms of the circuit of Fig. 13 (b) with different transformers. The DC bus voltage and the switching frequency are equal
to 100V and 200kHz, respectively. Output voltage of the inverter (ch1), Voltage across the resistor between the primary and secondary
(ch2). Waveforms with a) the traditional wire-wound transformer and b) the proposed PT. Comparing the results shows that, while the
proposed PT has a very large inter-winding capacitance of 700pF , it produces significantly lower CM current than does the wire-wound
transformer, which has 70 times less inter-winding capacitance.

has been added between the quiet point of the secondary and the proposed PT with a very large inter-winding capacitance of 700
earth. Since the impedance of this resistor is much less than the pF generates extremely low levels of CM noise (close to zero).
impedance of parasitic capacitances between the secondary nodes In other words, the proposed method enables the use of highly
and the earth, most of the transformer CM noise currents complete interleaved structures for PTs that minimize AC resistance and
the path through this resistor. Under this condition, the resistor leakage inductance, while simultaneously generating almost zero
voltage is a representation of the transformer’s CM noise. Figs. 14 CM noise, despite having large inter-winding capacitances.
(a) and (b) show the voltage across the resistor with the wire-wound
For the second test, the proposed PT has been employed in a
transformer and the PT employed in the circuit, respectively. Since
Flyback power converter to confirm the superiority of the proposed
the wire-wound transformer has significantly less inter-winding
method in terms of noise reduction. The specification of the
capacitance (70 times less), the general sense is that it will generate
converter is presented in table II. Line Impedance Stabilization
considerably lower CM noise current. However, the experimental
Networks (LISN) have been placed at the input of the converter and
results that are presented in Fig. 14 (a) and (b) show that the
the total conducted mode noise have been observed with a spectrum
 15

100 100
V/div V/div
Higher Voltage stress caused by leakage Inductance (1 uH) Low Voltage stress as a result of low leakage Inductance of PT (130 nH)

5 5
A/div A/div

10
V/div
(a) (b)

Fig. 15: Waveforms of the Flyback converter with different transformers. Switch voltage (Ch1) and primary current (Ch2). Waveforms
with a) the wire-wound transformer and b) with the proposed PT. Using a highly interleaved winding structure, the leakage inductance
of the proposed PT is very low, which has led to a significant reduction in voltage spike on the switch.

110 db/μV 110 db/μV

90 db/μV 90 db/μV

10 db/μV 10 db/μV

Although having just 10 pF inter-winding cap,

the generated noise of wire-wound transformer 8-10 dB less noise in despite of 700 pF inter-winding
is more than the proposed PT with 700 pF cap. Cap using the proposed winding method.
10 db/μV 10 db/μV
150 kHz 30 MHz 150 kHz 30 MHz

(a) (b)

Fig. 16: The spectrum of conducted mode noise of the Flyback with different transformers. Both tests have been done under the same
conditions but using different transformers. Noise spectrum with a) wire-wound transformer, and b) the proposed PT. A comparison of
the results shows that the proposed PT with a very large parasitic capacitance of 700 pF generates less noise than does the wire-wound
transformer with only 10 pF parasitic capacitance. As explained in the paper, since only paired layers that have similar dv/dt overlap
each other, no CM noise will be generated in the PT, even though it has a very large inter-winding capacitance.

analyzer. The conditions of both tests are the same and the same right configuration is not used for the converter, the overlapping
Flyback converter with RCD snubber is used. Figs. 15 (a) and (b) layers have voltage waveforms that change in opposite directions
show the waveforms of the converter with PT and the wire-wound and therefore, they generate significant levels of CM noise. In order
transformer, respectively. Due to large leakage inductance of wire- to show the effect of configuration, the same PT has been used in
wound transformer, the switch voltage has a considerably larger both configurations. Figs. 17 (a) and (b) show the spectrum of
spike. On the other hand, the proposed PT has a very small leakage conducted noise for wrong and right configurations, respectively.
inductance which is the result of highly interleaved structure and It is clear that noise for right configuration is significantly lower
leads to less voltage spike on the switch. Figs. 16 (a) and (b) show than the other configuration which is another verification of the
the spectrum of conducted noise with wire-wound transformer and proposed concept and method. As it was mentioned in the previous
the proposed PT, respectively. These figures show that while the sections, using the right configuration of the converter is essential
proposed PT has a very high parasitic capacitance of 700pF , to apply the proposed method.
it produces less noise than does a traditional transformer whose
parasitic capacitance is 70 times less. These results show that the Finally, as it was explained in the paper, the winding method
proposed method has resolved the trade-off between low leakage relies on the proposed concept of paired layers which tries to
inductance and the noise due to inter-winding capacitance, leading overlap the layers that have similar voltage waveforms (and so
to a new generation of PTs that have low leakage inductance and similar dv/dt)) to avoid generation of CM noise. Therefore, it
extremely low noise generation at the same time. is also interesting to compare the voltage of paired layers to
confirm the concept of paired layers and show why the proposed
As it was mentioned in the section II, the proposed method is method leads to no generation of CM noise. Fig. 18 (a) shows
applicable only if the right configuration of Flyback and Forward the voltage distribution along the primary winding. As it can be
converters are used. Under this condition and using the proposed seen from Fig. 18 (a), the first pin of the primary has a static
winding method, the overlapping layers have similar voltage wave- voltage waveform which is not affected by the switching of the
forms which leads to no generation of CM noise. However, if the converter. The amplitude of voltage swinging increases after each
 16

110 db/μV 110 db/μV

90 db/μV 90 db/μV

10 db/μV 10 db/μV

10 dB more noise as a result of

using wrong configuration
10 db/μV
10 db/μV
150 kHz 30 MHz 150
150 kHz
kHz 30 MHz

(a) (b)

Fig. 17: The spectrum of the conducted mode noise of the Flyback with different configurations and the same PT. Noise Spectrum with
a) wrong configuration and b) right configuration. This figure clearly shows that the same transformer can produce significant levels of
CM noise if the right configuration is not used. This figure is another proof of the value of the proposed method and concept.

Static Point Layers that have pair

on the secondary side
and can overlap with
their pairs.

Layers with no pair

Ch1 which do not overlap
Ch2 100
with secondary layers.
Ch3 V/div
Ch4
Ch5
Ch6

Layers with no pair

(a)

Paired Layers

Ch6 Ch5 Ch4 SE Ch1 Ch2 Ch3 Ch1

The proof that shows Paired
layers have similar voltage
Ch4 distribution. Overlapping of
such layers does not make
CM noise.

Ch2

Ch5

100

}
V/div
Layers with Ch3
no pair on the
secondary Ch6

(b)

Fig. 18: Validating the concept of paired layers through experimental tests. a) Ch1 to Ch6 show the voltage distribution over the primary
winding. As was explained in the paper, each of the first three turns of the primary have a pair on the secondary side (which has a
similar dv/dt). The remaining three turns do not have a pair and are avoided in the intersections of the primary and secondary. b) Ch1
to Ch3 and Ch4 to Ch6 are the voltage distribution over the first three turns of the primary and secondary, respectively. This figure
clearly shows that the first turns of the primary and the secondary have similar dv/dt and, therefore, are paired. The same is true for
the second and third turns. As these layers overlap, no CM noise is produced despite the large inter-winding capacitance.
 17

turn and reaches to its maximum after the last turn. Since this is and AC resistance/leakage inductance, and enables designers to
a 6:3 transformer, as it was explained in the paper, the first three design high-efficiency and CM noise free PTs for Flyback and
turns of the primary can be paired with the secondary layers. The Forward converters.
remaining three layers do not have a pair on the secondary side
and, therefore, should not overlap with secondary layers (structure
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 18

[18] Q. Chen and W. Chen, “An evaluation method of transformer behav- Martin Ordonez (S02M09) was born in
iors on the suppression of common-mode conduction noise in switch Neuquen, Argentina. He received the Ing. de-
mode power supply,” in Proc. CSEE., vol. 32, no. 18, pp. 73-79, Jun. gree in electronics engineering from the National
2012. Technological University, Cordoba, Argentina, in
[19] Y. Chu and S. Wang, “A Generalized Common-Mode Current Can- 2003, and the M.Eng. and Ph.D. degrees in elec-
cellation Approach for Power Converters,” IEEE Trans. Ind. Electron., trical engineering from the Memorial University
vol.62, no.7, pp.4130-4140, July 2015. of Newfoundland (MUN), St. Johns, NL, Canada,
[20] L. Xie, X. Ruan, Q. Ji, and Z. Ye, “Shielding-cancellation technique in 2006 and 2009, respectively.
for suppressing common mode EMI in isolated power converters,” He is currently an Assistant Professor with the
IEEE Trans. Ind. Electron., vol. 62, no. 5, pp. 2814-2822, May 2015. Department of Electrical and Computer Engineer-
[21] H. Chen and J. Xiao, “Determination of Transformer Shielding Foil ing, University of British Columbia, Vancouver,
Structure for Suppressing Common-Mode Noise in Flyback Converter, BC, Canada. He is also a Canada Research Chair in Power Converters
” in IEEE Trans. Mag, Early Access. for Renewable Energy Systems, as well as an Adjunct Professor with
[22] J. Lu and F. Dawson, “Characterizations of high frequency planar Simon Fraser University, Burnaby, BC, Canada, and MUN. His industrial
transformer with a novel comb-shaped shield,” IEEE Trans. Magnetics., experience in power conversion includes research and development at
vol. 47, no. 10, pp. 4493-4496, Oct. 2011. Xantrex Technology Inc./Elgar Electronics Corp. (now AMETEK Pro-
[23] D. Fu, P. Kong, S. Wang, F.C. Lee, M. Xu, “Analysis and Suppression grammable Power in San Diego, California), Deep-Ing Electronica de
of Conducted EMI Emissions for Front-end LLC Resonant DC/DC Potencia (Rosario, Argentina), and TRV Dispositivos (Cordoba, Argentina).
Converters,” in in Proc. IEEE PESC., pp. 1144-1150, 2008 With the support of industrial funds and the Natural Sciences and Engi-
[24] Y. P. Chan, M. H. Pong, N. K. Poon, and C. P. Liu, “Effective neering Research Council, he has contributed to more than 60 publications
switching mode power supplies common mode noise cancellation and R&D reports.
technique with zero equipotential transformer models,” in Proc. IEEE Dr. Ordonez is an Associate Editor of the IEEE TRANSACTIONS
Appl. Power Electron. Conf. (APEC), pp. 571-574, Oct. 2010. ON POWER ELECTRONICS, serves on several IEEE committees, and
[25] Y.P. Chan, B. M. H. Pong, N. K. Poon, J. C. P. Liu “Common-Mode reviews widely for IEEE/IET journals and international conferences. He
Noise Cancellation by an Antiphase Winding in Multilayer Isolated was awarded the David Dunsiger Award for Excellence in the Faculty
Planar Transformer,” IEEE Trans. on Elec. Compat, vol.56, no.1, pp. of Engineering and Applied Science (2009) and the Chancellors Graduate
67-73, Feb 2014. Award/Birks Graduate Medal (2006), and became a Fellow of the School
[26] P. Chen, H. Zhong, Z. Qian, Z. Lu, “The passive EMI cancellation of Graduate Studies, MUN.
effects of Y capacitor and CM model of transformers used in switching
mode power supplies (SMPS),” in IEEE 35th Annual Power Electronics
Specialists Conference, vol 2, pp. 1076-1079, 20-25 June 2004
[27] P. Kong and F. C. Lee, “Transformer structure and its effects on
common mode EMI noise in isolated power converters” in in Proc.
IEEE APEC,, 2010, pp. 1424-1429.
[28] X. Yang, D. Zhang, X. Li, W. Chen, W. Hu, “Conducted EMI
Mitigation Schemes in Isolated Switching Mode Power Supply without
the Need of a Y-capacitor,” IEEE Trans. Power. Electron., Early access,
June 2016
[29] Y. Bai1, W. Chen1, Ruirui He1, D. Zhang2, X. Yang1, “EMI Noise
Cancelation by Optimizing Transformer Design without Need for
the Traditional Y-Capacitor” in Proc. 29th Annu. IEEE Appl. Power
Electron. Conf, Mar. 2016, pp. 566-571
[30] Y. Yang, D. Huang, F. C. Lee, and Q. Li, “Analysis and reduction
of common mode EMI noise for resonant converters,” in Proc. IEEE
Navid Shafiei (S11) was born in Isfahan, Iran. He
Appl. Power Electron. Conf, Mar. 2014, pp. 766-771
received the B.S. degree in electrical engineering
[31] F. Blache, J. P. Keradec and B. Cogitore, “Stray capacitance of two
from Kashan University, Kashan, Iran, in 2005,
winding transformer: equivalent circuit, measurments, calculation and
and the M.S. degree in electrical engineering from
Lowering,” in IEEE Ind. application Society Annual Meeting, Vol. 2,
Islamic Azad University, Najafabad, Iran, in 2011.
1994, pp l2ll-1217.
He is currently working toward the Ph.D. degree
at the University of British Columbia, Vancouver,
BC, Canada. He was a Technical Designer in the
Information and Communication Technology In-
stitute, Isfahan University of Technology, Isfahan,
Iran, from 2005 to 2013, where he was involved
Mohammad Ali Saket (S’15) was born in in design and implementation of resonant converters. His current research
Tehran, Iran. He received the B.Sc. degree in interests include resonant converters and their application in pure electric
Electrical Engineering from the Amirkabir Uni- vehicles.
versity of Technology, Tehran, Iran, in 2009, and
the M.Sc. degree in Power Electronics from Sharif
University of Technology, Tehran, Iran, in 2011.
He is currently a PhD student at the University of
British Columbia (UBC), Vancouver, BC, Canada.
His research interests include planar magnetics,
conducted electromagnetic interference, resonant
converters, and wireless power transfer. He is cur-
rently working toward high-efficiency and low parasitic integrated magnetic
structures for resonant DC-DC converters.

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