N-1

To optimize the MMU sequence for non-memory instructions (e.g., ADD,

SUB), the (1,0) phase is skipped since address translation is unnecessary.
This reduces the sequence to: (0,0) → (0,1) → (1,1)
The control signals Ein and phasein are recalculated as follows:
Ein Calculation:
Ein(h,eev) = ¬jisr(h,eev) ∧ (¬h.mode[0] ∧ ¬h.E ∨ (h.mode[0] ∧ (¬ls(h) ∧
h.phase ∨ ls(h) ∧ h.E ⊕ h.phase)))
Substituting values:

Ein(h,eev) = ¬0 ∧ (¬1 ∧ ¬0 ∨ (1 ∧ (¬1 ∧ 0 ∨ 1 ∧ 0 ⊕ 0)))

= 1 ∧ (0 ∨ (1 ∧ (0 ∨ 1 ∧ 0)))
= 1 ∧ (0 ∨ (1 ∧ 0))
=1∧0
=0

Result: Ein = 0, meaning the (1,0) phase is skipped.

1. phasein Calculation:
phasein(h,eev) = ¬jisr(h,eev) ∧ (¬h.mode[0] ∨ (¬ls(h) ∧ h.phase ∨ ls(h) ∧
¬h.phase))
Substituting values:
phasein(h,eev) = ¬0 ∧ (¬1 ∨ (¬1 ∧ 0 ∨ 1 ∧ ¬0))
= 1 ∧ (0 ∨ (0 ∨ 1 ∧ 1))
= 1 ∧ (0 ∨ 1)
=1

Result: phasein = 1, allowing the sequence to directly transition to (1,1).

Conclusion:
For non-memory instructions, the updated MMU sequence is:
(0,0) → (0,1) → (1,1)
This reduces the execution time for these instructions.

Skipping the (1,0) phase improves performance for non-memory

instructions by saving one clock cycle, while memory instructions still
follow the full sequence (0,0) → (0,1) → (1,0) → (1,1) to ensure proper
address translation.

This ensures that address translation is performed accurately for load

and store instructions, maintaining proper memory access.

+--------------------+
 | Instruction Decoder|

+--------------------+

+-------------+-------------------------+

| |

+----------+ +----------+

| Opcode | | Control |

| Checker | | Logic |

+----------+ +----------+

| |

| |

| +--------------------+

| | Generate Signals |

+--------------------------->| Ein & phasein |

+--------------------+

+-----------------------------+-----------+

| |

+-----------------------+ +-----------------------+

| State Transition | | MMU Translation |

| Logic (0,0 → 0,1 → 1,1)| | Logic (LOAD/STORE) |

+-----------------------+ +-----------------------+
 N-2
The timer consists of:
1. A 64-bit counter that decrements each clock cycle when cmsr[0] =
1.
2. A 32-bit CMSR (Command and Status Register) that includes:
o cmsr[0]: Enables ticking.
o cmsr[1]: Becomes 1 to signal an interrupt when the counter
reaches 0.
Logical Behavior:
• Counter Update:
counter_next = {
counter - 1, if cmsr[0] = 1 ∧ counter > 0
counter, if cmsr[0] = 0 ∨ counter = 0
}
• Interrupt Logic:
cmsr[1] = {
1, if counter = 0
cmsr[1], if not cleared by a write to cmsr
}
Edge Cases:
• If the counter is initialized to zero, the interrupt (cmsr[1]) is
activated immediately, and ticking does not start.
• In multi-timer systems, priority encoding ensures only the highest-
priority interrupt is processed first.
Conclusion:
The timer functions as a periodic event handler, generating
interrupts when the counter reaches zero and allowing precise
system control.

N-3
To implement the timer, I designed the following components:
1. CMSR: Controls the ticking and stores the interrupt flag.
2. 64-bit Counter: Decrements each cycle when enabled by cmsr[0].
3. Comparator: Detects when the counter reaches zero and sets
cmsr[1].

+--------------------+

| CMSR |

| Command & Status |

| Register |
 +--------------------+

+----------+----------+

| |

+------------+ +------------------+

| Comparator | | 64-bit Counter |

| (Zero Test)| | (Decrement Logic)|

+------------+ +------------------+

| |

| +--------------------+

| | Current Count |

| | Value Output |

+---------------------------------+

+------------------+

| Processor Bus |

| (Memory-Mapped) |

+------------------+

SAME THING JUST LITTLE MORE DETAILS

The timer components are connected to the processor via a memory-
mapped interface, allowing the CMSR and counter values to be
accessed and updated by software instructions.

+---------------------------+

cmsr[0] ----->| CMSR Register |

cmsr[1] <-----| (Ticking, Interrupt) |

Write --------| |

+---------------------------+

+-----------------------------------+

| 64-bit Counter |

| - Decrement Logic |

| - Flip-Flops for Storage |

+-----------------------------------+

+--------------------+

| Comparator |

| (Checks counter == 0) |

+--------------------+
 |

+--------------------+--------------------+

| |

cmsr[1] <-------------------------------- Interrupt (Active = 1)

• The counter decrements on the rising edge of the clock signal.

• Interrupts are synchronized using edge-triggered flip-flops to ensure
accurate timing

N-4
The issue arises because the specification doesn’t prevent harmful side
effects, like a timer-triggered bomb destroying the disk. This happens
because the system lacks rules defining how interrupts interact with
external devices.
Proposed Fix:
Add the following rule to the specification:
"Interrupt signals generated by the timer must not cause undefined or
destructive behavior in external devices. All timer interactions must
follow predefined, safe, and predictable behavior."
Mitigation Strategy:
1. Restrict timer interrupts to legitimate tasks (e.g., scheduling).
 2. Add safeguards in external devices to ignore undefined or harmful
commands triggered by interrupts.
3. Simulate edge cases to verify the system adheres to the updated
rules.
Testing ensures that these rules effectively prevent harmful behaviors in
edge cases, such as simultaneous interrupts or unexpected timer
triggers.

N-5
To handle the violations:
1. No Branch or Jump in Delay Slots:
o A Delay Slot Checker ensures no branch or jump is in delay
slots.
o If detected, an interrupt is raised.
2. No Fetch from Recently Written Addresses:
o A FIFO Queue tracks the last write address.
o Comparators check the next 3 fetch addresses against the
stored address.
o If a match occurs, an interrupt is triggered.
3. The Delay Slot Checker continuously monitors delay slot
instructions to prevent logical errors.
4. The Memory Conflict Checker ensures data consistency by
avoiding fetches from recently written addresses.

+---------------------------+

| Instruction Decoder |

+---------------------------+

+----------------+--------------------------+

| |

+----------------+ +----------------+

| Delay Slot | | Memory Conflict|

| Checker Logic | | Checker Logic |

+----------------+ +----------------+

| |

V V

+--------------------+ +--------------------+

| Raise Interrupt if | | Raise Interrupt if |

| Branch in Delay | | Fetch == Write Addr|

| Slot Detected | | Within 3 Cycles |

+--------------------+ +--------------------+
Interrupts generated by these checks ensure immediate correction of
violations, maintaining program correctness and system stability.