Lecture 6

Sequential Logic Circuits

Sequential circuits consist of a combinational circuit to
which storage elements are connected to form a
feedback path. The sequential circuit receives binary
information from external inputs that, together with the
present state of the storage elements, determine the
binary value of the outputs.

SET means that the Q output is HIGH. RESET means that

the Q output is LOW.

Latches/ Flipflops
The S-R (SET-RESET) Latch
The main difference between latches and flip-flops is in
the method used for changing their state. Flip Flops are
edge-triggered and latches are level-triggered.
A latch is a temporary storage device, where the
output of each gate is connected to an input of the
opposite gate.
The Gated S-R Latch
A gated latch requires an enable input, EN (sometimes
designated as G). The latch will not change until EN is
HIGH; but as long as it remains HIGH, the output is
controlled by the state of the S and R inputs.

The edge-triggered D flip-flop

The dynamic input indicator means the flip-flop
changes state only on the edge of a clock pulse.
The Gated D Latch
Another type of gated latch is called the D latch. It
differs from the S-R latch because it has only one input
in addition to EN. This input is called the D (data) input.
When the D input is HIGH and the EN input is HIGH, the
latch will set. When the D input is LOW and EN is HIGH,
the latch will reset. Stated another way, the output Q
follows the input D when EN is HIGH.
The D input of the D flip-flop is a synchronous input Most integrated circuit flip-flops
because data on the input are transferred to the flip- also have asynchronous inputs.
flop’s output only on the triggering edge of the clock These are inputs that affect the
pulse. Q follows D at the triggering edge of the clock. state of the flip-flop independent
of the clock. They are normally
labeled preset (PRE) and clear
(CLR). An active level on the
preset input will set the flip-flop,
and an active level on the clear
input will reset it.

The JK Flip-Flop
The J and K inputs of the J-K flip-flop are synchronous
inputs because data are transferred to the flip-flop’s
output only on the triggering edge of the clock pulse.

The operation and truth table for a negative edge-

triggered D flip-flop are the same as those for a
positive edge-triggered device except that the falling
edge of the clock pulse is the triggering edge.
 Propagation Delay Time
The performance, operating requirements, and
limitations of flip-flops are specified by several
operating characteristics found on the data sheet.
Propagation Delay Times
A propagation delay time is the interval of time
required after an input signal has been applied for the
resulting output change to occur.
The T flip-flop
A J-K flip-flop connected for toggle operation is called
a T flip-flop.

In the toggle mode, a T flip-flop changes state on

every clock pulse.
Flip-Flop Applications
Parallel Data Storage
A common requirement in digital systems is to store
several bits of data from parallel lines simultaneously in
a group of flip-flops.

This operation is illustrated in following figure using four

flip-flops. Each of the four parallel data lines is
connected to the D input of a D flip-flop. The clock
inputs of the flip-flops are connected together, so that
each flip-flop is triggered synchronously by the same
clock pulse.

In this example, positive edge-triggered flip-flops are

used, so the data on the D inputs are stored
simultaneously by the flip-flops on the positive edge of
the clock, as indicated in the timing diagram.

Also, the asynchronous reset (R) inputs are connected

to a common CLR line, which initially resets all the flip-
flops.
Frequency Division Further division of a clock frequency can be achieved
by using the output of one flipflop as the clock input to
Another application of a flip-flop is dividing (reducing) a second flip-flop, as shown below. The frequency of
the frequency of a periodic waveform. the QA output is divided by 2 by flip-flop B. The QB
When a pulse waveform is applied to the clock input output is, therefore, one-fourth the frequency of the
of a D or J-K flip-flop that is connected to toggle (D = original clock input. Propagation delay times are not
Q or J = K = 1), the Q output is a square wave with shown on the timing diagrams.
one-half the frequency of the clock input.
Thus, a single flip-flop can be applied as a divide-by-2
device, as is illustrated below.
This results in an output that changes at half the
frequency of the clock waveform.
Counting
Another important application of flip-flops is in digital
counters.

Negative edge-triggered J-K flip-flops are used for

illustration. Both flip-flops are initially RESET. Flip-flop A
toggles on the negative-going transition of each clock
pulse. The Q output of flip-flop A clocks flip-flop B, so
each time QA makes a HIGH-to-LOW transition, flip-flop
B toggles.

If we take QA as the least significant bit, a 2-bit

sequence is produced as the flip-flops are clocked.
This binary sequence repeats every four clock pulses,
as shown in the timing diagram.

Thus, the flip-flops are counting in sequence from 0 to 3

(00, 01, 10, 11) and then recycling back to 0 to begin
the sequence again.
Lecture 7
 Shift Registers
Shift registers consist of arrangements of flip-flops and
are important in applications involving the storage and
transfer of data in a digital system.

Registers
A register is a digital circuit with two basic functions:
data storage and data movement. A 1 is applied to
the data input of a D flip-flop as shown in the figure,
and a clock pulse is applied that stores the 1 by setting
the flip-flop. When the 1 on the input is removed, the
The storage capacity of a register is the total number
flip-flop remains in the SET state, thereby storing the 1.
of bits (1s and 0s) of digital data it can retain.
A similar procedure applies to the storage of a 0 by
resetting the flip-flop. Each stage (flip-flop) in a shift register represents one
bit of storage capacity; therefore, the number of
stages in a register determines its storage capacity.
The shift capability of a register permits the movement
of data from stage to stage within the register or into
or out of the register upon application of clock pulses.
The 7 figures in the next slide illustrate the types of data
movement in shift registers. The block represents any
arbitrary 4-bit register, and the arrows indicate the
direction of data movement.
Types of Shift Register Data I/Os
Serial In/Serial Out Shift Registers
The serial in/serial out shift register accepts data
serially—that is, one bit at a time on a single line.
It produces the stored information on its output also in
serial form.
The following is a 4-bit device implemented with D flip-
flops. With four stages, this register can store up to four
bits of data.
The table below shows the entry of the four bits 1010 shift register (SRG)
into the register in the previous slide, beginning with with an 8-bit
the least significant bit. The register is initially clear. capacity.

Serial In/Parallel Out Shift Registers

Data bits are entered
serially (least-significant
bit first) into a serial
in/parallel out shift
register in the same manner
as in serial in/serial out
If you want to get the data out of the register, the bits registers, but taken out
must be shifted out serially to the Q3 output. differently.

A logic block symbol for an 8-bit serial in/serial out shift

register is designated by “SRG 8”, which indicates a
Parallel In/Serial Out Shift Registers
For a register with parallel data inputs, the bits are Notice that FF0 has a single AND to disable the parallel
entered simultaneously into their respective stages on input, D0. It does not require an AND/OR arrangement
parallel lines rather than on a bit-by-bit basis on one because there is no serial data in.
line as with serial data inputs.
Parallel In/Parallel Out Shift Registers
Bidirectional Shift Registers
Parallel entry and parallel output of data have been
discussed. A bidirectional shift register is one in which the data
can be shifted either left or right. It can be
The parallel in/parallel out register employs both implemented by using gating logic that enables the
methods. Immediately following the simultaneous entry transfer of a data bit from one stage to the next stage
of all data bits, the bits appear on the parallel outputs. to the right or to the left, depending on the level of a
control line.
A 4-bit bidirectional shift register is shown in the figure. enables data bits inside the register to be shifted to the
A HIGH on the RIGHT/LEFT control input allows data bits left. An examination of the gating logic will make the
inside the register to be shifted to the right, and a LOW operation apparent.
Shift Register Counters
A shift register counter is basically a shift register with
the serial output connected back to the serial input to
produce special sequences.
These devices are often classified as counters because
they exhibit a specified sequence of states.
Two of the most common types of shift register
counters are the Johnson counter and the ring
counter.
The Johnson Counter
In a Johnson counter the complement of the output of
the last flip-flop is connected back to the D input of
the first flip-flop (it can be implemented with other
types of flip-flops as well). If the counter starts at 0, this
feedback arrangement produces a characteristic
sequence of states, as shown in the first table for a 4-
bit device and in the second for a 5-bit device. Notice
that the 4-bit sequence has a total of eight states, or
bit patterns, and that the 5-bit sequence has a total of
ten states. In general, a Johnson counter will produce
a modulus (number of states) of 2n, where n is the
number of stages in the counter.
The implementation of the 4-stage and 5-stage
Johnson counters is very straightforward and is the
same regardless of the number of stages.
The Ring Counter
A ring counter utilizes one flip-
flop for each state in its
sequence.
It has the advantage that
decoding gates are not
required. In the case of a 10-
bit ring counter, there is a
unique output for each
decimal digit.
Lecture 8
 Counters
Finite State Machines
A state machine is a sequential circuit having a limited
(finite) number of states occurring in a prescribed
order. A counter is an example of a state machine; the
number of states is called the modulus. Two basic
types of state machines are the Moore and the Mealy.
The Moore state machine is one where the outputs
depend only on the present state.
The Mealy state machine is one where the outputs A Moore state machine consists of combinational
depend on both the present state and on the inputs. logic that determines the sequence and memory (flip-
Both types have a timing input (clock) that is not flops). In the Moore machine, the combinational logic
considered a controlling input. is a gate array with outputs that determine the next
state of the flip-flops in the memory. There may or may
not be inputs to the combinational logic. There may
also be output combinational logic, such as a
decoder. If there is an input(s), it does not affect the
outputs because they always correspond to and are
dependent only on the present state of the memory.
For the Mealy machine, the present state affects the
outputs, just as in the Moore machine; but in addition,
the inputs also affect the outputs. The outputs come
directly from the combinational logic, not the memory.
Example of a Moore Machine Example of a Mealy Machine
The following figure shows a Let’s assume that the
Moore machine (modulus-26 tablet-bottling system
binary counter with states 0 uses three different
through 25) that is used to sizes of bottles: a 25-
control the number of tablets tablet bottle, a 50-
(25) that go into each bottle tablet bottle, and a
in an assembly line. When 100-tablet bottle. This
the binary number in the operation requires a
memory (flip-flops) reaches state machine with
binary twenty-five (11001), three different terminal
the counter recycles to 0 counts: 25, 50, and 100.
and the tablet flow and
clock are cut off until the
next bottle is in place.
Asynchronous Counters
The term asynchronous refers to events that do not
have a fixed time relationship with each other and,
generally, do not occur at the same time. An
asynchronous counter is one in which the flip-flops (FF)
within the counter do not change states at exactly the
same time because they do not have a common
clock pulse.
A 2-Bit Asynchronous Binary Counter
The figure below shows a 2-bit counter connected for
asynchronous operation. Notice that the clock (CLK) is
applied to the clock input (C) of only the first flip-flop,
FF0, which is always the least significant bit (LSB).
A 3-Bit Asynchronous Binary Counter
The basic operation is the same as that of the 2-bit
counter except that the 3-bit counter has eight states,
due to its three flip-flops.
Notice that the counter progresses through a binary
count of zero through seven and then recycles to the
zero state. This counter can be easily expanded for
higher count, by connecting additional toggle flip-
flops.
Propagation Delay Asynchronous Decade Counters
Asynchronous counters are commonly referred to as The modulus of a counter is the number of unique
ripple counters for the following reason: The effect of states through which the counter will sequence. The
the input clock pulse is first “felt” by FF0. This effect maximum possible number of states (maximum
cannot get to FF1 immediately because of the modulus) of a counter is 2n, where n is the number of
propagation delay through FF0. Then there is the flip-flops in the counter. Counters can be designed to
propagation delay through FF1 before FF2 can be have a number of states in their sequence that is less
triggered. Thus, the effect of an input clock pulse than the maximum of 2n. This type of sequence is
“ripples” through the counter, taking some time, due called a truncated sequence.
to propagation delays, to reach the last flip-flop.
A modulus for counters with truncated sequences is
This ripple clocking effect is shown below for the first ten (called MOD10). Counters with ten states in their
four clock pulses, with the propagation delays sequence are called decade counters. A decade
indicated. The LOW-to-HIGH transition of Q0 occurs counter with a count sequence of zero (0000) through
one delay time (tPLH) after the positive-going transition nine (1001) is a BCD decade counter because its ten-
of the clock pulse. state sequence produces the BCD code.
This type of counter is useful in display
applications in which BCD is required for
conversion to a decimal readout.
To obtain a truncated sequence, it is necessary
to force the counter to recycle before going
through all of its possible states. For example, the
BCD decade counter must recycle back to the
0000 state after the 1001 state. A decade
counter requires four flip-flops (three flip-flops are
insufficient because 23 = 8)
Partial Decoding
Notice in the figure below that only Q1 and Q3 are Thus, the counter is in the 1010 state for a short time
connected to the NAND gate inputs. This arrangement before it is reset to 0000, Thus, producing the glitch on
is an example of partial decoding, in which the two Q1 and the resulting glitch on the CLR line that resets
unique states (Q1 = 1 and Q3 = 1) are sufficient to the counter.
decode the count of ten because none of the other
states (zero through nine) have both Q1 and Q3 HIGH Other truncated sequences can be implemented in a
at the same time. When the counter goes into count similar way.
ten (1010), the decoding gate output goes LOW and
asynchronously resets all the flip-flops.
The resulting timing diagram is shown in the next slide.
Notice that there is a glitch on the Q1 waveform. The
reason for this glitch is that Q1 must first go HIGH before
the count of ten can be decoded.
Not until several
nanoseconds after
the counter goes to
the count of ten
does the output of
the decoding gate
go LOW (both
inputs are HIGH).
 D flip-flops are also used but they require more logic.
They have no direct toggle or no-change states.
A 2-Bit Synchronous Binary Counter
Different arrangements from that for the asynchronous
counter are used, in order to achieve a binary
sequence in JK and D flip-flop implementation.

Synchronous Counters
The term synchronous refers to events that have a fixed
time relationship with each other. A synchronous
counter is one in which all the flip-flops in the counter
are clocked at the same time by a common clock
pulse. J-K flip-flops are used to illustrate most
synchronous counters.
A timing diagram of the counter operation is shown The complete timing diagram is shown below. Notice
below. that the propagation delays are not indicated.
Although the delays are an important factor in the
synchronous counter operation, in an overall timing
diagram they are normally omitted for simplicity.
A 3-Bit Synchronous Binary Counter
This counter operation can be
understood by examining its sequence
of states as shown in the presented
table.
The analysis of the counter is
summarized in the next slide.
A 4-Bit Synchronous
Binary Counter
This particular counter
is implemented with
negative edge-
triggered flipflops.

The fourth stage, FF3,

changes only twice
in the sequence.

Notice that both of these transitions

occur following the times that Q0, Q1,
and Q2 are all HIGH.
This condition is decoded by AND
gate G2 so that when a clock pulse
occurs, FF3 will change state.
For all other times the J3 and K3 inputs
of FF3 are LOW, and it is in a no-
change condition.
A 4-Bit Synchronous
Decade Counter
A BCD decade counter
exhibits a truncated
binary sequence and
goes from 0000 through
the 1001 state.
Rather than going from
the 1001 state to the
1010 state, it recycles to
the 0000 state.
Up/Down Synchronous Counters
An up/down counter is one that is capable of
progressing in either direction through a certain
sequence. An up/down counter, sometimes called a
bidirectional counter, can have any specified
sequence of states. A 3-bit binary counter that
advances upward through its sequence (0, 1, 2, 3, 4, 5,
6, 7) and then can be reversed so that it goes through
the sequence in the opposite direction (7, 6, 5, 4, 3, 2,
1, 0) is an illustration of up/down sequential operation.
In general, most up/down counters can be reversed at
any point in their sequence.
For instance, the 3-bit binary
counter can be made to go
through:

The arrows indicate the state-

to-state movement of the
counter for both its UP and its
DOWN modes of operation.
Design of Synchronous Counters state, which is the state that the counter goes to from
its present state upon application of a clock pulse.
Sequential circuits can be classified into two types: (1)
those in which the output or outputs depend only on
the present internal state (Moore state machines) and
(2) those in which the output or outputs depend on
both the present state and the input or inputs (Mealy
state machines).
Step 1: State Diagram
The first step in the design of a state machine (counter)
is to create a state diagram. A state diagram shows
the progression of states through which the counter
advances when it is clocked.
As an example, The
following is a state
diagram for a basic 3-bit Step 3: Flip-Flop Transition Table
Gray code counter. This
particular circuit has no
inputs other than the clock
and no outputs other than
the outputs taken off each
flip-flop in the counter.
Step 2: Next-State Table
The next-state table lists each state along with the next
Step 4: Karnaugh Maps
Step 5: Logic Expressions for Flip-Flop Inputs Step 6: Counter Implementation
From the Karnaugh maps we obtain the following The final step is to implement the combinational logic
expressions for the J and K inputs of each flip-flop: from the expressions for the J and K inputs and
connect the flip-flops to form the complete 3-bit Gray
code counter as shown below.