Tien Pham Van, Dr. rer. nat.

Hanoi University of Science and Technology

Compiled with reference to other presentations

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Outlines

• Custom interfaces
• GPIO
• Communication
• Human machine
interfaces

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Hardware: system view

Embedded system is a special-purpose computing device designed to perform dedicated function

EMBEDDED
INPUT OUTPUT
SYSTEM

- Keyboard Button - LCD Display

- Steering wheel position - Servo Engine

SOFTWARE
- Microphone APPLICATION SOFTWARE
- EEG signals
SYSTEM SOFTWARE
MIDDLEWARE

DEVICE DRIVERS

Analog Environment

Digital Environment HARDWARE

EMBEDDED BOARD
OUTPUT DEVICES

MCU

INPUT DEVICES

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Embedded development trend
• Interconnection
– IoT/M2M
– Diversified communication physical means
• Distribution/decentralization
– More modules to co-work
– Higher parallelism
• Human machine interface
– Behavior recognition
– More intelligent
• Customizability
– Configurable hardware
– Universal ports

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Devices have different data Rates
different I/O techniques used
+ sensors, actuators, SSD, router

Embedded
2/16 Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Interface Performance Measures

• Latency
 delay between service request and service
completion
» includes both software and hardware delays
 for real-time systems
» guarantee must be made for worst-case latency
• Bandwidth (or throughput)
 maximum rate at which data can be processed
• Priority
 determines service order when more than one
request is pending
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Synchronizing SW w/ I/O Devices

• Problem: I/O devices operate in parallel w/ controller

 pro: parallelism enhances performance
 con: it’s hard for humans to get it right
• Hardware common case
 3 states: idle, busy, or done
 when not idle
» busy and done alternate
• I/O or CPU bound (unbuffered vs. buffered interfaces)
 I/O bound is typical
» I/O devices often much slower than controller SW loop
• synchronization is required
• unbuffered interface works but SW has to do significantbabysitting
 CPU bound
» still need synchronization for accurate information transfer
» buffering required to store I/O transactions

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Synchronization Mechanisms

• Blind cycle
 SW waits a fixed amount of time for the I/O to complete
» then samples input or produces another output
• Busy waiting
 check I/O status flag once per iteration (previous example)
» waits for flag to indicate I/O done state
• Interrupt
 I/O requests SW to become active
• Periodic polling
 timer based interrupt requests software activity
» 6812 TCNT timer both more accurate and energy efficient than a cycle
counting software timer
• Direct Memory Access (DMA)
 I/O device transfers data to/from controller memory
» memory used as a mailbox to facilitate communication
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Scalable Embedded I/O Bus Architectures
- Device I/O interfaces and Drivers for
Real-time Systems | Coursera
https://www.coursera.org/lecture/real-time-mission-
critical-systems-design/scalable-embedded-i-o-bus-
architectures-sGxqA

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 I/O Basics

• I/O controller  I/O devices ports

– Transfers data to/from device
– Synchronizes operations with software
• Command / control registers
• Status registers: device status, errors
• Data registers
– Write: data  device eg Transmit
– Read: CPU device eg receive
– multiple I/O registers can map to same address

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Device Drivers

• Device-specific – controls IO device, written by

manufacturer eg SSD driver, mouse,
– command registers, commands vary from device to device

• Part of kernel
– Compiled with OS, Dynamically loaded into OS
• Accept abstract R/W requests from device-independent layer ;
• Initialize device, Manage power, and log
• Check & translate input parameters
– e.g., convert linear block number into the head, track, sector and cylinder
number for disk access
• Check device status & Control  sequence of commands

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 CPU Bus I/O

• CPU needs to talk to I/O Address

Data

• Memory-mapped I/O CPU

Read
– Devices mapped to Write
reserved memory locations -
like RAM Memory I/O Device
– Uses load/store instructions
just like accesses to memory
Address
Data
• I/O mapped I/O CPU Memory I/O
– Special bus line Read
Write
– Special instructions
I/O Port
Memory
I/O Device
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Memory Mapped I/O

Physical Layout Programmer’s View

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 I/O Register operations
 I/O Registers are NOT like normal memory
 Device events can change their values (e.g., status registers)
 Reading a register can change its value (e.g., error condition
reset)
 For example, can't expect to get same value if read twice
 Some are readonly (e.g., receive registers)
 Some are writeonly (e.g., transmit registers)
 Sometimes multiple I/O registers are mapped to same address
 Selection of one based on other info (e.g., read vs. write or extra control
bits)
 Cache must be disabled for memory-mapped addresses – why?
 When polling I/O registers, should tell compiler that value can
change on its own and therefore should not be stored in a register
 volatile int *ptr; (or int volatile *ptr;)
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Parallel vs. Serial Digital Interfaces

 Parallel $$$$
– Multiple parallel data lines
– Hi Speed
– Ex: PCI, ATA, CF cards
 Serial convenient
– minimal data lines
– Low Power, length
– Ex: USB, SATA, SD (secure digital),
I2C, SPI, CAN, PCI-Express

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Serial vs. Parallel

TX
Serial MCU 1 RX MCU 2

signal

Data[0:7]

Parallel MCU 1 MCU 2

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Why Serial Communication?

 Serial communication is a pin-efficient way of sending and

receiving bits of data
 Sends and receives data one bit at a time over one wire
 While it takes eight times as long to transfer each byte of data this way
(as compared to parallel communication), only a few wires are required
 Typically one to send, one to receive (for full-duplex), and a common
signal ground wire

 Simplistic way to visualize serial port

 Two 8-bit shift registers connected together
 Output of one shift register (transmitter) connected to the input of the
other shift register (receiver)
 Common clock so that as a bit exits the transmitting shift register, the bit
enters the receiving shift register
 Data rate depends on clock frequency

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Simple Serial Port
Receive
Buffer Register

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7
Receive
Shift Register
Transmit
Shift Register 0 1 2 3 4 5 6 7
Transmit 0 1 2 3 4 5 6 7
Hold Register

Processor Peripheral
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Protecting Against Data Loss
 How can data be lost?
 If the transmitter starts to send the next byte before the
receiver has had a chance to process/read the current byte
 If the next byte is loaded at the transmitter end before the
current byte has been completely transmitted

 Most serial ports use FIFO buffers so that data

is not lost
 Buffering of received bytes at receiver end for later processing
 Buffering of loaded bytes at transmitter end for later
transmission
 Shift registers free to transmit and receive data without worrying
about data loss

 Why does the size of the FIFO buffers matter?

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Serial Port

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FIFO Buffer FIFO Buffer

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Clock Clock
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

FIFO Buffer FIFO Buffer

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

Processor Peripheral
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 What is RS-232?

 So far, we’ve talked about clocks being synchronized and using the
clock as a reference for data transmission
 Fine for short distances (e.g., within chips on the same board)

 When data is transmitted over longer distances (off-chip), voltage

levels can be affected by cable capacitance
 A logic “1” “1”might appear as an indeterminate voltage at the receiver
 Wrong data might be accepted when clock edges become skewed

 Enter RS232: Recommended Standard number 232

 Serial ports for longer distances, typically, between PC and peripheral
 Data transmitted asynchronously, i.e., no reference clock
 Data provides its own reference clock

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Types of Serial Communications

 Synchronous communication
 Data transmitted as a steady stream at regular intervals
 All transmitted bits are synchronized to a common clock signal
 The two devices initially synchronize themselves to each other, and
then continually send characters to stay synchronized
 Faster data transfer rates than asynchronous methods, because it does
not require additional bits to mark the beginning and end of each data
byte
 Asynchronous communication
 Data transmitted intermittently at irregular intervals
 Each device uses its own internal clock resulting in bytes that are
transferred at arbitrary times
 Instead of using time as a way to synchronize the bits, the data format is
used
 Data transmission is synchronized using the start bit of the word, while
one or more stop bits indicate the end of the word
 Asynchronous communications slightly slower than synchronous

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Sync vs. Async

 Synchronous communications
 Requires common clock (SPI)
 Whoever controls the clock controls communication speed

 Asynchronous communications
 Has no clock (UART)
 Speed must be agreed upon beforehand (the baud-rate configuration
accomplishes that)

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 RS232 – Bits and Serial Bytes

 Serial ports on IBM-style PCs support asynchronous communication only

 A “serial byte” usually consists of
 Characters: 5-8 data bits
 Framing bits: 1 start bit, 1 parity bit (optional), 1-2 stop bits
 When serial data is stored on your computer, framing bits are removed, and this
looks like a real 8-bit byte
 Specified as number of data bits - parity type - number of stop bits
 8-N-1 a eight data bits, no parity bit, and one stop bit
 7-E-2 a seven data bits, even parity, and two stop bits
MSB LSB
0 1 2 3 4 5 6 7

7 6 5 4 3 2 1 0

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 RS-232 Signal Levels

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Serial Port Connector

 9-pin (DB-9) or 25-pin (DB-25) connector

 Inside a 9-pin connector
 Carrier Detect - Determines if the DCE is connected to a working
phone line
 Receive Data - Computer receives information sent from the DCE
 Transmit Data - Computer sends information to the DCE
 Data Terminal Ready - Computer tells the DCE that it is ready to talk
 Signal Ground - Pin is grounded
 Data Set Ready - DCE tells the computer that it is ready to talk
 Request To Send - Computer asks the DCE if it can send information
 Clear To Send - DCE tells the computer that it can send information
 Ring Indicator – Asserted when a connected modem has detected an
incoming call

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Embedded Real-Time Systems

RS-232 Pin Connections

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Handshaking

 Some RS232 connections using handshaking lines between DCE

and DTE
 RTS (ReadyToSend)
• Sent by the DTE to signal the DCE it is Ready To Send
 CTS (ClearToSend)
• Sent by the DCE to signal the DTE that it is Ready to Receive
 DTR (DataTerminalReady)
• Sent to DTE to inform the DCE that it is ready to connect
 DSR (DataSetRead)
• Sent to DCE to inform the DTE that it is ready to connect
 Handshaking lines can make it difficult to set up the serial
communications, but seamless after set-up.
 Also, software handshaking (XON/XOFF)

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Interfacing Serial Data to Microprocessor

 Processor has parallel buses for data need to convert serial data to
parallel (and vice versa)
 Standard way is with UART
 UART Universal asynchronous receiver and transmitter

Chip Reg
Select
Tx Clock
R/W
Control

Tx Data Reg Tx Shift Reg Tx Data

IRQ
Status Reg
CTS
D0-D7 Data Control Reg
Bus RTS
Buffers Rx Data Reg Rx Shift Reg Rx Data
Rx Clock

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Flow Control

 Necessary to prevent terminal from sending more data than the

peripheral can consume (and vice-versa)
 Higher data rates can result in missing characters (data-overrun errors)
 Hardware handshaking
 Hardware in UART detects a potential overrun and asserts a handshake
line to prevent the other side from transmitting
 When receiving side can take more data, it releases the handshake line
 Software flow-control
 Special characters XON and XOFF
 XOFF stops a data transfer (control-S or ASCII code 13)
 XON restarts the data transfer (control-Q or ASCII code 11)
 Assumption is made that the flow-control becomes effective before
data loss happens

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Other Serial Buses

I2C
RS-232 Two wire chip interconnect,
Point-to-point +/-12V multi-drop

I2S
RS-485 Audio format similar to SPI

Multi-drop RS-232
SPI
Four wire only chip
interconnect, multi-drop

Many more…
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Serial Peripheral Interconnect (SPI)

 Another kind of serial protocol in embedded systems (proposed by

Motorola)
 Four-wire protocol for short communication distance
 SCLK — Serial Clock
 MOSI/SIMO — Master Output, Slave Input
 MISO/SOMI — Master Input, Slave Output
 SS — Slave Select (Multiple Slaves, Single Master)
 Single master device and with one or more slave devices
 Higher throughput than I2C and can do “stream transfers”
 No arbitration required
 But
 Requires more pins
 Has no hardware flow control
 No slave acknowledgment (master could be talking to thin air and not
even know it)

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 SPI explanation

• SPI? – YouTube
https://www.youtube.com/watch?v=NyxQkGXbG6I
• Serial Bus protocol
• Synchronized
• Fast, Easy to use, Simple
• Everyone supports it

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 SPI Capabilities

 Always Full Duplex

 Communicating in two directions at the same time
 Transmission need not be meaningful

 Multiple Mbps transmission speed

 Transfers data in 4 to 16 bit characters

 Multiple slaves
 Daisy-chaining possible

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Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 SPI Protocol

 Wires:
 Master Out Slave In (MOSI)
 Master In Slave Out (MISO)
 System Clock (SCLK)
 Slave Select 1…N

 Master Set Slave Select low

 Master Generates Clock

 Shift registers shift in and out data

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 SPI Communication

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 SPI Pros and Cons

 Pros:
 Fast and easy
 Fast for point-to-point connections
 Easily allows streaming/Constant data inflow
 No addressing/Simple to implement
 Everyone supports it

 Cons:
 SS makes multiple slaves very complicated
 No acknowledgement ability
 No inherent arbitration
 No flow control

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 I2C Background

 I2C is also written as I2C (pronounced “eye-squared-see” or“eye- two-

see”)
 Stands for Inter-Integrated Circuit (IIC)
 Two-wire party-line bus for “inside the box”communication
 Intended for short-range communication between ICs on a circuit
board or across boards in an embedded system
 I2C devices commonly used in industrial applications
 EEPROMs, thermal sensors, real-time clocks, RF tuners, video
decoders/encoders
 Philips Semiconductors is the primary champion of I2C
 Specification publicly available at
http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf
 Originally developed for communication between devices inside a TV
set in the mid-1980s

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 I2C Characteristics

 Only two bus lines are required

 Each device connected to the bus is software-addressable by a
unique address and
 Simple master/slave relationships
 True multi-master bus including collision detection and arbitration to
prevent data corruption if two or more masters simultaneously
initiate data transfer
 Serial, 8-bit oriented, bidirectional data transfers
 Up to 100 kbit/s in the standard mode
 Up to 400 kbit/s in the fast mode
 High-speed (3.4 Mbps), I2C version2.0
 On-chip filtering rejects spikes on the bus data line to preserve data
integrity

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 I2C Design Criteria

 First of all, this is a serial bus

 Targeting 8-bit microcontroller applications
 Serial vs. parallel
 Criteria for design of I2C
 Need to avoid confusion between connected devices
 Fast devices must be able to communicate with slow ones
 Protocol must not be dependent on the devices that it
connects
 Need to have a mechanism to decide who controls the bus
and when
 If different devices with different clock speeds are connected,
the bus clock speed must be defined

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 I2C Explanation
 I2C? – YouTube
https://www.youtube.com/watch?v=qTLRRg6Mee0

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 I2C Details

 Two lines: Serial data line (SDA) & serial clock line (SCL)
 Each I2C device recognized by a unique address
 Each I2C device can be either a transmitter or receiver
 I2C devices can be masters or slaves for a data transfer
 Master (usually a microcontroller): Initiates a data transfer on the bus,
generates the clock signals to permit that transfer, and terminates the
transfer
 Slave: Any device addressed by the master at that time
 Roles/relationships are not permanent

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Master-Slave Relationships

 Masters can operate as master-transmitters or master-receivers

 Suppose microcontroller A wants to send information to
microcontroller B
 A (master) addresses B (slave)
 A (master-transmitter), sends data to B (slave-receiver)
 A terminates the transfer.
 If microcontroller A wants to receive information from microcontroller
B
 A (master) addresses microcontroller B (slave)
 A (master-receiver) receives data from B (slave-transmitter)
 A terminates the transfer
 In both cases, the master (microcontroller A) generates the timing
and terminates the transfer

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Connecting I2C Devices to the Bus

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Addressing

 First byte of transfer contains the slave address and the data direction
 Address is 7 bits long, followed by the direction bit
 Like all data bytes, address is transferred with the most significant bit first
 7-bit address space allows for 128 unique I2C device addresses
 16 addresses are reserved for special purposes
 Leaves only 112 addresses with this 7-bit address scheme
 New 10-bit address scheme has been introduced
 “General call”broadcast – to address every device on the bus

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Clock Stretching

 Form of flow control

 An addressed slave device may hold the clock line low after
receiving (or sending) a bit, indicating that it is not yet ready to
process more data
 Master that is communicating with the slave will attempt to raise the
clock to transfer the next bit, but
 If the slave is clock stretching, the clock line will still be low
 Mechanism allows receivers that cannot keep up with a transmitter
to control the flow of incoming data

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 PCI-express

• A high-speed serial computer expansion bus

standard, succeeding the older PCI, PCI-X and AGP
• PCI Express is a point-to-point connection, but
communicates directly with devices via a switch
that directs data flow.
• It is used for graphics cards, hard disk drive host
adapters, SSDs, Wi-Fi and Ethernet hardware
connections
• Improvements over the older: higher throughput,
lower I/O pin count and smaller physical footprint,
more detailed error detection and reporting
mechanism…
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 PCI-e

• Multiple lanes, each containing sending and

receiving lines of data, PCI-e may be used for
ExpressCard, SATA Express, U.2 (SFF-8639)
and M.2
• There may by up to 16 lanes

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 PCI-e connector pinout

• PCI Express – Wikipedia

https://en.wikipedia.org/wiki/PCI_Express

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Further reading

• Mini PCI-Express
https://www.assured-
systems.com/uk/news/article/what-
are-mini-pci-express-mpcie-cards/
• M2
https://en.wikipedia.org/wiki/M.2

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Fieldbus

• A family of industrial computer

networks used for real-time
distributed control
• It links the PLCs to sensors, actuators,
• Real-time ethernet tends to dominate
• Popular protocols: ModBus, Profibus,
CAN

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 • What is Fieldbus? – YouTube
https://www.youtube.com/watch?v=ndc6at_d7uQ
• CAN Bus System Explained – YouTube
https://www.youtube.com/watch?v=jnQoR67lIug

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Concept

• Uncommitted digital signal pin on an

integrated circuit or electronic circuit board
which may be used as an input or output, or
both, and is controllable by the user at
runtime
• Purpose and behavior is defined and
implemented by the circuit board designer in
the case of integrated circuit GPIOs, or
system integrator in the case of board-level
GPIOs
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 How GPIO works | General Purpose Input
Output | GPIO Behind The Scene –
YouTube
https://www.youtube.com/watch?v=QxvdmzKxEeg

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Integrated circuit GPIOs

• Microcontroller ICs usually include

GPIOs: may comprise its primary
interface to external circuitry, or be just
one type of I/O used among several,
such as analog signal I/O,
counter/timer, and serial
communication
• Some ICs provide GPIOs as a primary
function whereas others include GPIOs
as a convenient "accessory"
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Board-level GPIOs
• Many circuit boards expose board-level
GPIOs to external circuitry through integrated
electrical connectors. Usually, each such GPIO
is accessible via a dedicated connector pin
• Board-level GPIOs may provide Schmitt-
trigger inputs, high-current output drivers,
optical isolators for buffering, conditioning,
and protection
• Higher-level functions may be implemented,
such as input debounce, signal edge
detection, and PWM
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Implementation

• A GPIO pin's state may be exposed to the

software developer through one of a number of
different interfaces, such as a memory-mapped
I/O peripheral, or through dedicated IO port
instructions
• Some GPIOs have 5 V tolerant inputs: even
when the device has a low supply voltage (such
as 2 V), the device can accept 5 V without
damage
• A GPIO port is a group of GPIO pins (usually 8
GPIO pins) arranged in a group and controlled
as a group
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Abilities

• GPIO pins can be configured to be input

or output
• GPIO pins can be enabled/disabled
• Input values are readable (usually high or
low)
• Output values are writable/readable
• Input values can often be used
as IRQs (usually for wakeup events)

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 • General Purpose Input Output Lines (GPIO)
theory – YouTube
https://www.youtube.com/watch?v=z5GmbjUbges

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 USB

• Provides communication and power supply

between computers, peripherals and other
computers
• It has largely replaced interfaces such as
serial ports and parallel ports, and has
become commonplace on a wide range of
devices
Pin 1 VBUS (+5 V)
Pin 2 Data−
Pin 3 Data+
Pin 4 Ground

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 • Universal Serial Bus (USB) – YouTube
https://www.youtube.com/watch?v=RxuM2eHy5vI

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Further reading

• Wireless interfaces: BLE, ZigBee, Z-Wave

• LPWAN: LoRa, NB-IoT, LTE-M

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Concept

• Wearable sensors
• Touchscreen
• Screens/glasses
• Image processing-based interfaces
• Brain-computer interfaces

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 • Human Machine Interface (HMI) Adaptive
User Interface (xilinx.com)
https://www.xilinx.com/video/application/human-
machine-interface-hmi-adaptive-user-interface.html

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Interface boundaries

The design of an embedded system

interface can be seen as the placement of
two boundaries:
• The boundary between the software on
the CPU and the interface's digital
hardware.
• The boundary between the interface's
digital hardware and its analog hardware.

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Determination of embedded system use cases

• Help identify the important characteristics of their

interfaces
• CPU performance is a key driver of software
development; the class of CPU required to meet
performance requirements also constraints the
available microcontroller or system-on-chip
platforms and their associated interfaces.
• Sample rate is related to the software load but also
to the performance requirements on the interfaces.
• Network bandwidth requirements to the outside
world may constrain the interconnection
bandwidth available within the embedded
platform.

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Interface specifications

• The data rate or sample rate limits the frequency

characteristics of our signal. The latency of
processing is often critical; analog/digital and
hardware/software design choices may be
determined by how long we have to process a
signal.
• The precision and dynamic range of a signal
reflect the required resolution of the signal.
Interface design needs to preserve enough dynamic
range of the signal to allow the required processing
to be completed.
• Power consumption is a key parameter for many
designs. High power consumption may also lead to
excessive heat dissipation.
Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Choosing the right platform

Hardware platform:
• The processor or, in the case of high-
performance systems, several processors.
Some of the processors may provide only
limited programmability, as is the case for
many video accelerators.
• The set of I/O devices provided by the
platform.
• The bus interface.

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Choosing the right platform

Software platform:
• A hardware abstraction layer (HAL), board
support package (BSP), or basic input/output
system (BIOS).
• Device drivers.
• An executive or operating system.

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Hardware and software boundaries

• The partition between software running on

the CPU and interface hardware is the basic
decision in interface design.
• Various metrics must be considered for
balancing between the CPU and the
interface: algorithm complexity, cpu
utilization, sampling rate, numerical precision
and dynamic range, and latency

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Analog/Digital Boundaries

• We often have some choice as to how much

processing to perform on the signals in
analog form before converting them to digital
form
• Many specifications must be taken into
account: signal characteristics, dynamic
range, power consumption, latency, etc

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596
 Methodology

• We separate interface design details from

the rest of the system but inform the
system design of requirements,
specifications, architecture and testing
• For signals processed at interface, we need
to take care of signal forms, timing, power,
dynamic range, sampling rate, algorithm,
latency…
• From the requirements and other factors
such as costs, design effort, we come to
determine sw/hw boundaries and
partitioning which part to be implemented
by CPU and which by interface

Embedded Networking Research Group School of Elec. and Telecom - Hanoi University of Science and Technology
Email: tien.phamvan1@hust.edu.vn C9-411, Dai Co Viet str. 1, HBT, Hanoi Tel: +84-243-8693596