On the Design of High Switching Frequency

DC-DC Buck Converter Power Stages for

Automotive Post-Regulated Applications
Filippo Boera∗ , Bernd Pflaum† , Giuseppe Torti‡ , Franco Maloberti∗ , Edoardo Bonizzoni∗
∗
Dept. of Electrical, Computer and Biomedical Engineering, University of Pavia, Pavia, Italy
†
Infineon Technologies AG, Neubiberg, Germany
‡
Infineon Technologies Italy, Pavia, Italy
E-mail: filippo.boera01@universitadipavia.it, bernd.pflaum@infineon.com

Abstract—This paper describes the design and the performance which can often cost more than the chip itself, both in terms
comparison of four different configurations of power stages of of money and area consumption. It is known that the inductor
switching DC-DC buck converters with high switching frequency current ripple in DC-DC converters is dependent from both
(f = 100 MHz), studied for automotive applications in the post-
regulated domain. Different transistors are used for both power the inductance value and the switching frequency [1], through
stage and pre-driver chain, and the solutions are compared in the following equation:
terms of efficiency and maximum input voltage. A rough estima- Vout (1 − D)
tion of the area consumption of each of the four configuration is ∆il = (1)
also provided. The circuits have been optimized to have maximum Iload · f s · L
efficiency with Vin = 3.6 V, Vout = 1.8 V and Iload = 1 A, which Where ∆il is the current ripple, Vout is the output voltage, Iload
are typical values in automotive post-regulated applications.
the output current, D the duty cycle, f s the switching frequency
I. Introduction and L the inductance value. The typical switching frequency of
The current trends in the automotive market push toward a DC-DC converter is a few MHz. By increasing the switcing
an ever increasing integration of electronic components in a frequency, a much smaller inductor can be used without
car. Modern cars need to be safer and smarter, hence there degrading the ripple. Smaller inductors could be inserted inside
is the need of a lot of sensors, radars, microcontrollers etc. the package, or even integrated, thus saving a lot of space and
Consequentially, the power supply circuits that are needed to money.
power up all these devices starting from the 12-V battery Efficiency is obviously another key parameter, defined as:
of a car are also facing an intense thrust to integration. Vout · Iload
!
More integration of the power supply circuits means that the η = avg (2)
Vin · Iin
production costs and area of the components are significantly
reduced, but leads to less flexibility of the circuits and less Where Vin and Iin are, respectively, the input voltage and
robustness to high temperatures. The traditional approach was the input current. A higher efficiency translates in less power
to directly convert the battery voltage to each desired lower wasted, and therefore in less CO2 emission, which, for both
voltage (using either low dropout regulators or switching DC- environmental and economic reasons, has become a very
DC depending on the application). Nowadays a post-regulated critical specification for car manufacturers in recent years. The
approach is preferred: one converter downshifts the battery purpose of this research is the study and the design of a buck
voltage to an intermediate one, typically in the range of 4∼8 converter power stage switching at 100 MHz with a target
V, and that intermediate voltage can either directly supply efficiency of at least 85%.
some circuits, or be the input of multiple successive regulators, This paper is organized as follows. Section II summarizes
that will each power up the circuits that require lower supply the previous art and describes the designed circuits, Section
voltages. While complicating the design, this approach is III discusses the simulation results and Section IV concludes
preferred due to a higher efficiency, and the possibility of the paper.
a more robust thermal isolation of the circuits. Since each
II. Circuit Description
converter can be thermally isolated from the others, they can be
properly designed according to their own thermal environment. A. Previous Art
This work, done in collaboration with Infineon Technologies The most common configuration for an integrated buck
Italy, focuses on switching DC-DC buck converter in the post- DC-DC converter power stage uses a PMOS as high-side
regulated domain. switch, and an NMOS as low-side switch, both driven with
Switching DC-DC converters are usually very expensive and a tapered chain of inverters. This structure is simple, well
bulky, and this is mostly due to the presence of the inductor, known, and has a high efficiency, therefore it is widely used,

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 HVP1 MVP1
PWMH PWMH

MVP2

Vin MV L
Vin MV L
MVN2
C Iload C Iload
Vin/2 HVN1 Vin/2 MVN1
PWML PWML

GND GND

(a) (b)

VDS MVP1 VDS LVP1

PWMH PWMH

MVP2 MVP2

Vin LV L
Vin LV L
MVN2 MVN2
C Iload C Iload
VDS MVN1 VDS LVN1
PWML PWML

GND GND

(c) (d)

Fig. 1. Four proposed schematics: (a) HV, (b) MV, (c) Mv with LV driving, (d) Hybrid LV+MV.

[2], [3]. However, the simple buck power stage has an intrinsic switching at 100 MHz with an output current equal to 1 A
limitation: the maximum input voltage that it can sustain and Vin up to more than 4 V.
is equal to the maximum drain-to-source voltage (VDS ) of
the transistor allowed by the technology. If the application B. Designed Circuits
requires an input voltage which is higher than the maximum The technology for high voltage automotive applications
VDS , there are two possible solutions: either use transistors used in this work features several MOS transistors, each with
from a different technology that allows a higher voltage, different minimum sizes, maximum VDS sustainable, threshold
or stack multiple ”low voltage” transistors. By stacking two voltage, and capacitance. The transistors involved in this study
PMOS and two NMOS transistors the maximum Vin rises to are three: a “high voltage” (HV) MOS with minimum channel
2VDS , assuming that the two transistors are equal in terms length of approximately 1 µm, a “medium voltage” (MV)
of maximum VDS . A number of stacked structures or high MOS with minimum channel length of approximately 400 nm,
frequency buck converters has been studied in literature. The and a “low voltage” (LV) MOS with minimum channel length
research in [4] shows an example of this technique: by stacking of approximately 120 nm. The maximum VDS sustainable is,
two 180-nm transistors higher input voltages are allowed, and obviously, higher for the HV MOS, intermermediate for the
a high efficiency (88%) is still reached with Iload = 250 mA. MV MOS and lower for the LV MOS. The purpose of this
The work presented in [5] brings this configuration even study is to verify which device and which topology works
further stacking three low voltage transistors (40-nm with best as a power stage. The correct choice of transistor types
maximum VDS around 1 V) to sustain 3.3 V of input voltage and dimensions for the pre-driver inverter chain also counts
with very high efficiency (97 %) when the load current is 150 for an optimal efficiency.
mA. The circuit in [6] uses a 45-nm technology to achieve a Fig. 1 shows the four schematics designed and compared in
peak efficiency of 87.8% with a very high switching frequency this paper. The circuit in Fig. 1 (a) uses the HV MOSFETs
equal to 240 MHz and Iload = 250 mA. However, the particular as power stage and the MV MOS in the inverter chains. The
dead time architecture proposed requires both positive and chains are supplied at Vin /2, since the MV MOSFETs cannot
negative inductor current to properly work. All these solutions sustain the full range of Vin . The HV MOSFETs can sustain
achieve high efficiencies with high switching frequency, but any Vin in the desired range, but the length and the large
with output currents in the range of only few hundred of gate capacitance of the HV MOSFETs cause an increase of
mA. For automotive post-regulated applications, the output both switching and conduction losses, decreasing the overall
current is typically much larger, up to 1∼2 A which is another power efficiency. The use of HV transistors can be avoided
challenging specification for the design. This paper studies by building the power stage with two MV MOSFETs stacked,
different configurations and technologies for a power stage as shown in Fig. 1(b). This circuit can still sustain any Vin in

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the desired range, and the MV devices are more performing at
high frequencies, thanks to their reduced dimension and capac-
itance. Without changing the MV power stage, if the low-side
and high-side chains are designed with LV transistors instead
of MV, as shown in Fig. 1(c), another slight improvement
in the efficiency could be obtained. Notice that, unlike the
previous two circuits, in the circuit in Fig. 1(c) the low supply
of the high-side chain and the high side of the low-side chain
cannot be both set as Vin /2, but have to be set to a lower
value to avoid the breakdown of he LV chains. The fourth and
last circuit is shown in Fig. 1(d). For this circuit, a hybrid
solution for the power stage has been studied, cascading a LV
and a MV transistor. LV MOSFETs are used for switching,
while MV are used as cascode. Given the reduced channel
Fig. 2. Simulated power stages efficiency as a function of the load current.
length of the LV MOS which makes them more suited for high
frequency switching, the efficiency is expected to rise, while
the MV cascode protects the LV MOS, ensuring high voltage
operation. The drawback of this solution is the maximum
sustainable Vin , now limited to 4 V (Vds (LV) + Vds (MV)).
To minimize the losses, in all the designs, the channel length
of the MOSFETs has been kept to the minimum value. Since
the maximum load current required is 2 A, the channel widths
of the power stages have been optimized for Iload = 1 A (half
the maximum value, assuming that the converters will rarely
have to work at maximum load condition), while the widths of
the low-side and high-side chains have been calculated with
the taper formula:

(b + 1)n−1
Wn−1 = Wn (3)
an Fig. 3. Simulated output voltage ripple.
In (3), a is the taper factor, b is the WP /WN ratio, n is the
number of each inverter. As shown in Fig. 1, for all the power
stages, chains of five inverters have been used for high and boost in the efficiency (gray curve): from 79% to 82%. The
low side driving. Parasitic Equivalent Series Resistances (ESR) highest efficiency is achieved with the hybrid LV+MV power
of the inductor and capacitor are included in the schematics, stage (yellow curve) that reaches a peak efficiency of 86%.
equal for all the four configurations. A detail of the output voltage ripple in the four circuits is
shown in Fig. 3, equal to 20 mV in all the cases. Fig. 4
III. Simulation Results shows the drain voltages of the switching transistors in the
The considered four schematics have been simulated to MV and hybrid power stage circuits: thanks to the stacked
compare their efficiency. For all the schematics in Fig. 1 the configuration, in both cases the VDS of the transistors stays
value of the inductance is 60 nH and the load capacitance is within their respective breakdown limits.
equal to 10 nF. The power efficiency has been simulated for Table I summarizes the results comparing the simulated
Iload ranging from 0 to 2 A, which is the common range in peak efficiencies and the maximum input voltages. A rough
these applications. An ideal voltage mode control [1] (VCM) estimation of the area consumption of each power stage
loop has been designed, to keep the output voltage of all the is calculated and added to the table in percentage terms,
four schematics fixed at 1.8 V for the efficiency evaluation, showing that the hybrid configuration (used as reference for
while Vin is 3.6 V for this comparison. A classical dead-time the percentages calculation) is not only the best in terms of
generation circuit has been added to the loop to avoid cross- peak efficiency, but also in area consumption, while the two
conduction currents in the power stages. MV solutions are the bulkiest. Notice that this is just a rough
Fig. 2 shows the resulting simulated power efficiency of estimation to have an idea of area comparison between the
the four schematics. As anticipated in the previous section, four circuits. Among the four solutions, the hybrid power
the lowest efficiency is obtained with the HV power stage stage has been chosen for further development, thanks to
(blue curve), that reaches a peak value of 72%. The efficiency the high efficiency improvement provided by the LV+MV
improvement is significant with the two-stacked MV power configuration.
stage (orange curve), peaking at 79%. Changing the low-side A comparison of the proposed hybrid LV+MV solution and
and high-side chains from MV to LV provides another slight the previously discussed state of the art circuits is summa-

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 TABLE I TABLE II
Performance summary and comparison of the proposed power stages. Performance comparison with previous art.

HV MV MV(LV driv) Hybrid LV+MV [4] [5] [6] Hybrid

Technology [µm] 1 0.4 0.4+0.12 0.12+0.4 Technology [µm] 0.18 0.04 0.045 0.12+0.4
Peak Efficiency 72% 79% 81% 86% Max. Vin [V] 3.6 3.6 ∼3.6 4
Area Estimation 118% 239% 205% 100% Peak Efficiency 87.8% 91%(meas.) 87.8% 86%
Switching Frequency [MHz] 97 100 240 100
Load current [mA] 250 150 150 1000
rized in Table II, showing that the proposed solution is still
competitive in terms of efficiency, while implementing longer
transistors and operating with much higher output currents,
with the additional advantage of a slightly higher maximum
input voltage.
Since 100 MHz is a very high switching frequency for a
buck converter with these specifications, a good compromise
between efficiency, area, and possible time-to-market could
be to lower the switching frequency to some tens of MHz.
Doing so, the efficiency would rise, and the area of the power
stage would decrease, at the expense of a larger inductor,
but it would still be smaller than the ones needed in the
conventional 1-2 MHz converters. Fig. 5 shows the simulated
power efficiency of the four power stages as a function of
the switching frequency. The load current, for all circuits, is
set to 1 A. From the figure, it is clear that the frequency Fig. 5. Simulated power stages efficiency as a function of the switching
frequency.
range with the highest efficiency is in the range 30-60 MHz,
reaching 89.7% for the LV+MV schematic, which proves to be
better than the other three in all the frequency sweep. Above them switching at a frequency of 100 MHz, with an input
60 MHz, the switching losses increase too much, degrading voltage of 3.6 V and an output current ranging from 0 to 2 A.
the efficiency. On the other side, conduction losses are the These specifications are taken from the usual post-regulated
cause for the efficiency drop at lower frequencies. Notice that applications in automotive. Each of the four schematics uses
the sizes of the transistors were optimized to maximize the different transistors, either in the power stage or in the pre-
efficiency in the 100-MHz condition, so the power efficiency is driver chains. All circuits except the HV one use a stacked
expected rise even further by re-optimizing the widths of both configuration for the power stage, to ensure high voltage
the power stages and the inverter chains for lower frequencies. operation without risking the breakdown of the transistors.
Among the four presented schematics, the hybrid LV+MV
IV. Conclusion
circuit has proven to be the best in terms of efficiency and
In this paper, the design and comparison of high switching area consumption, reaching a peak efficiency equal to 86%. A
frequency buck DC-DC converter power stages have been slower (30 to 60 MHz) solution of the same circuit could be
discussed. The four designed schematics are compared, all of studied re-optimizing the area to achieve higher efficiency and
faster time-to-market.
References
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Converter with 60/120-MHz Switching Frequency and 1-A Output Cur-
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[4] V. Kursun, G. Schrom, V. De, E. Friedman, and S. Narendra, “Cascode
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Fig. 4. Simulated drain voltages (VD ) of the hybrid and MV power stages.

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