Mukund Modi;

STANDARDS modimp@lakehurst.mil

Mixed-signal test bus,

embedded core test
efforts advance

This is the third article in a series on mulgation. The ideas and constructs on an output, the functional driver,
IEEE standards to keep you informed presented here are proposals accepted under command of the boundary-scan
about the status of all standards that by the working group and documented data register, drives these signals. The
affect design and test activities. First, in the ballot draft, though they may still ABM can capture the signal incident on
working group chair Adam Cron dis- change for technical or other reasons. the pin by comparing the signal’s value
cusses the status of the IEEE P1149.4, to a local threshold (VTH) and storing the
Mixed-Signal Test Bus. Then Yervant Current architecture digitized result as a bit in the boundary
Zorian, working group chair, reports on The current architecture defined by register. These features define what the
the status of the P1500, Embedded Core the P1149.4 standard has been crafted working group has termed dot 1 mode.
Test standardization effort. The IEEE over the years with attention to practi- Parametric measurement mode, on
Test Technology Technical Council cal details. Like 1149.1, it is a boundary the other hand, is what really sets this
(TTTC) sponsors both of these efforts. architecture, though it may be applied standard apart from its sibling, 1149.1.
E-mail any comments concerning the to core circuitry. A P1149.4-compliant The ABM allows each analog pin to
general interest of this column to device will have an analog boundary source a current or measure a voltage
Mukund Modi, who is serving as an edi- module (ABM) on every analog pin. at any other analog pin. Current is
tor and IEEE Standards Group vice chair, Figure 1 illustrates the ABM function- sourced from internal bus AB1 via con-
at modimp@lakehurst.navy.mil or phone ality. nection SB1. The voltage measurement
(732) 323-7002. For general test stan- Each ABM will be able to mimic the runs through SB2 to internal bus AB2.
dards information, contact TTTC Stan- functions of an 1149.1 boundary-scan While these testability features are acti-
dards Group chair Pat McHugh at cell. These capabilities include driving vated, the mission-mode circuitry
patrick.f.mchugh@lmco.com or phone logic 1 and logic 0 via the SH and SL con- inside the device may or may not be
(609) 338-5969. nections to a local VH and VL. Typically, disconnected from the pin via the SD

IEEE P1149.4, Mixed-Signal Test

Bus standard vTH vH vL
vG
The second round of balloting has −
completed on the IEEE P1149.4 stan- +
dard with complete success—100% SH SL SG
SD Analog
acceptance. The working group labored Core function
over a year to address the comments Core pin
resulting from the first ballot, and their disconnect SB1 SB2
efforts have paid off. The 50% larger doc-
ument has added material that improves Internal analog AB1
test bus AB2
clarity and defines circuit parameters.
This short update on the standard’s Test bus AT1
interface
current architecture outlines what has circuit AT2
changed since the first ballot. The stan-
dard is taking its final steps toward pro- Figure 1. Functionality of the analog boundary module.

APRIL–JUNE 1999 0740-7475/99/$10.00 © 1999 IEEE 5

STANDARDS

AB1 AB2 connection features required for the

standard’s calibration and parametric
measurement modes.
vH
S1 S2 vclamp
S9 S10 New definition
vL Figure 3 shows an example of “dis-
S3 S4 crete” internal impedances that may
stay connected even while the device
S5 S8 S7 S6
is disconnected from the core circuit-
+ − − +
vTH ry. Specifically, E1 through E5 may
remain connected, while E6 and E7
must be disconnected during para-
AT1 metric measurement modes in which
AT2 the device’s core circuitry is to be dis-
Provision for Bus connection connected and isolated from the pins.
interconnect testing and calibration
This revised definition of “core dis-
Figure 2. Test bus interfacing circuitry functions. connect” gives designers great flexibil-
ity in designing their I/O interfaces yet
maintains the standard’s integrity. The
standard has been designed with a goal
E3 E4
of within 1% measurement accuracy.
To maintain this goal and still give
designers freedom, impedances such
E7
E5 as E1 through E5 need only be docu-
ABM ABM mented in the device’s data sheet. The
F1 F2 system test software would then com-
(analog) (analog) prehend these discretes when calcu-
lating board stimulus and expected
E6 ABM E1
Core response values.
F4 F3
(digital) (analog)
Future activity
Digital boundary E2 The ballot draft will undergo small
module
revisions suggested by the balloters. It
VSS
will then be submitted to the IEEE for
its June RevCom meeting. This com-
Figure 3. Discrete internal impedances. mittee is expected to accept the sub-
mission and approve it as a standard.
The working group still has work to
feature. We’ll return to this shortly. ment, respectively. The AT1 and AT2 do, however, as revisions are expect-
The last connection required by the signals would be connected in parallel ed. These would include an update to
ABM, SG to VG, forms the current return to each device of similar power and the Boundary Scan Description
path for the analog measurements. VG ground scheme within a system. Language, with definitions to describe
need not be ground, but in most appli- Because of device signal frequency the new analog features of the 1149.4
cations it will be a likely choice for the ranges or other reasons, AT buses on standard. There are sure to be new
designer to use in providing a stable ref- the board may be segregated. twists and discoveries once the stan-
erence connection. Figure 2 shows the circuitry func- dard is put into practice. Anyone inter-
The addition of test resource pins tions required for interfacing the board- ested in learning more about, or taking
AT1 and AT2 to each IEEE P1149.4- level signals routed to the AT1 and AT2 part in, future efforts may contact
compliant device enables the analog pins to internal analog test buses AB1 Adam Cron, Synopsys Inc., chair, IEEE
signal stimulus to travel to and from the and AB2. The left half of the figure P1149.4 Mixed-Signal Test Bus Standard
chip. These pins are used for stimulus shows circuitry for emulating 1149.1 working group.
application and response measure- behaviors, while the right half shows continued on p. 93

6 IEEE DESIGN & TEST OF COMPUTERS

support efficient implementations. Standards
Mary Sheeran (Chalmers Univ. of continued from p. 6
Technology) and Satnam Singh a mode in which the test for the core
(Xilinx) presented Lava, an experi- Bibliography external logic can be supported.
mental tool for hardware design and IEEE Std 1149.1b-1994, Standard Test
verification. The tool has been used in Access Port and Boundary-Scan Leading industry players, including
several industrial projects. With Lava, Architecture, IEEE Standards Board, systems companies, EDA vendors, core
hardware circuits are described using New York, 1990. providers, IC manufacturers, and ATE
a simple functional programming lan- IEEE P1149.4 Mixed-Signal Test Bus work- vendors, are participating in IEEE
guage, with emphasis on the need to ing group home page, http://grouper. P1500. The working group holds five or
capture common patterns of connec- ieee.org/groups/1149/4/, Adam Cron, six meetings a year, often in conjunc-
tion between components. Their thesis Cyberspace, 1995-1999. tion with major conferences, that are
is that a simple, elegant language will open to anyone interested. One such
likely ease the designer’s task and IEEE P1500, Embedded Core Test meeting was at April’s VLSI Test
therefore increase productivity. standardization Symposium 99 and another is planned
Christer Svensson (Linkoping Univ.) The IEEE P1500 working group is for the 36th Design Automation
described the rapid increase of network pursuing a standard for testing embed- Conference (21-25 June 1999). The var-
electronics in many different applica- ded cores. To improve the efficiency of ious task forces carrying out the
tion areas: Internet, intranets, phone, both core providers and core users, this detailed work of P1500 are addressing
fax, TV, multimedia, conferencing, elec- standard should facilitate interoper- issues such as terminology and glos-
tronic commerce, and so on. He ability with respect to testing when sary, merged core requirements, link-
addressed the need for protocol pro- cores from different sources appear in ing, documentation, benchmarking,
cessing and switching at wire speed and one system-on-a-chip design. P1500 and industry deployment. The working
the challenges that hardware designers does not standardize the core’s inter- group’s goal is to have a first draft ver-
face in trying to satisfy this need. nal test methods or DFT, nor does it sion of its standard in December 1999.
Two large Swedish research activities define system-IC test integration and For more information on IEEE P1500,
were also presented. One is the optimization issues, such as the type of visit http://grouper.ieee.org/groups/
National Program on Integrated test pattern source, sink, or test access 1500/ or contact the working group
Electronics Systems, which involves 30 mechanism. Rather, the P1500 stan- chair, Yervant Zorian, at zorian@
PhD students and their supervisors from dard encompasses two main items: logicvision.com.
four major universities. The program
consists of three main research areas: ■ A standard Core Test Language IEEE 1445, Digital Test
generic techniques (low-power design, that is capable of expressing all Interchange Format
A/D converter, and embedded memo- test-related information to be trans- Under the sponsorship of IEEE SCC-
ry techniques), system-on-chip method- ferred from core provider to core 20 Test and Diagnosis for Systems, this
ology, and wireless access systems. The user. This includes not only the test standard was approved and published
second activity is a consortium on self- stimuli and expected responses, on 10 March 1999. The document pro-
test in embedded systems, which con- but also data on core-internal DFT, vides the basis for standardizing digital
sists of three university research groups test modes and protocols, fault information for use on automatic test
and three industrial partners. The con- coverage, and so on. The idea is to equipment. The digital test information
sortium’s aim is to develop efficient self- extend IEEE Std P1450 Standard consists of the unit-under-test model
test methodologies and tools to act as Test Interface Language (STIL) to information, stimulus and response,
an enabling technology for the design accommodate these specific core fault dictionary data, and probe data.
of embedded systems. test constructs. A copy of IEEE 1445 is available from
For more detailed information on ■ A standardized but configurable the IEEE Standards Department at
this conference or the next EDA-Traff, core test wrapper, which allows www.ieee.org/membership/standards.
contact the organizer, Anders easy integration of the core into a html, or phone (732) 562-2746.
Marcelius (anders.marcelius@vi.se), system chip design. In addition to a
Association of Swedish Engineering mode for normal operation, in
Industries, or Zebo Peng (zpe@ida. which it becomes transparent, the
liu.se), Linkoping University. wrapper should support a mode for
testing the core internally, as well as

APRIL–JUNE 1999 93