Error Detection and Correction
Error Detection and Correction
Definition
Error detection is the ability to detect the presence of
stream is
1 0 1 1 0 1 1 1 0
The transmitted electrical signal corresponding to this bit stream
and the received waveform are shown in Figure 1. Due to the noise
Note
010101001
In this case, the number of bit errors (the underlined bits) is 3. The
Studies indicate that even if 20% of the letters are missing, human
voice from one place to another. Studies indicate that even if the Bit
Error Rate is 10−3, the listener will be able to understand the speech.
Content errors
Content errors are the errors in the content of the message; a binary
data block are referred to as burst error and occur when the
Duration of noise
Transmit bit: 101100101……………01
Length of the burst error is defined from the first corrupted bit to
the last corrupted bit. For example, burst error in fig. below is 6 bits
Transmitted bit: 0 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1
path fails due to any reason (cut in channel), the signals are switched
burst error.
the same path. In the fig., packet 1and 2 goes via nodes as shown in
the figure. Packet 4 goes directly from source node to the destination
node. Packet 3 starts its journey from source node and follow other
route than packets 1, 2 and 4. Flow of these data packets from the
packet 1and 2.
the network.
expired packets.
eventually.
Thus, a packet may be delivered to a wrong destination, or may be
ERROR DETECTION
The three widely used techniques for error detection are
parity
checksum
PARITY
A parity bit is a basic way to check for errors in digital
data may be subjected to noise so that such noise can alter 0s (of
data bits along with parity bit is transmitted from transmitter to the
there is an error in the data. Thus, the Parity Bit it is used to detect
Even parity
The parity bit is adjusted so that the total number of 1s in the code,
including the parity bit, is even. If there are already an even number
of 1s, the parity bit is 0. If there are an odd number of 1s, the parity
bit is 1. Hence, if any error occurs, the parity check circuit will
Odd parity
number of 1s, the parity bit is 0. If it’s even, the parity bit is set to
1.
binary bit will have an even number of 1’s which will indicate an
error.
11100011
If one bit (or any odd number of bits) is erroneously inverted during
11000011
receiver.
At Receiver Side
After receiving the code word, total number of 1’s in the code
word is counted.
011
the transmission.
Performance
If two (or any even number) of bits are inverted due to error,
error.
Error is not detected (Even parity Check)
CHECKHSUM
steps-
Step-01:
At sender side,
complement arithmetic.
The value so obtained is called as checksum.
Step-02:
receiver.
Step-03:
At receiver side,
If m bit checksum is being used, the received data unit is
All the m bit segments are added along with the checksum
value.
checked.
transmission.
Case-02: Result ≠ 0
transmission.
retransmission.
Checksum Example
Suppose that the sender wants to send 4 frames each of 8 bits, where
The sender adds the bits. While adding two numbers, if there is a
After adding all the 4 frames, the sender complements the sum to
get the checksum, 11010011, and sends it along with the data
the incoming data into equal segments of n bits each, and all these
Important Notes-
Note-01:
Consider while adding the m bit segments, the result obtained
Then, wrap around the extra bits and add to the result so that
Note-02:
The checksum cannot detect all the errors. Checksum, for example,
easy.
converting all the 1s to 0s. Thus the 1’s complement of the sum
introduced into the segment. If one of the bits is a not zero, then we
know that errors have been introduced into the segment and discard
the data.
CYCLIC REDUNDANCY CHECK (CRC)
– Example: x2 + 1
CRC Generator
pattern.
following rule-
The power of each term gives the position of the bit and the coefficient
x + 1.
Procedure:
101100
4. Divide M(x) by P(x).
7. T(x) is transmitted.
no error detected.
At sender side,
A string of n 0’s is appended to the data unit to be transmitted.
CRC generator.
3. This is divided by P:
Transmission to Receiver
At receiver side,
generator.
Case-01: Remainder = 0
transmission.
the transmission.
retransmission.
Example 2
3. This is divided by P:
4. The remainder (R = 01110) is appended to M to give
T=101000110101110
which is transmitted.
errors.
and also an error detection code, which the receiver uses to check
period of time.