ECE3110J Electronic Circuits

Differential Amplifiers
Design of Analog CMOS Integrated Circuits, Chapter 4
Fundamentals of Microelectronics, Chapter 10

Yuljae Cho, PhD

Associate Professor
Joint Institute, SJTU
Need for Differential Circuits
Having learned the design of rectifiers and basic amplifier stages, a student A constructed the
circuit shown below to amplify the signal of a microphone. Unfortunately, the student observed
that the amplifier output contained a strong humming noise (a steady low-frequency component).

Small signal

Or MOSFET M1

Examining the output Vout = VCC – ICRC, we can identify two components: (1) the amplified
microphone signal and (2) the ripple waveform present on VCC.
To suppress the hum, we can increase C1, thus lowering the ripple amplitude. A potential issue is
that the required capacitor value may become prohibitively large if many circuits draw current from
the rectifier.

𝐓
*𝑽𝒓 ≅ 𝐕𝑷 − 𝟐𝐕𝐨𝐧
𝟐𝐑𝐂

Or MOSFET M1 and M2

Alternatively, we can modify the amplifier topology such that the output is insensitive to VCC.
Vout = VCC – ICRC implies that a change in VCC directly appears in Vout, fundamentally because both
are measured with respect to ground and differ by RCIC.
What if Vout is measured with respect to another point that itself experiences the supply ripple to
the same extent? It is thus possible to eliminate the ripple from the “net” output.

Or MOSFET M1 and M2

In the circuit above, the output is measured between nodes X and Y rather than from X to
ground. If VCC contains ripple (vr), both VX and VY rise and fall by the same amount and hence
the difference between VX and VY remains free from the ripple (vr).
 Or MOSFET M1 and M2

However, Q2 carries no signal, simply serving as a constant current source—improvement needed.

Overall, the above development serves as the foundation for differential amplifiers: the
symmetric CE stages provide two output nodes whose voltage difference remains free from the
supply ripple.
 Or MOSFET M1 and M2

In the circuit left, Q2 and RC2 remains idle, thereby wasting current. To improve the circuit, we
apply the input signal to the base of Q2. Unfortunately, the signal components at X and Y are in
phase, canceling each other as they appear in vX − vY.

vX = Avvin + vr; vY = Avvin + vr

Thus, vX – vY = 0.
For the signal components to enhance each other at the output, we invert one of the input
phases, obtaining
vX = Avvin + vr; vY = – Avvin + vr
Thus, vX – vY = 2Avvin

This topology provides twice the output swing by exploiting the amplification capability of
the duplicate stage. The circuit senses two inputs that vary by equal and opposite amounts and
generates two outputs that behave in a similar fashion. These waveforms are examples of
differential signals and stand in contrast to single-ended signals.
Single-Ended vs Differential Signals

A single-ended signal: Signal measured with respect

to the common ground and carried by one line.

Or MOSFET M1

A differential signal: Signal measured between two

nodes that have equal and opposite swings and is
thus carried by two lines.

Or MOSFET M1 and M2
The differential signals V1 and V2 vary by equal and opposite amounts around a fixed level and
have the same average (dc) level with respect to ground:
V1 = V0sin ωt + VCM; V2 = −V0sinωt + VCM.
V1 and V2 has a peak-to-peak swing of 2V0 and thus the differential swing is 4V0.

VCM, the dc voltage that is common to both V1 and V2, is called the common-mode (CM) level.
That is, in the absence of differential signals, the two nodes remain at a potential equal to VCM with
respect to the global ground.
While sensing and producing differential signals, the circuit above suffers from some drawbacks:
As the Vin,CM changes, so do the bias currents of M1 and M2, thus varying both the transconductance
of the devices and the Vout,CM level. The variation of the transconductance, in turn, leads to a change
in the small-signal gain.
 Output swing clipping
Available output swing
M2 off
→ VCM,out increase

Also, the departure of the Vout,CM level from its ideal value lowers the maximum allowable
output swings. For example, if the Vin,CM is excessively low, the minimum values of Vin1 and Vin2
may in fact turn off M1 and M2, leading to severe clipping at the output. Thus, it is important
that the bias currents of the devices have minimal dependence on the Vin,CM.
Differential Pair

A simple modification yields an elegant, versatile topology. In a differential pair, the sources of M1
and M2 are tied to a constant current source rather than to ground. The sum of the transistor
currents (ID1 + ID2) is equal to the tail current ISS, and are independent of Vin,CM.

Thus, if Vin1 = Vin2, the bias current of each transistor equals ISS/2 and the output common-mode
level is VDD − RD×ISS/2.
Differential-Mode (Qualitative Analysis)
(2)
(1) (3)
(2)
(1) (3)

(1) M1 is off and M2 is on by assuming that VTH is higher than the min. point
Vout1 = VDD as M1 is off while Vout2 = VDD – RDISS = VDD – RDID2

1
(2) When Vin1 = Vin2, both M1 and M2 on. ID1 = ID2 = ISS
2
𝟏
Vout1 = Vout2 = VDD – RDID1 = VDD – RDID2 = VDD – RDISS
𝟐

(3) M1 is on and M2 is off.

Vout1 = VDD – RDISS = VDD – RDID1 as M1 is off while Vout2 = VDD
 Highest Gain
Max
Most linear

Min

(1) Maximum and minimum levels at the output are well-defined, VDD and VDD – RDISS, and
independent of the input CM level.
(2) The small signal gain, the slope of Vout1-Vout2 vs Vin1-Vin2, is maximum for Vin1 = Vin2.
Differential-Mode (Quantitative Analysis)
(1) DC Analysis
λ=0
γ=0

ID1 + ID2 = ISS

Vout1 = V𝐷𝐷 − 𝑅𝐷1 𝐼D1 ; Vout2 = V𝐷𝐷 − 𝑅𝐷2 𝐼D2

Thus, 𝐕𝐨𝐮𝐭𝟏 − 𝐕𝐨𝐮𝐭𝟐 = 𝑅𝐷2 𝐼D2 − 𝑅𝐷1 𝐼D1 = 𝑹𝑫 (𝑰𝑫𝟐 − 𝑰𝑫𝟏 )

 λ=0
γ=0

ID1 + ID2 = ISS

Assuming that the circuit is symmetric, and M1 and M2 are in a saturation region,

VG = Vin1; VS = VP; VGS = Vin1 – VP → 𝑉𝑃 = Vin1 − VGS1

And similarly, 𝑉𝑃 = Vin2 − VGS2

Thus, 𝐕𝐢𝐧𝟏 − 𝐕𝐢𝐧𝟐 = 𝐕𝐆𝐒𝟏 − 𝐕𝐆𝐒𝟐

 λ=0
γ=0

ID1 + ID2 = ISS

𝐕𝐢𝐧𝟏 − 𝐕𝐢𝐧𝟐 = 𝐕𝐆𝐒𝟏 − 𝐕𝐆𝐒𝟐

1 W 2ID
As ID = μn Cox VGS − V𝑇𝐻 2 , VGS = W + 𝑉𝑇𝐻 and put it into VGS1 and VGS2
2 L μn Cox
L
 2ID
Vin1 − Vin2 = VGS1 − VGS2 where VGS = W + 𝑉𝑇𝐻
μn Cox L

2ID1 2ID2
Vin1 − Vin2 = −
W W
μn Cox μn Cox
L L

To find ID1 – ID2 (to get Gm), take square of the equation above

2
2ID1 2ID2 4ID1 ID2 2
Vin1 − Vin2 = + −2 = I − 2 ID1 ID2
W W W W SS
μn Cox μn Cox μn Cox μn Cox
L L L L

1 W
→ μn Cox Vin1 − Vin2 2 = ISS − 2 ID1 ID2
2 L
1 W
→ μn Cox Vin1 − Vin2 2 − ISS = −2 ID1 ID2 take square of it again
2 L
1 W 2
μ C V − Vin2 − ISS = −2 ID1 ID2 take square of it again
2 n ox L in1
2
1 W 4 2 W
μ C Vin1 − Vin2 + ISS − μn Cox Vin1 − Vin2 2 ISS = 4ID1 ID2
4 n ox L L

Where 4ID1 ID2 = 𝐼𝐷1 + 𝐼𝐷2 2 − (𝐼𝐷1 − 𝐼𝐷2 )2 from a quadratic equation
= 𝐼𝑆𝑆

2
1 W 2 W
μ C 4
Vin1 − Vin2 + ISS − μn Cox Vin1 − Vin2 2 ISS = ISS 2 − ID1 − ID2 2
4 n ox L L
= ΔVin = ΔVin = Δ𝐼in
 2
1 W 2 W
μ C 4
Vin1 − Vin2 + ISS − μn Cox Vin1 − Vin2 2 ISS = ISS 2 − ID1 − ID2 2
4 n ox L L
= ΔVin = ΔVin = Δ𝐼in

𝚫𝐈𝐃
𝐈𝐒𝐒
𝟏 𝐖 𝟒𝐈𝐒𝐒
𝐈𝐃𝟏 − 𝐈𝐃𝟐 = 𝛍𝐧 𝐂𝐨𝐱 𝚫𝐕𝐢𝐧 − 𝚫𝐕𝐢𝐧 𝟐
𝟐 𝐋 𝐖
𝛍𝐧 𝐂𝐨𝐱
𝐋 𝚫𝐕𝐢𝐧

If Vin1 = Vin2, ID1 – ID2 = 0 −𝐈𝐒𝐒

If 𝑉𝑖𝑛1 − 𝑉𝑖𝑛2 increases from zero, ID1 – ID2 also increases 𝟐𝐈𝐒𝐒 𝟐𝐈𝐒𝐒
−
𝐖 𝐖
𝛍𝐧 𝐂𝐨𝐱 𝐋 𝛍𝐧 𝐂𝐨𝐱 𝐋
 1 W 4ISS
ID1 − ID2 = μn Cox ΔVin − ΔVin 2
2 L W
μn Cox
L
4ISS 2
W − 2ΔVin
𝜕ΔID 1 W μn Cox L
Gm = = μ C
𝜕ΔVin 2 n ox L 4ISS 2
W − ΔVin
ID is Iout in the circuit μn Cox
L
 4ISS 2
W − 2ΔVin
𝜕ΔID (= 𝐼𝑜𝑢𝑡 ) 1 W μn Cox L
Gm = = μn Cox
𝜕ΔVin 2 L 4ISS 2
W − ΔVin
μn Cox 𝐖
L 𝛍𝐧 𝐂𝐨𝐱 𝐈𝐒𝐒 = 𝐠 𝒎𝟏,𝟐
𝐋
𝑾
At 𝛥𝑉𝑖𝑛 = 0, 𝑮𝒎 (𝑚𝑎𝑥) = μn Cox 𝑰
𝑳 𝑺𝑺
As 𝛥𝑉𝑜𝑢𝑡 = Vout1 – Vout2 = RDΔID = RDGmΔVin
𝑾
→ 𝑨𝒗 = 𝝁𝒏 𝑪𝒐𝒙 𝑰 𝑹
𝑳 𝑺𝑺 𝑫
2𝑰𝑺𝑺 2𝑰𝑺𝑺
𝐕𝐨𝐮𝐭𝟏 −𝐕𝐨𝐮𝐭𝟐 −
𝒐𝒓 𝐀𝐃𝐌 = = −𝐠 𝒎𝟏,𝟐 𝐑 𝐃 𝑾 𝑾
𝚫𝐕𝐢𝐧 μn Cox μn Cox
𝑳 𝑳

• Larger ISS leads to higher Gm and wider input range.

• Smaller W/L leads to lower Gm but wider input range.
(2) Small-signal analysis – Method 1. Superposition

λ=0 Using a superposition method

γ=0

Remove Vout2

𝟏
=
𝐠 𝒎𝟐

𝐑𝐃
𝛖𝐨𝐮𝐭𝟏 (𝒗𝑿 ) = − 𝛖𝐢𝐧𝟏
𝟏 𝟏
+
𝐠 𝒎𝟏 𝐠 𝒎𝟐
Using a superposition method

Remove Vout2

𝟏
=
𝐠 𝒎𝟐

𝐑𝐃
𝛖𝐨𝐮𝐭𝟏 (𝒗𝑿 ) = − 𝛖𝐢𝐧𝟏
𝟏 𝟏
+
𝐠 𝒎𝟏 𝐠 𝒎𝟐
Recall: Gain of degenerated CS stage
−iout
λ≠0 Vin Vout
+
γ≠0 υgs1 RD
ro1
−
υgs1 g 𝑚1 υsb1 g 𝑚𝑏1
Rs

υout 𝑅𝑜𝑢𝑡 (−𝑖𝑜𝑢𝑡 )

Av = = = −Gm R out
υin 𝑣𝑖𝑛
−g 𝑚1 ro1 R S + ro1 + g 𝑚1 + g 𝑚𝑏1 ro1 R S R D
= ∙
R S + ro1 + g 𝑚1 + g 𝑚𝑏1 ro1 R S R S + ro1 + g 𝑚1 + g 𝑚𝑏1 ro1 R S + R D
 Using a superposition method

Remove Vout1

VTH and RTH

Find Thevenin Eq. circuit

Using the small-signal model, we can find VTH = Vin1 and RTH = 1/gm1
 𝛖𝐨𝐮𝐭𝟐
RTH

𝛖𝐢𝐧𝟏

From the stage above, we get vout2

𝑹𝑫
𝝊𝒐𝒖𝒕𝟐 (𝒗𝒀 ) = 𝝊𝒊𝒏𝟏
𝟏 𝟏
+
𝐠 𝐦𝟏 𝐠 𝐦𝟐
Recall: Common gate

λ≠0
γ≠0 vgs vgsgm ro vsbgmb

Small Signal
+ RS

gm + g mb ro + 1
Av = R
ro + R S + gm + g mb ro R S + R D D
 λ=0
γ=0

𝐑𝐃 𝑹𝑫
𝛖𝐨𝐮𝐭𝟏 (𝒗𝑿 ) = − 𝛖𝐢𝐧𝟏 𝝊𝒐𝒖𝒕𝟐 (𝒗𝒀 ) = 𝝊𝒊𝒏𝟏
𝟏 𝟏 𝟏 𝟏
+ +
𝐠 𝒎𝟏 𝐠 𝒎𝟐 𝐠 𝐦𝟏 𝐠 𝐦𝟐

And thus, the overall voltage gain for vin1 is vX – vY

𝟐𝑹𝑫
=− 𝒗 = −𝐠 𝒎 𝑹𝑫 𝒗𝒊𝒏𝟏 if gm1 = gm2 = gm
𝟏 𝟏 𝒊𝒏𝟏
+
𝐠 𝐦𝟏 𝐠 𝐦𝟐
 2R D
υout1 −υout2 = − υin1 = −g m R D 𝝊𝒊𝒏𝟏
1 1
+
g 𝑚1 g 𝑚2

By the virtue of symmetry, the effect of vin2 at X and Y is identical to that of vin1 except for a
change in the polarities.
2R D
υout1 −υout2 = υin2 = g m R D 𝝊𝒊𝒏𝟐
1 1
+
g 𝑚1 g 𝑚2
𝛖𝐨𝐮𝐭𝟏 −𝛖𝐨𝐮𝐭𝟐
𝐀𝐃𝐌 = = −𝐠 𝐦 𝐑 𝐃
𝛖𝐢𝐧𝟏 −𝛖𝐢𝐧𝟐
 Example 1 Calculate the ADM of the differential pair below if the biasing conditions of M1 and M2
are the same.

2R D 4
υout1 −υout2 = − υin1 = − g m1 R D υin1
1 1 3
+
g m1 2g m1
2R D 4 𝛖𝐨𝐮𝐭𝟏 −𝛖𝐨𝐮𝐭𝟐 𝟒
υout1 −υout2 = υin2 = g m1 R D υin2 𝐀𝐃𝐌 = = − 𝒈𝒎𝟏 𝐑 𝐃
1 1 3 𝛖𝐢𝐧𝟏 −𝛖𝐢𝐧𝟐 𝟑
+
g m1 2g m1
Example 1

W
𝑔𝑚 = 2µnCox ′ ID
L
(2) Small-signal analysis – Method 2. Half circuit

If a fully-symmetric differential pair senses differential inputs, then the concept of ‘half circuit’
can be applied.

Input VG changes Corresponding VGS changes

Lemma. D1 and D2 represent any three terminal active device. Suppose Vin1 and Vin2 change
differentially, the former changes from V0 to V0 + ΔVin and the latter from V0 to V0 − ΔVin. Then,
if the circuit remains linear, VP does not change. Assume λ = 0.
*Lemma proof

Input VG changes Corresponding VGS changes

V1 (VGS1) = Va + ΔV1, V2 (VGS2) = Va – ΔV2. Then, the output currents change by gmΔV1 (ΔI1)
and – gmΔV2 (ΔI2).

Since the current is constant I1 + I2 = IT, the sum of changes gmΔV1 – gmΔV2 = 0
→ ΔV1 = ΔV2 .
*Lemma proof (continue)

Input VG changes Corresponding VGS changes

Vin1 = V0 + ΔVin
VP

Because Vin1 – Vp = V1 (= VGS1) and Vin2 – Vp = V2 (= VGS2), we get Vin1 – V1 = Vin2 – V2

From the bias condition we have, (i) Vin1 = V0 + ΔVin; (ii) Vin2 = V0 − ΔVin; (iii) V1 = Va + ΔV1;
and (iv) V2 = Va − ΔV2. Insert these into the equation in green Vin1 − V1 = Vin2 − V2

we get V0 + ΔVin − (Va + ΔV1) = V0 − ΔVin − (Va − ΔV2).

*Lemma proof (continue)

Input VG changes Corresponding VGS changes

Vin1 = V0 + ΔVin
VP

From V0 + ΔVin − (Va + ΔV1) = V0 − ΔVin − (Va − ΔV2), blue cancels out.

2ΔVin = ΔV1 + ΔV2.

Because ΔV1 = ΔV2, 2ΔVin = 2ΔV1.

if Vin1 and Vin2 change by +ΔVin and −ΔVin, respectively, then V1 and V2 change by the same
values. Since VP = Vin1 − V1, and since V1 exhibits the same change as Vin1, VP does not change.
Since VP experiences no change, node P can be considered as ac ground, and the circuit can be
decomposed into two separate halves.

We can write VX/Vin1 = −gmRD and VY /(−Vin1) = −gmRD. Thus, (VX − VY)/(2Vin1) = −gmRD.
If two inputs are not fully differential, we can adjust inputs as shown below.

The circuit senses a combination of a differential input and a common-mode variation.

Therefore, the effect of each type of input can be computed by superposition, with the half-
circuit concept applied to the differential-mode operation.
Example 2 Calculate the differential gain of the circuit below.

Differential-Mode Response, Input is symmetry

λ≠0
γ≠0

+Vin1 -Vin1

𝛖𝐨𝐮𝐭𝟏 − 𝛖𝐨𝐮𝐭𝟐
𝐀𝐃𝐌 = = −𝐠 𝐦 𝐑 𝐃 ∥ 𝐫𝐨
𝟐𝛖𝒊𝒏𝟏
Example 2 Calculate the differential gain of the circuit below.

Differential-Mode Response, Input is asymmetry

λ≠0
γ≠0

𝛖𝒊𝒏𝟏 − 𝛖𝒊𝒏𝟐 𝛖𝒊𝒏𝟐 − 𝛖𝒊𝒏𝟏

2 2

𝛖𝐨𝐮𝐭𝟏 − 𝛖𝐨𝐮𝐭𝟐
𝐀𝐃𝐌 = = −𝐠 𝐦 𝐑 𝐃 ∥ 𝐫𝐨
𝛖𝒊𝒏𝟏 − 𝛖𝒊𝒏𝟐
Example 2 Calculate the differential gain of the circuit below.

Common-Mode Response (ideal)

𝐕𝐢𝐧,𝐂𝐌

If the circuit is fully symmetric, the current drawn by M1 and M2 is ISS/2 and is independent of Vin,CM.
This means that Vout1 and Vout2 do not change by Vin,CM, leading to zero gain.
𝛖𝐨𝐮𝐭𝟏 − 𝛖𝐨𝐮𝐭𝟐
𝐀𝐂𝐌−𝐃𝐌 = =𝟎
𝛖𝐢𝐧,𝐂𝐌
Common-Mode Response (Non-ideal)
An example in previous slide shows an idealized case of a common-mode response. In reality,
neither is the circuit fully symmetric nor does the current source exhibit an infinite output
impedance. As a result, a fraction of the input CM variation appears at the output.

Case 1. Finite output impedance and symmetric circuit

λ=0
γ=0
 λ=0
γ=0

VP is now affected by changes in Vin,CM due to RSS. However, due to the symmetry, VX remains
equal to VY. Thus, we can view the circuit as two parallel transistor circuits.
1 W 2
ID = µnCox VGS − VTH × 2 and the same for the transconductance gm × 𝟐
2 L

𝑅𝐷
ൗ2
From small-signal model, we get 𝐴𝑣,𝐶𝑀 = − 1
ൗ2𝑔𝑚 +𝑅𝑆𝑆
Recall: Gain of degenerated CS stage
−iout
λ≠0 Vin Vout
+
γ≠0 υgs1 RD
ro1
−
υgs1 g 𝑚1 υsb1 g 𝑚𝑏1
Rs

υout 𝑅𝑜𝑢𝑡 (−𝑖𝑜𝑢𝑡 )

Av = = = −Gm R out
υin 𝑣𝑖𝑛
−g 𝑚1 ro1 R S + ro1 + g 𝑚1 + g 𝑚𝑏1 ro1 R S R D
= ∙
R S + ro1 + g 𝑚1 + g 𝑚𝑏1 ro1 R S R S + ro1 + g 𝑚1 + g 𝑚𝑏1 ro1 R S + R D
Example 3 The circuit uses a resistor rather than a current source to define a tail current of 1
mA. Assume that (W/L)1,2 = 25/0.5, μnCox = 50 μA/V2, VTH = 0.6 V, λ = γ = 0, and VDD = 3 V.
(a) What is the required input CM voltage for which RSS sustains 0.5 V?
Example 3 The circuit uses a resistor rather than a current source to define a tail current of 1
mA. Assume that (W/L)1,2 = 25/0.5, μnCox = 50 μA/V2, VTH = 0.6 V, λ = γ = 0, and VDD = 3 V.
(b) Calculate RD for a differential gain of 5. Assume there is a constant current 1 mA at RSS.
Example 3 The circuit uses a resistor rather than a current source to define a tail current of 1
mA. Assume that (W/L)1,2 = 25/0.5, μnCox = 50 μA/V2, VTH = 0.6 V, λ = γ = 0, and VDD = 3 V.
(c) What happens at the output if the input CM level is 50 mV higher than the value calculated
in (a)?
Case 2. Finite output impedance and asymmetric circuit

λ=0
γ=0

𝑅𝐷ൗ
2
As Vin,CM increases, output will change according to 𝐴𝑣,𝐶𝑀 =−
1ൗ
2𝑔 + 𝑅𝑆𝑆
𝑚
However, due to asymmetry in RD,
𝑔𝑚 𝑅𝐷
∆𝑉𝑋 = −∆𝑉𝑖𝑛,𝐶𝑀 𝒈𝒎 ∆𝑹𝑫 Common-mode input introduces
1+2𝑔𝑚 𝑅𝑆𝑆
𝑔 (𝑅 +∆𝑅 )
𝑨𝑪𝑴−𝑫𝑴 =
∆𝑉𝑌 = −∆𝑉𝑖𝑛,𝐶𝑀 𝑚 𝐷 𝐷 𝟏 + 𝟐𝒈𝒎 𝑹𝑺𝑺 differential component at the output
1+2𝑔𝑚 𝑅𝑆𝑆
A common-mode change at the input introduces a differential component at the output →
common-mode to differential conversion.

If the input of a differential pair includes both a differential signal and common-mode noise, the
circuit corrupts the amplified differential signal by the input CM change.
Case 3. Asymmetry resulting from mismatches between M1 and M2
λ=0
γ=0

Due to dimension and threshold voltage mismatches, the two transistors carry slightly
different currents and exhibit unequal transconductances. As ID = gmVGS, ID1 = gm1(Vin,CM –
VP) and ID2 = gm2(Vin,CM – VP).

Because (ID1 + ID2)RSS = VP → VP = (gm1 + gm2)(Vin,CM – VP)RSS

 (g m1 + g m2 )𝑅𝑆𝑆
VP = V
(g m1 + g m2 )𝑅𝑆𝑆 + 1 in,CM
Output voltage (Vout1 or VX) becomes
−𝐠 𝐦𝟏
𝑽𝑿 = 𝑽𝑫𝑫 − 𝑔𝑚1 𝑉𝑖𝑛,𝐶𝑀 − 𝑉𝑃 𝑅𝐷 = 𝑽𝑫𝑫 + 𝑹𝑫 𝑽𝒊𝒏,𝑪𝑴
(g m1 +g m2 )𝑹𝑺𝑺 + 𝟏
−𝐠 𝐦𝟐
Similarly, 𝑽𝒀 = 𝑽𝑫𝑫 + 𝑹 𝑽
(𝐠𝐦𝟏 +𝐠𝐦𝟐 )𝑹𝑺𝑺+𝟏 𝑫 𝒊𝒏,𝑪𝑴

gm1 −gm2 ∆𝐠 𝐦
Finally, we get 𝑉𝑋 − 𝑉𝑌 = − 𝑅 𝑉 or, 𝑨𝑪𝑴−𝑫𝑴 = − 𝑹
(gm1+gm2)𝑅𝑆𝑆+1 𝐷 𝑖𝑛,𝐶𝑀 (𝒈𝒎𝟏+𝒈𝒎𝟐)𝑹𝑺𝑺+𝟏 𝑫
Differential-Mode (Small-Signal, Superposition)

λ=0
γ=0

RSS

𝟏
𝐑𝐒 = ∥ 𝐑 𝐒𝐒
𝐠 𝐦𝟐

𝐑𝐃
Referring to DM without RSS, we can get vout1 𝛖𝐨𝐮𝐭𝟏 = − 𝛖𝐢𝐧𝟏
𝟏 𝟏
𝐑𝐃 + ∥ 𝐑 𝐒𝐒
𝐠 𝒎𝟏 𝐠 𝒎𝟐
𝛖𝐨𝐮𝐭𝟏 (𝒗𝑿 ) = − 𝛖𝐢𝐧𝟏
𝟏 𝟏
+
𝐠 𝒎𝟏 𝐠 𝒎𝟐
 As we saw previously

VTH = Vin1
RTH = 1/gm1

VTH and RTH RSS

Find Thevenin Eq. circuit

𝑅𝑆𝑆
g m1 g m2 R SS 1 𝑅𝐷
Gm = 𝑅𝑆𝑆 +
1 + g m1 R SS + g m2 R SS 𝑔𝑚2
𝑜𝑟 𝜐𝑜𝑢𝑡2 = 𝜐𝑖𝑛1
1 1
+ ∥ 𝑅𝑆𝑆
R out = 𝑅𝐷 𝑔𝑚1 𝑔𝑚2
VTH = Vin1
RTH = 1/gm1

RSS

g m1 g m2 R SS
Gm =
1 + g m1 R SS + g m2 R SS

R out = 𝑅𝐷
𝑅𝑆𝑆
1 𝑅𝐷
𝑅𝑆𝑆 +
𝑔𝑚2
𝑜𝑟 𝜐𝑜𝑢𝑡2 = 𝜐𝑖𝑛1
1 1
+ ∥ 𝑅𝑆𝑆
𝑔𝑚1 𝑔𝑚2
From Vin1 we have
g 𝑚1 + 2R SS g 𝑚1 g 𝑚2 R D
υout1 −υout2 = − υin1
1 + g 𝑚1 + g 𝑚2 R SS
From Vin1 we have
g 𝑚1 + 2R SS g 𝑚1 g 𝑚2 R D
υout1 −υout2 = − υin1
1 + g 𝑚1 + g 𝑚2 R SS

From Vin2 we have

g 𝑚2 + 2R SS g 𝑚1 g 𝑚2 R D
υout1 −υout2 = υin2
1 + g 𝑚1 + g 𝑚2 R SS

υout1 −υout2 g m1 + g 𝑚2 + 4R SS g 𝑚1 g 𝑚2 𝑹𝑫
≈− ൗ𝟐
𝑣𝑖𝑛1 − 𝑣𝑖𝑛2 1 + g 𝑚1 + g 𝑚2 R SS
For meaningful comparison of differential circuits, the undesirable differential component
produced by CM variation must be normalized to the wanted differential output.

Common-mode rejection ratio, or CMRR, is defined as

𝑨𝑫𝑴
𝑪𝑴𝑹𝑹 =
𝑨𝑪𝑴−𝑫𝑴

g m1 + g 𝑚2 + 4R SS g 𝑚1 g 𝑚2 𝑅𝐷
𝐴𝐷𝑀 = ൗ2
1 + g 𝑚1 + g 𝑚2 R SS g m1 + g 𝑚2 + 4R SS g 𝑚1 g 𝑚2
=
2(g m1 − g m2 )
g m1 − g m2
𝐴𝐶𝑀−𝐷𝑀 = 𝑅𝐷
(g m1 +g𝑚2)𝑅𝑆𝑆 + 1

The CMRR of a differential amplifier is a metric used to

quantify the ability of the device to reject common-mode
signals. An ideal differential amplifier would have infinite
CMRR, however this is not achievable in practice
Common-Mode + Differential-Mode

Not necessarily fully

differential

𝛖𝐨𝐮𝐭𝟏 − 𝛖𝐨𝐮𝐭𝟐 𝛖𝐨𝐮𝐭𝟏 − 𝛖𝐨𝐮𝐭𝟐

𝐀𝐃𝐌 = 𝐀𝐂𝐌−𝐃𝐌 =
𝒗𝒊𝒏𝟏 − 𝒗𝒊𝒏𝟐 𝛖𝐢𝐧,𝐂𝐌
𝛖𝐨𝐮𝐭,𝐂𝐌 𝐀𝐃𝐌
𝐀𝐂𝐌 = 𝐂𝐌𝐑𝐑 =
𝛖𝐢𝐧,𝐂𝐌 𝐀𝐂𝐌−𝐃𝐌
Example 4 The differential pair shown below must achieve a CMRR of 60 dB ( = 1000). Assume a
power budget of 2 mW (VDD×Itotal), a nominal differential voltage gain of 5, and neglect channel-
length modulation in M1 and M2, compute the minimum required λ for M3 (Only for M3). Assume
the virtual ground concept applies at node P for the differential voltage gain.

Use parameters W/L for both M1 and M2 = 10/0.18, 𝜇𝑛 𝐶𝑜𝑥 = 100 𝜇𝐴/𝑉 2 , VDD = 1.8 V, ΔR/R = 2%,
and ID1 = ID2 = ID3/2.
 𝛖𝐨𝐮𝐭𝟏 − 𝛖𝐨𝐮𝐭𝟐
𝐀𝐃𝐌 = = −𝐠 𝐦 𝐑 𝐃 ∥ 𝐫𝐨
𝛖𝒊𝒏𝟏 − 𝛖𝒊𝒏𝟐

∆𝐠 𝐦
𝑨𝑪𝑴−𝑫𝑴 =− 𝑹
(𝒈𝒎𝟏 + 𝒈𝒎𝟐 )𝑹𝑺𝑺 + 𝟏 𝑫
Additional example. Compute the common-mode rejection ratio of the stage below. For simplicity,
neglect channel-length modulation in M1 and M2 but not in other transistors. A half circuit concept
can be applied for ADM. gm = gm1 = gm2