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Iisc Soniya S Mtech Mvlsi

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PRERAK GUPTA
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66 views1 page

Iisc Soniya S Mtech Mvlsi

Uploaded by

PRERAK GUPTA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Soniya S ƒ +91-9486007524

\ live:.cid.f684c2c050f0d06 # soniyas@iisc.ac.in
ï Soniya S # soniyasegar24@gmail.com

Education
• Indian Institute of Science, Bangalore, India. Aug’22-Present
M.Tech - Microelectronics and VLSI Design CGPA: 8.1/10

• Pondicherry Engineering College, Puducherry, India. Aug’15-Apr’19


B.Tech - Electronics and Communication Engineering CGPA: 8.7/10

• Aditya Vidhyashram Higher Secondary School, Puducherry, India. May’15


XII std - Tamil Nadu Board of Education Percentage: 97.17/100

• Aditya Vidhyashram Residential School, Puducherry, India. May’13


X std - Central Board of Secondary Education CGPA: 10/10

Academic Projects
• RISC V Architecture Design for TinyML Applications M.Tech Project
This project aims at designing customized architecture for low-cost, low-power implementation of convolutional neural Ongoing
networks using common subexpression elimination (CSE) optimization technique. Tech: Python, Verilog. Mentors: Prof.
Chetan Singh Thakur, Dr. Mahesh Mehendale.
• Design and Implementation of 16-bit RISC based Multi-cycle CPU Course Project
Designed, implemented and verified a 16-bit multi-cycle RISC processor with custom instruction set supporting arith- Aug’23
metic, logical, and branch instructions. The design was verified in Basys-3 FPGA board with an algorithm to find the
maximum number from a set of ten random numbers. Tech: Verilog, Xilinx Vivado, Basys-3.
• Design of 32-bit Single Precision IEEE-754 format Floating-point Arithmetic unit Course Project
Designed and implemented a unit that performs addition, subtraction, and multiplication of 32-bit Single Precision IEEE- Apr’23
754 format (MSB sign bit, 8-bit exponent, 23-bit significand) floating point numbers. Tech: Verilog, Xilinx Vivado.

• RTL Design of Asynchronous FIFO Course Project


Designed and implemented Asynchronous FIFO that transfers data between two modules working at two different clock Apr’23
domains. Tech: Verilog, Xilinx Vivado.
• Design and Implementation of Variable Frequency Sine-wave Generator using CORDIC Algorithm Course Project
Designed, implemented and verified sine waveform generator (for variable frequency) based on 12-stages pipelined Apr’23
CORDIC (COordinate Rotation DIgital Computer) Algorithm. The design was verified in Basys-3 FPGA board. Tech:
Verilog, Xilinx Vivado, Basys-3.
• Implementation of Schematic and Layout of 8x8 Unsigned Radix4 Booth Multiplier Course Project
Designed and implemented the transistor-level schematic and layout of 8-bit integer multiplier based on Radix4 Booth Nov’22
Recoding Algorithm. Tech: Cadence Virtuoso.
Skills
• Hardware Description Language: Verilog
• Programming Language: C, Python, MATLAB
• CAD Tools: Xilinx Vivado, Cadence Virtuoso
• FPGA/Microcontroller: Digilent Basys-3 FPGA board(xc7a35tcpg236-1), Arduino
• Soft Skills: Leadership, Event Management, Public Speaking, Communication
Relevant Academic Courses
• Digital VLSI Circuits • Digital System Design with FPGAs
• Hardware Acceleration and Optimization for ML • Processor System Design

Positions of Responsibility
• Placement coordinator for Internship placement drive, DESE, IISc for the duration Jan-May, 2023.
• Secretary of Students’ Council, ECE, PEC for the academic year 2018-2019.
• Joint Secretary of Literary Club, PEC for the academic year 2018-2019.
• Class Representative, ECE, PEC for the academic year 2016-2017.
Achievements and Awards
• Obtained GATE AIR 233 (EC) in 2022.
• Received "Above and Beyond Explorer Award" for the Project, “Safety Glove for Women” in PEC in 2017.
Hobbies
• Chess • Badminton • Yoga • Modern Cooking

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