Hariri Canadian University

Faculty of Engineering
Electrical And Computer engineering Department
CCEE 213 Computer Architecture

Final

Thursday, May 3rd, 2007

Name ________________________________________

ID _________________________
Duration: 120 minutes.

Instructions:
9 Check to insure that you have a
complete copy of the examination.
There are 4 Questions, and a total
of 10 pages. There should be no
blank pages in your set.
Question 1
30 9 This examination is open book and
open notes.
Question 2 9 Questions are NOT allowed
30 during the exam.
Question 3 9 No use of scratch paper is
30 allowed. You should work your
Questions directly on the Question
Question 4 statement sheet in the appropriate
30 space only. You may use the
backside of the exam sheets as
Total Grade appropriate.
120
9 It is recommended that you read
the whole exam before attempting
any one Question.
9 Include all steps and calculations
as appropriate for maximum
credit. Be clear, brief, and
specific in your answers.
Good Luck!
Question 1: (30 points)
Given the following MIPS assembly program, write, next to each line, what kind of
hazard (structural, data, control) do you expect if the code was run on the 5 stage
pipeline of the book. Also indicate what solution would you use for each hazard and
whether you will need stall cycles and how many.
Number of
Instruction Hazard Solution
Stall cycles
add $t0,$a0,$0
add $t1,$0,$0
L1: lb $t2,0($t0)
beq $t2,$0,L2
addi $t1,$t1,1
addi $t0, $t0, 1
j L1
L2: beq $t1,$0,END0
add $t0,$a1,$0
add $t3,$0,$0
L3: lb $t2,0($t0)
beq $t2,$0,L4
addi $t3,$t3,1
addi $t0, $t0, 1
j L3
L4: beq $t3,$0,END0
slt $t0,$t3,$t1
bne $t0,$0,END0
sub $t0,$t3,$t1
add $v0,$a1,$t0
L5: addi $t0,$v0,$0
addi $t1,$a0,$0
L6: lb $t2,0($t0)
lb $t3,0($t1)
beq $t3, $0, END
bne $t2,$t3,L7
addi $t0,$t0,1
addi $t1,$t1,1
j L6
L7: addi $v0,$v0,-1
slt $t0,$v0,$a1
j L5
END0: add $v0,$0,$0
END: jr $ra
Question 2: (30 points)
A. The following MIPS instruction sequence can be used to implement
a MIPS pseudo instruction. Give the instruction a name and
describe what it does. The register $11 is the input register and $10
is the output register.
addu $10,$0,$11
bge $11,$0, next
sub $10,$0,$11
next: . . .

B. The IBM PowerPC supports several additional addressing modes

beyond that of the MIPS. One, called indexed addressing, adds the
values stored in two registers (whose register file addresses are
contained in the instruction) together to form the memory address
of the operand. If this were an addressing mode supported in the
MIPS, what instruction format (R, I, or J) would it be?

Complete the diagram below to illustrate lw with indexed

addressing.

op
Memory
word or byte operand

Read Addr 1
Read
Register
Read Addr 2 Data 1
File
Write Addr
Read
Data 2
Write Data

C. Show how the bit string for +2010 would be stored in memory if
represented in a format similar to the MIPS floating point format
except with only 3 bits of exponent (and a bias of 3) and only 4 bits
of fraction.

CCEE 213 Computer Architecture – Final Spring 2006-2007 3-May-2007 3

 D. The following are the five steps (in random order) that need to be
performed to add two floating point operands, F1x2E1 and F2x2E2.
Give the proper step order.

Proper order: ___________________________________________

1. Normalize F3
2. Insert a 1 as the most significant bit of F1 and F2
3. Add F2 to F1 to form F3
4. Strip off the most significant bit of F3
5. Round F3
6. Align F2 with F1

E. Compare the performance of four different MIPS implementations

for a sequence of ten independent add instructions (i.e., with no
data hazards). In the case of the pipelined machines, assume the
pipeline is initially empty.
a. a single cycle machine with a 10 nsec clock,
b. a multi-cycle machine with a 2 nsec clock,
c. a five stage pipelined machine with a 2 nsec clock

1 – total time for the single cycle machine to complete

2 – total time for the multi-cycle machine to complete

3 – total time for the five stage pipelined machine to complete

CCEE 213 Computer Architecture – Final Spring 2006-2007 3-May-2007 4

 Question 3: (30 points):
The MIPS ISA is modified to add an is1 instruction. The is1
(increment and skip on one) increments (by 1) the contents of a
register, stores the incremented value back in the register, and skips
the next instruction if the result of the incrementing is 1. All other
instructions remain unchanged.

A. Show the minimum changes – additions and/or deletions of hardware

components (e.g., muxes) and interconnects – that need to be made to
the single cycle MIPS datapath shown on the next page to
accommodate this modification.

B. What new or expanded (in terms of number of bits) control signals

will need to be added, if any?

C. What old control signals can be eliminated or reduced, if any?

D. Give the setting for the control signals to execute the modified
instruction. Use an X to indicate a don’t care signal and a – to
indicate a control signal that has been eliminated. For ALUOp, just
indicate the arithmetic operation that needs to be performed (e.g.,
add, and, …). Use the blank space to give the setting for any control
signals that you had to add to the datapath.

Reg ALU ALU Branch Mem Mem Reg Memto

Dst Op Src Read Write Write Reg
isz

CCEE 213 Computer Architecture – Final Spring 2006-2007 3-May-2007 5

 0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

CCEE 213 Computer Architecture – Final

RegWrite
RegDst

Instr[25-21] Read Addr 1

Instruction Address
Memory Register Read
Instr[20-16] Read Addr 2 Data 1 zero
Read Data
PC Instr[31-0] 0 File ALU Memory Read Data 1
Address

Spring 2006-2007
Write Addr Read
1 0
Instr[15-11] Write Data Data 2 Write Data 0
1

3-May-2007
Instr[15-0] Sign ALU
16 Extend 32 control

Instr[5-0]

6
 E. What is the CPI of the unmodified machine?

F. What is the CPI of the modified machine?

G. This change may have some performance trade-offs. In addition to

changing the instruction count, the clock period may also be affected.
If the modified machine has a clock period 10% longer than that of
the unmodified machine, what is the largest increase in instruction
count that can be tolerated (i.e., that would still result in the modified
machine having the best performance)?

CCEE 213 Computer Architecture – Final Spring 2006-2007 3-May-2007 7

 Question 4: (30 points)
A. Consider the six stage pipelined datapath shown below. Assume
that the first instruction (the top row) is an R type instruction (e.g.,
add $2,$1,$3). Show all data hazards by drawing lines from
the earliest point in the pipeline that the data is produced by this
instruction to the latest point that the data is consumed for
subsequent dependent instructions. Indicate, by labeling each line,
which can be solved with data forwarding and from which pipeline
stage the forwarding is done (e.g., DF-EX/M) and which incur a
hazard along with the hazard length in cycles (e.g., H-2).

I1 I2 ID EX M WB

I1 I2 ID EX M WB

I1 I2 ID EX M WB

B. Do the same for all remaining producer-consumer instructions that

have data hazards (assume that the producer instruction is issued in
the first row and indicate the type of producer-consumer
instructions you are considering).

I1 I2 ID EX M WB

I1 I2 ID EX M WB

I1 I2 ID EX M WB

C. How can hazards like the ones above be handled (give all options)?

D. How many delay slots (stall cycles) are incurred in this six stage
pipeline if the branch decision hardware is implemented as in the
five stage MIPS pipeline shown on the next page?

CCEE 213 Computer Architecture – Final Spring 2006-2007 3-May-2007 8

 PCSrc

0 ID/EX
EX/MEM

IF/ID Control

Add MEM/WB
Branch
4 Shift Add

CCEE 213 Computer Architecture – Final

left 2
Instruction Read Addr 1
Read Data
Memory RegisterData 1 Memory
Read Addr 2 zero
Read Read

PC
Address File
Write Addr ALU Address 1
Read Data
1
Data 2 Write Data 0
Write Data
0

Spring 2006-2007
ALU
16 Sign 32 cntrl
Extend

3-May-2007
1
Forward
Unit

9
 E. What is the minimum number of delay slots that could be achieved
by moving the branch decision hardware as early in the pipeline as
possible?

F. Can the hazard in the MIPS code shown below be handled by

forwarding on the five stage MIPS pipeline discussed in class?

lw $2, 400($3)
sw $2, 800($4)

G. If so, add the additional forwarding logic to datapath on the

previous page (the Forward Unit shown is to handle the data hazard
discussed in class). If not, add the hazard logic to the MIPS
pipelined datapath and state how many stalls cycles are incurred.

H. Consider the loop code shown below running on the five stage
MIPS pipeline discussed in class.

loop: lw $2,50($3)
addi $1,$1,1
addi $3,$3,4
add $4,$2,$4
bne $1,$5,loop

If $1 is initially 0 and $5 is 3 (i.e., the loop is executed three

times), how many cycles are incurred if the following branch
prediction schemes are used for both a branch penalty of three
cycles and a branch penalty of one cycle. Assume for each, if the
prediction is successful that the branch penalty is reduced to zero.

Three cycle penalty One cycle penalty

Static, not taken
Static, taken
Dynamic, 1-bit
initial state is not
taken

CCEE 213 Computer Architecture – Final Spring 2006-2007 3-May-2007 10