2024 Aut Oct8 Drone Design
2024 Aut Oct8 Drone Design
EE and ME Departments
IIT Bombay, Mumbai
Making a Drone
2 Block Diagram
3 Terminology
Bill of Materials
LIPO
UBEC
Joystick Battery
5V/3A
Controller User Commands 11.1 V
Vin D4 Vin
D8
Rx
D9
All Gnd pins
D2
D10
D1 D4 ESC 1 M1
WiFi D11
Node MCU (PWM) D5
ESC 2 M2
ARDUINO
PRINTED NANO D6
5V ESC 3 M3
ANTENNA
SDA
VCC A4 D7
ESC 4 M4
MPU 6050 A5
SCL
Sensor Data through I2C
Terminology
It is useful to understand terms which are frequently used for flying and
sailing objects. Consider an object flying along the x direction.
Yaw: is rotation around the vertical axis.
(Left and right turn from the
direction of motion). Yaw
z
Roll: is rotation around the direction of y
motion (x axis).
Roll
(Movement of wing tips in x
5 Calibration
6 Motion Control
Measuring Acceleration
x
Accelerometers actually measure
force. Then a = F /m.
One way of measuring acceleration
is through the use of an inertial
mass.
Acceleration
The frame (shown hashed) is rigidly coupled to the moving body.
There is an inertial mass which is constrained to move along the
direction of motion. It is fixed to the frame through a spring.
As the body accelerates to the right, it leaves the inertial mass behind,
stretching the spring by x. Then,
k
−ma = kx so a = − x
m
Academic Year: 2024-2025, Semester: I (Au
(IIT B) Let’s Make a Drone 15 / 74
Sensors Accelerometers
Coriolis Force
Coriolis Force
Consider an object moving from point P1
Axis
to point P2 on a spinning spherical body
like the Earth.
P2
When viewed from a static frame outside P1
the spinning body, the object has a
velocity from West to East, which is
maximum near the equator and zero at R
Coriolis Force
Coriolis force has been known for a long time.
An interesting aside . . .
Here is a quote from the Wikipedia:
“In 1674, Claude Francois Milliet Dechales described in
his Cursus seu Mundus Mathematicus how the rotation of
the Earth should cause a deflection in the trajectories of both
falling bodies and projectiles aimed toward one of the planet’s
poles.
Axis
Coriolis force is proportional to the angular
velocity.
P2
It will be observed only when the object P1
moves along the axis of rotation. This
effect is used in MEMS based gyroscopes.
R
An inertial mass is made to vibrate along
the axis of rotation.
Coriolis force will try to displace the
inertial mass perpendicular to its motion.
This movement can be measured as was done for an
accelerometer, using force balance technique.
PRECAUTION
The drone contains thin and sharp blades of the propellers rotating at
a very high speed.
These can cause serious harm if they colloid with people or objects.
Always use guards around the propellers and
exercise extreme care when attempting to fly your
drone!
8 Synchronization
Serial Interfaces
The transmitter and the receiver must agree on the order in which the
bits will be sent.
Academic Year: 2024-2025, Semester: I (Au
(IIT B) Let’s Make a Drone 33 / 74
Synchronization
Synchronization
The rate at which the transmitter shifts the data out must be
matched to the rate at which the receiver shifts the data in.
Even if the clock frequencies at the transmitter and receiver are
perfectly matched, the phase of the clock at the receiver should be
carefully adjusted so that we sample the serial line when it is
stable and not when the data on it is changing.
How can this be ensured? This can be done through
1 synchronous communication, or
2 asynchronous communication.
In our project, we shall mostly use synchronous serial communication.
Synchronous communication
Synchronizing data transmission and reception can be easily managed
If the transmitter and receiver use the same clock.
The transmitter can From Transmitter To Receiver
send the data through
Data
one wire and the shift
Shift Register Shift Register
clock through another. Shift Clock
The receiver uses the clock sent by the transmitter for sampling and
shifting the data.
Shift
If the transmitter places data on the positive Clock
edge of the clock, while the receiver samples it Data sampled
by receiver
at the negative edge, the data will be stable at
the sampling instant. Data
Data placed by Transmitter
Synchronous communication
If the clock is sent along with data, the sampling rate as well as
timing for data change and sampling can be easily managed. This
is called synchronous serial communication.
However, this requires that the skew (differences in delay)
between the clock and data must be very small. This will be the
case if the transmitter and the receiver are located close to each
other – as in our project.
The advantage of this method is that it can achieve very high data
rates.
In this project, we shall use two popular protocols for synchronous
serial communication:
I2 C bus
Serial Peripheral Interface or SPI.
All devices drive the bus lines using open drain drivers.
Each line has a pull up resistor.
Since devices provide only the pull down function, individual
devices can use different supply voltages.
The ability to connect devices using different supply voltages and
the use of only 2 wires are the most attractive features of the I2 C
Bus.
Because of its open drain drivers and resistive pull ups, this bus is
used for low and medium speed communication.
In the standard mode, Data is transferred at rates of up to 100
kbit/s on this bus.
The protocol does not restrict one from using much lower clock
frequencies.
Data can be sent at up to 400 kbit/s in the Fast-mode and up to 1
Mbit/s in Fast-mode Plus.
Recent versions of the bus protocol can support a speed of up to
3.4 Mbit/s in the High-speed mode.
To use the 10-bit address scheme, the address frame consists of two
bytes instead of one. A specific combination (‘11110’) of five most
significant bits of the first byte is used to signal the 10-bit address
mode. These 5 bits, the 10 bit address and the read/write bit make up
the 16 bit address frame.
Both lines (SDA and SCL) use open drain drivers. So it is worth
recalling some characteristics of open drain logic.
Vdd
Pull Up Each driver has only a pull
Dev1 Dev2 Dev3
Bus line
SDA or SCL down transistor. Pull up is
provided by the common pull
In1 Out1 In2 Out2 In3 Out3 up resistor on the bus.
The bus can be ’High’ only if all driver transistors are OFF.
Any device can pull down the bus wire unconditionally.
Different devices using different supply voltages can be easily
connected as pull down devices.
The bus driver transistor should be able to withstand the voltage
provided by external VDD – typically 5V.
For normal data transmission, the transmitter places data on the data
line at the falling edge of clock.
SCL
The receiver samples data on the rising edge of the clock so that
the data is stable at the time of sampling.
In this protocol, the most significant bit is sent first.
The master device can be the talker or the listener.
Listener and talker roles are decided during the first message
from the master.
When the master is the talker, it generates the start condition, then
sends the 7 bit address of the slave, followed by a ‘0’ to indicate that
the master is the talker and the slave is the listener.
During the ninth bit time, the driver transistor of the master is
turned off and the receiver should pull down the SDA line if it
received the data successfully.
This is called the ‘Ack’ message.
If the receiver driver transistor is also ‘OFF’ during the ninth bit
period, the SDA line will be seen to be ‘High’ during this time.
This is known as a ’Nack’ message. It is used by the slave to
signal failure to receive when it is a listener (during write operation
by master).
To summarize:
The first transmission from the master establishes it as the talker
and the slave as the listener if the last bit sent from the master is
‘0’.
After the address has been acknowledged by the receiver, the
master, (which is the talker), sends data serially to the slave
receiver, checking for the ‘Ack’ signal at the end of each byte.
After all bytes have been sent, the transmission is terminated by a
‘Stop’ signal on the line.
MOSI
Slave Out Slave In
D7 D6 D5 D4 D3 D2 D1 D0
Output of the master shift register is connected to the input of the slave
shift register, while the output of the slave shift register is connected to
the input of the master shift register, thus forming a ring.
There is simultaneous transfer of data between the two devices with
clock pulses generated by the master device.
Academic Year: 2024-2025, Semester: I (Au
(IIT B) Let’s Make a Drone 50 / 74
Synchronous Serial I-O Serial Peripheral Interface: SPI
Slave Out
D7 D6 D5 D4 D3 D2 D1 D0
Slave In
signals.
Slave Select
Slave Device Serial Clock Only the selected device takes
part in data transfer. Others do
not driveAcademic
their Year:
outputs.
2024-2025, Semester: I (Au
(IIT B) Let’s Make a Drone 51 / 74
Synchronous Serial I-O Serial Peripheral Interface: SPI
Signals in SPI
The SPI interface defines the following signals:
MOSI: Master out, Slave in This is the output from the master and
input to the slave for serial data.
MISO: Master in, Slave out This is the output from the slave and input
to the master for serial data.
Sclk: Serial clock provided by the master. The master outputs a
counted number of clock pulses to interchange the data in
the two shift registers.
SSi : Slave select These are the slave select lines, one per slave.
Typically, the microprocessor is the master device and
multiple peripherals such as serial memory, ADC, DAC,
real time clock chips etc. are the multiple slaves.
The master has to have a separate slave select line for each slave
device. If the number of slaves is large and this many pins cannot be
provided, a decoder can be used.
Academic Year: 2024-2025, Semester: I (Au
(IIT B) Let’s Make a Drone 52 / 74
Synchronous Serial I-O Serial Peripheral Interface: SPI
Clock phase decides the timing of data changes on the MOSI and
MISO lines.
CPHA=0 indicates that the MOSI and MISO lines will change data
on the trailing edge while the inside circuit captures data at (or
shortly after) the leading edge of the clock cycle.
The driver for the data lines should hold the data steady till the
next trailing edge.
For the first cycle of the clock, the first bit must already be on the
MOSI line before the leading edge of the clock arrives.
Thus, for CPHA=0, there is half a cycle with clock at idle, followed
by half a cycle with clock asserted.
CPOL=0 and CPHA=0 are the most commonly used combination for
SPI communication.
Academic Year: 2024-2025, Semester: I (Au
(IIT B) Let’s Make a Drone 55 / 74
Synchronous Serial I-O Serial Peripheral Interface: SPI
CPHA=1 indicates that the “output” side will change data on the
leading edge while the “input” side captures the data on (or shortly
after) the trailing edge of the clock cycle.
The “output” side should hold the data steady till the next leading
edge.
Thus, for CPHA=1, there is half a cycle with clock asserted,
followed by half a cycle with clock idle.
For the last cycle of the clock, drivers should hold the data steady
till slave select is de-asserted.
The four combinations of clock polarity and phase are often
summarised as a mode number, with CPOL as the more significant bit
and CPHA as the less significant bit.
CPOL = 0
SCK
CPOL = 1
Leading
Leading
Leading
Leading
Leading
Leading
Leading
Leading
Trailing
Trailing
Trailing
Trailing
Trailing
Trailing
Trailing
Trailing
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
CPHA = 0
Cycle No. 1 2 3 4 5 6 7 8
MOSI
MISO
As long as the same mode is used by all devices, the exact clock
frequency is immaterial.
CPOL = 0
SCK
CPOL = 1
Leading
Leading
Leading
Leading
Leading
Leading
Leading
Leading
Trailing
Trailing
Trailing
Trailing
Trailing
Trailing
Trailing
Trailing
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
CPHA = 1
Cycle No. 1 2 3 4 5 6 7 8
MOSI
MISO
Notice that 9 clock cycles will be required for transferring 8 bits. This is
because of the extra half clock cycle delay required to be inserted for
ensuring that data change and sampling take place at different clock
edges.
Data Size
Daisy chaining
One problem with SPI is that it needs a separate slave select signal for
each slave. This may be a problem for many processors with a pin
constraint.
Daisy Chained Slaves
An alternative to connecting
MISO
Sclk
MOSI MOSI
Sclk
MISO
slave devices in parallel is to
Master Slave 0 daisy chain these, with a
Slave 2 Slave 1
single slave select used for all.
MISO MOSI MISO MOSI
Sclk Sclk Now we do not need multiple
slave select signals.
The master can control where the data ends up by controlling the
number of clock pulses to be supplied.
Asynchronous communication
If the transmitter and the receiver are physically remote, they must
use independent shift clock generators, set nominally to the same
frequency.
In this case, their clock frequencies will invariably have a small but
non-zero mismatch.
Unfortunately, this means that with time, the sampling instant will
drift further and further away from the ideal sampling time.
When the sampling time has shifted by more than a half period,
the receiver might sample the wrong bit on the serial line, leading
to errors.
Obviously some means of re-synchronization must be provided to
avoid this and to ensure reliable transfer of data.
Asynchronous communication
Asynchronous communication
Asynchronous communication
Write instants
Notice that the first sampling instant is offset from the writing
instant by half a bit time.
This is to ensure that a bit is sampled in the middle of the bit
interval T, where it is stable.
After sampling the start bit, each bit is sampled a time T after the
previous bit.
Asynchronous communication
Frame synchronisation
The receiver knows that a frame will always begin with an edge.
It uses a locally generated clock for synchronization and timing.
The ‘start of frame’ edge on the serial data may not coincide with
an edge on the locally generated clock.
We take the next edge of the local clock as the effective start of
frame.
The error in timing due to this could be a whole cycle of the local
clock in the worst case.
Obviously, the local clock should not operate at the data rate - a
timing error of 1 bit time will then shift the data by 1 bit!
So the local clock is operated at a multiple of the shift clock.
Frame synchronisation
Frame synchronisation
Frame Detect Sampling Instants
T/2 T T T T T T T T T
0
start b0 b1 b2 b3 b4 b5 b6 b7 stop
(LSB) Time (MSB)
Frame synchronisation
Notice that this scheme will work equally well, if additional delay is
inserted between the end of one frame and the beginning of the next.
After the last bit has been sampled, no further timing needs to be
performed.
The serial line idles at the stop bit (normally ‘1’).
The counter is reset to zero whenever the next frame edge is
detected.
Therefore it does not matter how much time elapses between the
end of a frame and the beginning of the next.