5 4 3 2 1

Schematics Only for TB-RK3576D

D
TB-RK3576D0_V10 D

Main Functions Introduction

1) PMIC: 1 x RK806S-5 + DiscretePower
2) RAM: 1 x LPDDR4x 32bit(Option 1 x LPDDR4 32bit)
3) ROM: 1 x eMMC5.1 + 1 x UFS2.1 (Option)
4) Support: 1 x Micro SD Card3.0
5) Support: 2 x USB3.0 TYPEA(OTG)
6) Support: 2 x RGMII 1000M Ethernet RJ45 Connector(one with POE)
C
7) Support: 1 x 4Lanes MIPI DCPHY RX Camera C

8) Support: 1 x 4Lanes MIPI DPHY RX Camera

9) Support: 1 x 4Lanes MIPI DSI with Touch Connector
10) Support: 1 x a/b/g/n/ac 2T2R PCIe WIFI5+ UART/PCM BT
11) Support: 1 x pcie M.2
12) Support: TypeC Power with PD3.0
13) Support: 40pin GPIO Connector
14) Support: PowerOn Key,Rev Key

B B

Note:
The RK806S-5 LDO power distribution of the reference
schematic is only suitable for the interface used in
the reference schematic.
A
If other interface functions need to be added to Rockchip Electronics Co., Ltd
A

the reference schematic, the RK806S-5 LDO distribution

needs to be re evaluated, otherwise the added Project: TB-RK3576D0

functions may exceed the maximum current File:

Date:
00.Cover Page
Monday, May 13, 2024 Rev: V1.0
provided by the LDO Designed by: Jason Deng Reviewed by: Sheet: 1 of 50
5 4 3 2 1
 5 4 3 2 1

Table of Content
Page 1 00.Cover Page
Page 2 01.Index and Notes
Page 3 02.Revision History
Page 4 03.Block Diagram
Page 5 04.Power Diagram
D
Page 6 05.Power Sequence and Map D

Page 7 06.Lower-Speed Bus Map

Page 8 07.USB/DP Configure Map
Page 9 08.PCIe Comb PHY Configure Map
Page 10
Page 11 10.RK3576-Power/GND
Page 12 11.RK3576-OSC/PLL/PMUIO/SARADC
Page 13 12.RK3576-DDR PHY
Page 14 13.RK3576-eMMC/UFS/SD
Page 15 14.RK3576-TypeC/USB
Page 16 15.RK3576-MIPI DSI/CSI
Page 17 16.RK3576-HDMI/eDP
Page 18 17.RK3576-PCIe/SATA/USB3
Page 19 18.RK3576-GPIO VCCIO2/3/6
C Page 20 19.RK3576-GPIO VCCIO4/5 C

Page 21 20.Power-DC IN
Page 22 23.Power-PMIC RK806S-5
Page 23 24.Power-Ext Discrete/RTC IC
Page 24 25.USB/TypeC Port
Page 25 38.DRAM-LPDDR4X_1X32bit_200P
Page 26 40.Flash-eMMC
Page 27 41.Flash-UFS
Page 28 42.Flash-MicroSD Card
Page
Page
29
30 Generate Bill of Materials Description
Page 31 47.VI-Camera_MIPI-CSI
Page 32 50.VO-LCM MIPI DPHY TX Header:
Page 33 Note
Item\tPart\tDescription\tPCB Footprint\tReference\tQuantity\tOption
Page 34 64.WIFI6/BT-PCIe+UART_2T2R
B B
Page 35
Page 36 Combined property string:
Page 37
{Item}\t{Value}\t{Description}\t{PCB Footprint}\t{Reference}\t{Quantity}\t{Option} Option
Page 38 70.Audio-CODEC(ES8388)
Page 39 74.Audio-SPK
Page 40
Page 41
Page
Page
Page
42
43
44
90.Key
91.Sensors
Notes
Page 45 NOTE 1：
Page 46 Component parameter description
1. NC stands for component not mounted temporarily
Page 47 96.HW_ID/BOM_ID 2. If Value or option is NC, which means the area is reserved without
Page 48 being mounted
A
Page 49 A

Page 50 99.Mark/Hole NOTE 2:

Please use our recommended components to avoid too many changes.
Page 51 For more informations about the second source,please refer to our AVL. Rockchip Electronics Co., Ltd
Page 52
Page 53 Project: TB-RK3576D0
File: 01.Index and Notes
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 2 of 50

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Revision History
Version Date By Change Dsecription Approved
D D

V1.0 2024-02-18 Jason.Deng 1: Revision preliminary version;

V1.1 2024-02-19 Jason.Deng 1. page20,R2006改dnp

2. page20,C2003 BST cap place between pin5 and pin6 of u2000（lastest SCH改NB679）
3. page68.R6824 DNP,R6825 install 4K7
4. page18 &85,网络名变更PCIE0_CLKREQn_M0改PCIE0_CLKREQn
5. CON2400 更改为 卧式1.25R封装
6. R2011 change 5.11K(最新版本原理图没有R2011）
7. R2000,R2001 DNP
8. R2517/R2518改20k
9.R2500/R2501改3.6K
10.C2511/C2521 change 4.7u->22uF 0603,add C2520/C2513 22uF 0603
C
11.c2006 22pF-->220nF,add R2020/R2021/C2020/C2010, C
u2000 change NB679,delete R2010/R2011;
L2000 change 2.2uH
12. change VCCIO4 power supply rom VCCIO_1V8_s0 to "VCC_1V8_S3"
13. delete page64 board ant
14. ignore add power switch for vcc_1v8_s0

B B

A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 02.Revision History
Date: Friday, July 12, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 3 of 50

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RK3576 Ref Block Diagram(Typical Application Case) Rockchip Other

IC IC
I2C0

TP INT

RK3576
VBUS_TYPEC(5V-9V-12V) Panel+TP
TP RST

D Reset VOP D
nPOR
DCDC MIPI DCPHY ComboPHY
DPHY DSI TX 4Lane or
MIPI DPHY DSI TX 4Lanes BL_PWM

CPHY DSI TX 3Trio

24MHz OSC

HDMI2.1/eDP TX
VCC_SYSIN
2*16bit
LPDDR4/4x DDR PHY
RGB888/BT1120/BT656

I2C1

EINK TCON

RK806S-5
eMMC 5.1/ 8bit eMMC
PWR_CTRL1/2 INT
/FSPI0
VI CAP
I2C5
MIPI DPHY CSI1/2 RX
PWRON Reset 4Lane or 2x2Lane
FSPI1_M1
MIPI DPHY CSI3/4 RX MIPI DPHY CSI3 RX
2Lanes 4Lane or 2x2Lane
UFS UFS MPHY
Power Reset
Key Key MIPI DCPHY ComboPHY
MIPI DPHY CSI0 RX I2C4
DPHY CSI0 RX 4Lane or
CPHY CSI RX 3Trio
C
26MHz UFS OSC C

CIF 8/12/16bit
Power for RK3576
Micro SDMMC0 4bit SDMMC0
and External device SD Card /FSPI1_M0 Combo PHY0

SATA0

PCIe0
ETH MAC0

Combo PHY1

SATA1
ETH MAC1

PCIe1

SDMMC1
USB3.2 Gen1x1_OTG1
POGO
SPI0~4
USB2.0 HOST1 DP/DM
USB2.0 OTG1
B B
SAI1
SDIO
SAI0~1(8CH) USB2.0 OTG0 DP/DM
WIFI 5 USB2.0 OTG0 Type-C
SAI2(PCM) SAI2, 4
SDIOWIFI SAI2~4(2CH) With ALT Mode
USB3/DP ComboPHY
UART/PCM BT UART4 USB3.2 Gen1x1_OTG0 SS
PDM1 USB3.2 Gen1x1_OTG0
PDM0~1
JTAG I2C2
DP TX
DP TX CC IC
SPDIF TX0~1 INT

SPDIF RX0~1 I3C0~1

I2C2
SAI1
I2C0,1,2,3,4,5,7,8 INT
DSMAUD L/R I2C0~9 RTC IC
Audio Codec 32.768KHz
I2C3
UART0,4
CAN0~1 UART0~11

HPOUT MIC LINEOUT LINEOUT JTAG PWM0CH0~PWM0CH1

_L/R L R 32.768KHz

A FLEXBUS A
/DSMC PWM1CH0~PWM1CH5

SARADC_VIN1 SARADC0~7 PWM2CH0~PWM2CH7

Rockchip Electronics Co., Ltd

SARADC_VIN0
Project: TB-RK3576D0
Headphone MIC Maskrom Key File: 03.Block Diagram
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 4 of 50

5 4 3 2 1
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Note:
Power Tree The RK806 LDO power distribution of
the reference schematics is only suitable
for the interface used in the reference schematics.
If other interface functions are to be added to
VBUS_TYPEC
the reference schematics, the RK806 LDO distribution
needs to be re evaluated, otherwise the added
functions may exceed the maximum current
D
provided by the LDO D
Note: DC
With PCIe, the current is
estimated according to the CHARGER eMMC_3V3 Max:
actual number of PCIe
VCC_UFS_S0 Max:
MIPI CSI RX0/1/2/3/4_CON_3V3 Max:
VCCSYS_IN
Seq:0 Max:
Max:
Max:
Max:

RK806S-5
Max:
Power on VCCIO6_VCC_SOC Max:
LOAD SWITCH
Sequence USB2_OTG_AVDD3V3_SOC Max:
VCC_3V3_S0
BUCK1 Seq:2
VCC1 6.5A max VDD_CPU_BIG_S0
VDD_CPU_BIG_SOC Max: PMOS VCC3V3_LCD_S0 Max:
Max:
BUCK2 Seq:2
VCC2 5.0A max VDD_NPU_S0 LOAD SWITCH VCC3V3_SD_S0 Max:
VDD_NPU_SOC Max:
Max:
BUCK3 Seq:2 HUSB311_CC_3V3 Max:
VCC3 5.0A max VDD_CPU_LIT_S0
VDD_CPU_LIT_SOC Max: Max:
Max: eMMC_1V8 Max:
BUCK4 Seq:5 FT232RL_3V3 Max:
VCC4 5.0A max VCC_3V3_S3 Max:
PCIe WIFI-AP6276P Max:
Max: ES8388_AUDIO_1V8 Max:
BUCK5 Seq:2 Max:
C
VCC5 3A max VDD_GPU_SOC MIPI CSI RX_1V8 Max: C

VDD_GPU_SOC Max: LPDDR4x VDDQ Max: PMUIO1_VCC_SOC Max:

Max: VCCIO0_VCC1V8_SOC Max:
BUCK6 Seq:7 DDRPHY_CK_VDDQ_SOC Max:
VCC6 3A max VDDQ_DDR_S0 VCCIO2_VCC_SOC Max:
DDRPHY_VDDQ_SOC Max: LOAD SWITCH
Max: VCCIO5_VCC_SOC Max:
BUCK7 Seq:2 VCCIO_1V8_S0
VCC7 3A max VDD_LOGIC_S0
VDD_LOGIC_SOC Max:
Max: PMOS UFS_VCCQ2_1V8_S0 Max:
BUCK8 Seq:3 VDD_LOGIC_MEM_SOC Max:
VCC8 3A max VCC_1V8_S3
LPDDR4/4X VDD1 Max:
Max:
BUCK9 Seq:4 WIFI/BT-Ext Board Max:
VCC9 3A max VDD2_DDR_S3
MOS to LPDDR4 VDDQ(Opt) Max: PCIe WIFI-AP6276P Max:
Max:
BUCK10 Seq:2 LPDDR4/4x VDD2 Max: PMUIO0_VCC1V8_SOC Max:
VCC10 3A max VDD_DDR_S0
DDRPHY_DVDD_SOC Max: DDRPHY_CKE_VDDQ_SOC Max: VCCIO3_VCC_SOC Max:
Max:
PLDO1 Seq:3
500mA max VCCA_1V8_S0
OSC_AVDD1V8_SOC Max:
PLDO2 Seq:3 PLL_AVDD1V8_SOC Max:
VCC_2V0_PLDO_S3 VCC11 300mA max VCC_1V8_S0
CAMERA 1V8 SARADC_AVDD1V8_SOC Max:
PLDO3 Seq:4 VCCIO7_VCC_SOC Max: DDRPHY_PLL_AVDD1V8_SOC Max:
300mA max VDDA_1V2_S0
OSC_UFS_AVDD_SOC Max: UFS_AVDD1V8_SOC Max:
PLDO4 Seq:5 MIPI_DCPHY_AVDD1V2_SOC Max: USB3_OTG0/DP_TX_AVDD1V8_SOC Max:
VCC12 500mA max VCCA_3V3_S0
CODEC_VCCA3V3 Max: USB2_OTG_AVDD1V8_SOC Max:
PLDO5 Seq:5 MIPI_D/C_PHY_AVDD1V8_SOC Max:
B 300mA max VCCIO_SD_S0 B
VCCIO1_VCC_SOC Max: MIPI_CSI1/2_AVDD1V8_SOC Max:
PLDO6 Seq:3 Max: MIPI_CSI3/4_AVDD1V8_SOC Max:
VCCA 300mA max VCCA1V8_PLDO6_S3
VCCA1V8_PLDO6_S3 Max: Max:
NLDO1 Seq:2 Max:
300mA max VDD_0V75_S3
PMU_LOGIC_DVDD0V75_SOC Max: PCIE0_SATA0_AVDD1V8_S0C Max:
NLDO2 Seq:2 PCIE1_SATA1_USB3_OTG1_AVDD1V8_S0C Max:
VCC_1V1_NLDO_S3 VCC13 300mA max VDDA_DDR_PLL_S0
DDRPHY_PLL_DVDD_SOC Max: VCCIO7_VCC_SOC(Opt) Max:
NLDO3 Seq:2 Max: OSC_UFS_AVDD_SOC(Opt) Max:
500mA max VDDA0V75_HDMI_S0
Max:
NLDO4 Seq:2
VCC_1V1_NLDO_S3 VCC14 500mA max VDDA_0V85_S0
UFS_AVDD0V85_SOC Max:
NLDO5 Seq:2 USB3_OTG0/DP_TX_AVDD0V85_SOC Max:
300mA max VDDA_0V75_S0
PLL_DVDD0V75_SOC Max: USB3_OTG0/DP_TX_DVDD0V85_SOC Max:
OTP_DVDD0V75_SOC Max: PCIE0_SATA0_AVDD0V85_S0C Max:
USB2_OTG_DVDD0V75_SOC Max: PCIE1_SATA1_USB3_OTG1_AVDD0V85_S0C Max:
Seq:1 VCC_2V0_PLDO_S3
EXT DC/DC ,2A MIPI_DCPHY_AVDD_SOC Max:
Max:
PMIC_EXT_EN_OUT EN MIPI_CSI1/2_RX_AVDD0V75_SOC Max:
MIPI_CSI3/4_RX_AVDD0V75_SOC Max:
Seq:1 VCC_1V1_NLDO_S3
EXT DC/DC ,2A
Max:
PMIC_EXT_EN_OUT EN
A A

Seq:5B VCC_UFS_S0
EXT DC/DC ,2A VCC_UFS_S0(Opt) Max:
Max:
VCC_3V3_S0 EN

Seq:4B VCC1V2_UFS_VCCQ_S0
EXT DC/DC ,2A VCC1V2_UFS_VCCQ_S0(Opt) Max:
Max:
VCC1V8_UFS_VCCQ2_S0 EN
Rockchip Electronics Co., Ltd
Seq:4B VCC_5V
EXT BOOST 5V USB HOST2.0 Max: Project: TB-RK3576D0
Max:
File: 04.Power Diagram
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 5 of 50

5 4 3 2 1
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Power Sequence Power description

Power PMIC Supply Power Time Default Default Work Peak Sleep
Supply Channel Limit Name Slot Voltage ON/OFF Voltage Current Current
0 1 2 3 4 5 7 12 VCC_SYSIN RK806_BUCK1 6.5A VDD_CPU_BIG_S0 Slot:2 0.75V ON DVFS TBD TBD

VCC_SYSIN RK806_BUCK2 5A VDD_NPU_S0 Slot:2 0.75V ON DVFS TBD TBD

D VBUS_TYPEC VCC_SYSIN RK806_BUCK3 5A VDD_CPU_LIT_S0 Slot:2 0.75V ON DVFS TBD TBD D

VCC_SYSIN RK806_BUCK4 5A VCC_3V3_S3 Slot:5 3.3V ON 3.3V TBD TBD

VCC_SYSIN
VCC_SYSIN RK806_BUCK5 3A VDD_GPU_S0 Slot:2 ADJ ON DVFS TBD TBD
FB=0.5V
VCC_1V1_NLDO_S3 VCC_SYSIN RK806_BUCK6 3A VDDQ_DDR_S0 Slot:7 ADJ ON 0.61V-LP4/4x TBD TBD
FB=0.5V 0.51V-LP5
VCC_SYSIN RK806_BUCK7 3A VDD_LOGIC_S0 Slot:2 0.75V ON 0.75V TBD TBD
VCC_2V0_PLDO_S3 VDD_LOGIC_MEM_S0
VCC_SYSIN RK806_BUCK8 3A VCC_1V8_S3 Slot:3 1.8V ON 1.8V TBD TBD

VDD_0V75_S3 VCC_SYSIN RK806_BUCK9 3A VDD2_DDR_S3 Slot:4 ADJ ON 1.1V-LP4/4x TBD TBD

FB=0.5V 1.05V-LP5
VCC_SYSIN RK806_BUCK10 3A VDD_DDR_S0 Slot:2 0.85V ON 0.85V TBD TBD
VDD_LOG_S0 DVFS
RK806_PLDO1 0.5A VCCA_1V8_S0 Slot:3 1.8V ON 1.8V TBD TBD

VDD_LOGIC_MEM_S0 VCC_2V0_PLDO RK806_PLDO2 0.3A VCC_1V8_S0 Slot:3 1.8V ON 1.8V TBD TBD

RK806_PLDO3 0.3A VDDA_1V2_S0 Slot:4 1.2V ON 1.2V TBD TBD

VDD_CPU_LIT_S0
RK806_PLDO4 0.5A VCCA_3V3_S0 Slot:5 3.0V ON 3.3V TBD TBD
VCC_SYSIN
VDD_CPU_BIG_S0 RK806_PLDO5 0.3A VCCIO_SD_S0 Slot:5 3.3V ON 3.3V TBD TBD

VCC_SYSIN RK806_PLDO6 0.3A VCCA1V8_PLDO6_S3 Slot:3 1.8V ON 1.8V TBD TBD

VDD_NPU_S0
RK806_NLDO1 0.3A VDD_0V75_S3 Slot:2 0.75V ON 0.75V TBD TBD
C C
VDD_GPU_S0 VCC_1V1_NLDO RK806_NLDO2 0.3A VDDA_DDR_PLL_S0 Slot:2 0.85V ON 0.85V TBD TBD
DVFS
RK806_NLDO3 0.5A VDDA0V75_HDMI_S0 Slot:2 0.75V ON 0.75V TBD TBD
VDDA_0V75_S0
RK806_NLDO4 0.5A VDDA_0V85_S0 Slot:2 0.85V ON 0.85V TBD TBD
VCC_1V1_NLDO
VDDA_DDR_PLL_S0 RK806_NLDO5 0.3A VDDA_0V75_S0 Slot:2 0.75V ON 0.75V TBD TBD

RK806_RESETn
VDD_DDR_S0
VCC_SYSIN EXT BUCK 2A VCC_2V0_PLDO_S3 Slot:1 2.1V ON 2.0V TBD TBD

VDDA_0V85_S0 VCC_SYSIN EXT BUCK 2A VCC_1V1_NLDO_S3 Slot:1 1.1V ON 1.1V TBD TBD

VDDA0V75_HDMI_S0

VCC_1V8_S3 VCC_3V3_S3 SWITCH 2A VCC_3V3_S0 Slot:5A 3.3V ON 3.3V TBD TBD

VCC_1V8_S3 SWITCH 2A VCCIO_1V8_S0 Slot:3A 1.8V ON 1.8V TBD TBD

VCCA_1V8_S0

VCCA1V8_PLDO6_S3
Note:
B
VCC_1V8_S0 The power suffix S0, S3 or S5 means: B
S5: Keep power on during power down
VCCIO_1V8_S0 S3: Keep power on during sleeping
S0: Power off during sleeping
VDD2_DDR_S3

VDDA_1V2_S0

VCC_3V3_S3 IO Power Domain Map

VCCIO_SD_S0 IO Support Supply Power Power Operating
Domain Pin Num IO Voltage Pin Name Source Voltage IO Type Operating Voltage
VCCA_3V3_S0 PMUIO0 Pin 2K11 1.8V Only PMUIO0_VCC1V8 VCC_1V8 1.8V 1.8V Only VCCIO*_VCC1V8=1.8V

1.8V or 3.3V VCC_1V8 1.8V

PMUIO1 Pin 1U20 PMUIO1_VCC 1.2V or 1.8V VCCIO*_VCC=1.2V or 1.8V
VCC_3V3_S0 VCC_3V3
Related to SW's Ton
VCCIO0 Pin 1J20 1.8V Only VCCIO0_VCC1V8 VCC_1V8 1.8V 1.8V or 3.3V VCCIO*_VCC=1.8V or 3.3V
VCC5V0_DEVICE_S0 VCC_1V8
VCCIO1 Pin 2A8 1.8V or 3.3V VCCIO1_VCC 1.8V/3.3V
VCC_3V3
VCC_1V8
VCCIO2 Pin 2A2 1.8V or 3.3V VCCIO2_VCC 1.8V
VDDQ_DDR_S0 VCC_3V3
VCC_1V8
VCCIO3 Pin 2B10 1.8V or 3.3V VCCIO3_VCC 1.8V
A VCC_3V3 A
RESET_L VCCIO4 Pin 2A7 1.8V or 3.3V VCCIO4_VCC
VCC_1V8
1.8V
VCC_3V3
VCC_1V8
VCCIO5 Pin 2A4/2A5 1.8V or 3.3V VCCIO5_VCC 1.8V
VCC_3V3
VCC_1V8
VCCIO6 Pin 2N3 1.8V or 3.3V VCCIO6_VCC 3.3V
VCC_3V3 Rockchip Electronics Co., Ltd
VCC_1V2
VCCIO7 Pin 2M3 1.2V or 1.8V VCCIO7_VCC 1.2V
VCC_1V8 Project: TB-RK3576D0
File: 05.Power Sequence and Map
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 6 of 50

5 4 3 2 1
 5 4 3 2 1

I2C MAP TP(Touch Panel)

UART MAP Audio MAP
RK3576 Slave Unknown RK3576 RK3576
M0 Debug Port
I2C0 Pull UP rail: PMUIO1, VCC_3V3_S3 M0 40PIN Interface M0
M1 UART0 PMUIO1
Rate: TBD M1 SAI0_8CH M1
PMIC RK806S-5 M2
M0
Slave 7bit: 0x23
UART1 M1 M0
SAI1_8CH
Pull UP rail: PMUIO0_VCC1V8 M2 M1
D
M0 D
I2C1 Rate: TBD
M1
M0 M0
UART2 M1 SAI2_2CH M1 WIFI/BT
VCCIO4, 1.8V Module
M2 M2
40PIN Interface
M0 M0
M0 Slave Unknown
UART3 M1 M1
M1 SAI3_2CH
I2C2 Pull UP rail: VCCIO2, VCC_3V3_S0 M2 M2 CODEC
M2 VCCIO4, 1.8V ES8388
Rate: TBD M3
M3
M0
40PIN Interface UART4 M1 M0
M2 M1
Slave Unknown
SAI4_2CH M2
Pull UP rail: VCCIO2, VCC_3V3_S0 M0 M3
M0
Rate: TBD UART5 M1 (inner path)
M1
I2C3 M2
M2
M3
M0
DSM_AUD
M1
UART6
M2
C C
M3 M0
M1
M0 BT UART PDM0
M0 WIFI/BT Module M2
M1 VCCIO4, VCC_1V8_S0
I2C4 UART7 M1 M3
M2
Pull UP rail: VCCIO5, VCCIO_1V8_S0 M2
M3
Rate: TBD M0
M0 40PIN Interface PDM1 M1
VCCIO5, VCC_3V3_S0
UART8 M1 M2
M2
M0
M0
M0 SPDIF_TX0 M1
M1
I2C5 UART9 M1 M2
M2
M2
M3
M0
M0 SPDIF_TX1 M1
UART10 M1 M2
M2
ES8388
M0 M0
M0
M1 Slave 7bit: 0x11 SPDIF_RX0 M1
I2C6 UART11 M1
M2 M2
B
Pull UP rail: VCCIO3, VCC_1V8_S0 M2 B
M3
Rate: TBD
M0
SPDIF_RX1 M1
M2
HYM8563TS

M0 Slave 7bit: 0x51

M1
I2C7 Pull UP rail: VCCIO5, VCCIO_3V3_S0
M2
Rate: TBD
M3

M0
M1
I2C8
M2

Note:
M3

M0 Unselected IOmux path

CAM_Connector
A A
M1 IOmux path in use
M0 Slave Unknown
M1
I2C9 Pull UP rail: VCCIO4, VCCIO_1V8_S0 At the same time, only one path can be selected.
M2
Rate: TBD
M3

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 06.Lower-Speed Bus Map
HDMI_TX_I2C
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 7 of 50

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 5 4 3 2 1

MULTI_PHY Path Map PCIe Combo PHY1--

USBDP PHY--USB3.2 GEN1X1 OTG0/DP1.4 PCIe1/SATA1/USB3.2 GEN1X1 OTG1
PCIe1
DP Controller Controller
USBDP PHY
MUX USB3.2 GEN1X1 OTG0/DP1.4 MULTI_PHY1
SATA1 MUX PCIe1/SATA1
D Controller /USB3.2 GEN1X1 OTG1 D

USB3 OTG0 Controller

USB3 OTG1 Controller
USB3.2 GEN1X1 OTG0
SS USB3.2 GEN1X1 OTG1
SS
USB2 OTG0 USB2 PHY0
HS/FS/LS OTG0_HS/FS/LS USB2 OTG1 USB2 PHY1
HS/FS/LS OTG1_HS/FS/LS

USB OTG0/DP Application

CASE0: TYPEC with DP CASE1: USB2 OTG0 + DP 4Lane(Swap OFF) CASE2: USB2 OTG0 + DP 4Lane(Swap ON)
USBDP PHY
USB3.2 GEN1X1 OTG0
USB3.2 GEN1X1 OTG0/DP1.4 USBDP PHY
USBDP PHY /DP1.4 USB3.2 GEN1X1 OTG0/DP1.4
USB3.2 GEN1X1 OTG0/DP1.4 Lane0
USB3_OTG0_SSRX1/DP_TX_D0 Lane0
Lane1 USB3_OTG0_SSRX1/DP_TX_D0
USB3_OTG0_SSRX1/DP_TX_D0 USB3_OTG0_SSTX1/DP_TX_D1 Lane1
Lane2 USB3_OTG0_SSTX1/DP_TX_D1
C USB3_OTG0_SSTX1/DP_TX_D1 USB3_OTG0_SSRX2/DP_TX_D2 Lane2 C

USB3_OTG0_SSRX2/DP_TX_D2 TYPEC USB3_OTG0_SSTX2/DP_TX_D3

Lane3 USB3_OTG0_SSRX2/DP_TX_D2
USB3_OTG0_SSTX2/DP_TX_D3
Lane3
USB3_OTG0_SSTX2/DP_TX_D3 with DP USB3_OTG0_SBU/DP_TX_AUX
USB3_OTG0_SBU/DP_TX_AUX
USB3_OTG0_SBU/DP_TX_AUX

USB2 PHY0
USB2 PHY0 OTG0_HS/FS/LS USB2
USB2 PHY0
OTG0_HS/FS/LS USB2 OTG0_HS/FS/LS USB2
USB2 OTG0 USB2 OTG0

CASE3: USB3.2 GEN1X1 OTG0 + DP 2Lane(Swap OFF) CASE4: USB3.2 GEN1X1 OTG0 + DP 2Lane(Swap ON)
Lane0 Lane0
USBDP PHY Lane1 2Lanes USBDP PHY Lane1 2Lanes
USB3.2 GEN1X1 OTG0/DP1.4 Device USB3 OTG0/DP1.4 Device
Note:
USB3_OTG0_SSRX1/DP_TX_D0 USB3_OTG0_SSRX1/DP_TX_D0
DP Lane swap enable
USB3_OTG0_SSTX1/DP_TX_D1 USB3_OTG0_SSTX1/DP_TX_D1 0:Lane0/1/2/3 TxData mapping to Lane0/1/2/3_TXDP/N
USB3_OTG0_SSRX2/DP_TX_D2 USB3_OTG0_SSRX2/DP_TX_D2 1:Lane0/1/2/3 TxData mapping to Lane2/3/0/1_TXDP/N

B
USB3_OTG0_SSTX2/DP_TX_D3 USB3_OTG0_SSTX2/DP_TX_D3 B

USB3_OTG0_SBU/DP_TX_AUX USB3_OTG0_SBU/DP_TX_AUX

USB2 PHY0 SS USB2 PHY0 SS

OTG0_HS/FS/LS USB2 OTG0_HS/FS/LS USB2
USB3.2 GEN1X1 OTG0 USB3.2 GEN1X1 OTG0

USB OTG1 Application

CASE0: USB2 OTG1 CASE1: USB3.2 GEN1X1 OTG1
MULTI_PHY1 USB3.2 Gen1x1
PCIe1/SATA1
USB2 PHY1 /USB3.2 GEN1X1 OTG1
OTG1_HS/FS/LS SS
USB2 OTG1 USB2 PHY1
OTG1_HS/FS/LS USB2 USB3.2 GEN1X1 OTG1
A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 07.USB/DP Configure Map
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 8 of 49

5 4 3 2 1
 5 4 3 2 1

CASE0: PCIe x 1Lane

PCIe Combo PHY0--PCIe0/SATA0
MULTI_PHY0 PCIe0
PCIe0/SATA0
PCIe0
Controller
D D

MULTI_PHY0 PCIe0 REFCLK

MUX PCIe0/SATA0
100MHz
RC Mode PCIe Slot
SATA0
Controller CASE1: SATA
MULTI_PHY0 SATA0
PCIe0/SATA0 SATA

CASE0: PCIe x 1Lane + USB2 OTG1

MULTI_PHY1 PCIe1
PCIe1/SATA1
/USB3.2 GEN1X1 OTG1
C C

PCIe1 REFCLK
PCIe Combo PHY1-- 100MHz
RC Mode PCIe Slot
PCIe1/SATA1/USB3.2 GEN1X1 OTG1
USB2 PHY1
OTG1_HS/FS/LS
PCIe1
Controller USB2 OTG1

SATA1
MULTI_PHY1 CASE1: SATA + USB2 OTG1
MUX PCIe1/SATA1
Controller /USB3.2 GEN1X1 OTG1 MULTI_PHY1 SATA1
PCIe1/SATA1
/USB3.2 GEN1X1 OTG1
USB3 OTG1 Controller
B
SATA B

USB3.2 GEN1X1 OTG1

SS USB2 PHY1
OTG1_HS/FS/LS

USB2 OTG1 USB2 PHY1 USB2 OTG1

HS/FS/LS OTG1_HS/FS/LS
CASE2: USB3.2 GEN1X1 OTG1
MULTI_PHY1 USB3.2 Gen1x1
PCIe1/SATA1
/USB3.2 GEN1X1 OTG1
SS
USB2 PHY1
OTG1_HS/FS/LS USB2 USB3.2 GEN1X1 OTG1
A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 08.PCIe Combo PHY Configure Map
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 9 of 49

5 4 3 2 1
 5 4 3 2 1

RK3576_S (Power) RK3576_T/U/V (GND)

D D

U1000S
VDD_CPU_BIG_S0

2G5
CPU_BIG_DVDD_0 2G6 C1000 C1001 C1002 C1003 C1004 C1005 C1038 C1006 C1007 U1000V
CPU_BIG_DVDD_1

1
2H6 100nF 100nF 1uF 1uF 1uF 1uF 4.7uF 10uF 22uF
CPU_BIG_DVDD_2
2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1
2H7 X5R X5R X5R X5R X5R X5R X5R X5R X5R AJ29 2T6
CPU_BIG_DVDD_3 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 4V 6.3V AVSS_0 AVSS_52
CPU_BIG CPU_BIG_DVDD_4
2J6 AK6
AVSS_1 AVSS_53
2T8

2
2J7 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0402 C0603 AK14 2T11
CPU_BIG_DVDD_5 2K6 AK25 AVSS_2 AVSS_54 2U1
CPU_BIG_DVDD_6 2K7 AL4 AVSS_3 AVSS_55 2U2
CPU_BIG_DVDD_7 AL8 AVSS_4 AVSS_56 2U3
VDD_CPU_LIT_S0 AL14 AVSS_5 AVSS_57 2U4
AL25 AVSS_6 AVSS_58 2U5
2H4 AL29 AVSS_7 AVSS_59 2U6
CPU_LIT_DVDD_0 2J3 C1009 C1010 C1011 C1039 C1012 C1013 U1000T U1000U 1Y20 AVSS_8 AVSS_60 2U7
CPU_LIT_DVDD_1 AVSS_9 AVSS_61
1
2J4 100nF 1uF 1uF 4.7uF 10uF 22uF 1AB20 2U9
CPU_LIT CPU_LIT_DVDD_2 AVSS_10 AVSS_62
2 1

2 1

2 1

2 1

2 1
2K3 X5R X5R X5R X5R X5R X5R A1 1H2 1W1 2C10 1AB21 2U10
CPU_LIT_DVDD_3 2K4 6.3V 6.3V 6.3V 4V 4V 6.3V A4 VSS_0 VSS_41 1H3 1W3 VSS_82 VSS_123 2C11 1AB22 AVSS_11 AVSS_63 2U11
CPU_LIT_DVDD_4 VSS_1 VSS_42 VSS_83 VSS_124 AVSS_12 AVSS_64
2

C C0201 C0201 C0201 C0201 C0402 C0603 A29 1H4 1W5 2C12 1AB23 2V1 C
B5 VSS_2 VSS_43 1H6 1W6 VSS_84 VSS_125 2D3 1AB24 AVSS_13 AVSS_65 2V2
C1 VSS_3 VSS_44 1H20 1Y2 VSS_85 VSS_126 2D6 1AC20 AVSS_14 AVSS_66 2V3
VDD_LOGIC_S0 V28 VSS_4 VSS_45 1J2 1Y3 VSS_86 VSS_127 2D9 1AC21 AVSS_15 AVSS_67 2V4
AL1 VSS_5 VSS_46 1J4 1Y4 VSS_87 VSS_128 2E3 1AC24 AVSS_16 AVSS_68 2V5
2E7 1A2 VSS_6 VSS_47 1K3 1Y5 VSS_88 VSS_129 2E5 1AD20 AVSS_17 AVSS_69 2V6
LOGIC_DVDD_0 2F8 C1015 C1016 C1017 C1018 C1040 C1020 C1021 C1022 1A3 VSS_7 VSS_48 1K6 1Y6 VSS_89 VSS_130 2E6 1AD23 AVSS_18 AVSS_70 2V7
LOGIC_DVDD_1 VSS_8 VSS_49 VSS_90 VSS_131 AVSS_19 AVSS_71
1

2F9 100nF 100nF 1uF 1uF 4.7uF 10uF 22uF 22uF 1B2 1L2 1AA2 2E8 1AD24 2V8
LOGIC_DVDD_2 VSS_9 VSS_50 VSS_91 VSS_132 AVSS_20 AVSS_72
2 1

2 1

2 1

2 1

2 1

2 1

2 1
2G8 X5R X5R X5R X5R X5R X5R X5R X5R 1C2 1L3 1AA4 2E9 1AE4 2V9
LOGIC LOGIC_DVDD_3 2G9 6.3V 6.3V 6.3V 6.3V 4V 4V 6.3V 6.3V 1C4 VSS_10 VSS_51 1L4 1AA21 VSS_92 VSS_133 2F4 1AE6 AVSS_21 AVSS_73 2V10
LOGIC_DVDD_4 VSS_11 VSS_52 VSS_93 VSS_134 AVSS_22 AVSS_74
2

2H8 C0201 C0201 C0201 C0201 C0201 C0402 C0603 C0603 1C9 1L5 1AA24 2F5 1AE20 2V11
LOGIC_DVDD_5 2H9 1C13 VSS_12 VSS_53 1L6 1AB2 VSS_94 VSS_135 2F6 1AE21 AVSS_23 AVSS_75 2V12
LOGIC_DVDD_6 1C16 VSS_13 VSS_54 1M1 1AB5 VSS_95 VSS_136 2G4 1AE23 AVSS_24 AVSS_76
1C21 VSS_14 VSS_55 1M2 1AB6 VSS_96 VSS_137 2G7 2M1 AVSS_25
2F7 1D1 VSS_15 VSS_56 1M4 1AC1 VSS_97 VSS_138 2G10 2M4 AVSS_26 G29
LOGIC_MEM_DVDD_0 2J9 1D3 VSS_16 VSS_57 1M6 1AC2 VSS_98 VSS_139 2H3 2M6 AVSS_27 AVSS1_0 T28
LOGIC_MEM_DVDD_1 C1024 C1023 1D5 VSS_17 VSS_58 1N2 1AC3 VSS_99 VSS_140 2H5 2M9 AVSS_28 AVSS1_1 T29
100nF 1uF 1E2 VSS_18 VSS_59 1N4 1AC4 VSS_100 VSS_141 2J1 2M10 AVSS_29 AVSS1_2 1H21
VSS_19 VSS_60 VSS_101 VSS_142 AVSS_30 AVSS1_3
2 1

2 1

X5R X5R 1E3 1N6 1AC5 2J5 2M11 1H24

6.3V 6.3V 1E5 VSS_20 VSS_61 1P2 1AD3 VSS_102 VSS_143 2J8 2M12 AVSS_31 AVSS1_4 1J21
C0201 C0201 1E6 VSS_21 VSS_62 1P3 1AE3 VSS_103 VSS_144 2J11 2N1 AVSS_32 AVSS1_5 1J22
1E10 VSS_22 VSS_63 1P4 2A1 VSS_104 VSS_145 2J12 2N6 AVSS_33 AVSS1_6 1J23
1E13 VSS_23 VSS_64 1P6 2A3 VSS_105 VSS_146 2K1 2N8 AVSS_34 AVSS1_7 1J24
VDD_GPU_S0 1E16 VSS_24 VSS_65 1P20 2A6 VSS_106 VSS_147 2K2 2N9 AVSS_35 AVSS1_8 1K20
2C4 1E23 VSS_25 VSS_66 1P21 2A9 VSS_107 VSS_148 2K5 2N12 AVSS_36 AVSS1_9 1K21
GPU_DVDD_0 2C5 1E24 VSS_26 VSS_67 1P22 2A11 VSS_108 VSS_149 2K8 2P1 AVSS_37 AVSS1_10 1K24
GPU_DVDD_1 2D4 C1026 C1027 C1028 C1041 C1029 C1030 1F3 VSS_27 VSS_68 1P24 2A12 VSS_109 VSS_150 2K9 2P6 AVSS_38 AVSS1_11 1L20
GPU GPU_DVDD_2 VSS_28 VSS_69 VSS_110 VSS_151 AVSS_39 AVSS1_12
1

2D5 100nF 1uF 1uF 4.7uF 10uF 22uF 1F5 1R1 2B1 2K10 2P9 1L21
GPU_DVDD_3 VSS_29 VSS_70 VSS_111 VSS_152 AVSS_40 AVSS1_13
2 1

2 1

2 1

2 1

2 1

2E4 X5R X5R X5R X5R X5R X5R 1F6 1R2 2B3 2K12 2P12 1L22
B GPU_DVDD_4 6.3V 6.3V 6.3V 4V 4V 6.3V 1F20 VSS_30 VSS_71 1T3 2B4 VSS_112 VSS_153 2L1 2R1 AVSS_41 AVSS1_14 1L24 B
VSS_31 VSS_72 VSS_113 VSS_154 AVSS_42 AVSS1_15
2

C0201 C0201 C0201 C0201 C0402 C0603 1F21 1T5 2B5 2L3 2R4 1M20
1F24 VSS_32 VSS_73 1T6 2B6 VSS_114 VSS_155 2L4 2R5 AVSS_43 AVSS1_16 1M21
1G3 VSS_33 VSS_74 1T20 2B7 VSS_115 VSS_156 2L5 2R7 AVSS_44 AVSS1_17 1M22
VDD_NPU_S0 1G6 VSS_34 VSS_75 1U2 2B8 VSS_116 VSS_157 2L6 2R8 AVSS_45 AVSS1_18 1M24
2C7 1G20 VSS_35 VSS_76 1U3 2B9 VSS_117 VSS_158 2L7 2R9 AVSS_46 AVSS1_19 1N20
NPU_DVDD_0 2C8 1G21 VSS_36 VSS_77 1U4 2B11 VSS_118 VSS_159 2L8 2R10 AVSS_47 AVSS1_20 1N21
NPU_DVDD_1 2C9 C1032 C1033 C1034 C1035 C1042 C1036 C1037 1G22 VSS_37 VSS_78 1U6 2B12 VSS_119 VSS_160 2L9 2R11 AVSS_48 AVSS1_21 1N24
NPU NPU_DVDD_2 VSS_38 VSS_79 VSS_120 VSS_161 AVSS_49 AVSS1_22
1

2D7 100nF 100nF 1uF 1uF 4.7uF 10uF 22uF 1G24 1V2 2C1 2L12 2R12 2D10
NPU_DVDD_3 VSS_39 VSS_80 VSS_121 VSS_162 AVSS_50 AVSS1_23
2 1

2 1

2 1

2 1

2 1

2 1

2D8 X5R X5R X5R X5R X5R X5R X5R 1H1 1V6 2C6 2T1 2E10
NPU_DVDD_4 6.3V 6.3V 6.3V 6.3V 4V 4V 6.3V VSS_40 VSS_81 VSS_122 AVSS_51 AVSS1_24
2

C0201 C0201 C0201 C0201 C0201 C0402 C0603

RK3576 RK3576 RK3576 RK3576

BGA698_16R1x17R2x1R18 BGA698_16R1x17R2x1R18 BGA698_16R1x17R2x1R18 BGA698_16R1x17R2x1R18

Note:
Caps of between dashed red lines and U1000
should be placed under the U1000 package.
Other caps should be placed close to the U1000 package
A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 10.RK3576-Power/GND
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Wesley Huang Reviewed by: Sheet: 11 of 50

5 4 3 2 1
 5 4 3 2 1

RK3576_E U1000E

(PMUIO0/1) OSC
PMUIO0 Domain
Operating Voltage=1.8V NPOR
W28
C1119
100nF
R1107 0R R0201
RESET_L
PMUIO0_VCC1V8

2 1
X5R Note: Closed to Pin W28 R1105
R1100 22R R0201 XOUT_24M U29 6.3V 10K
OSC_XOUT C0201 R0201
RESET_L
Y1100 R1101 2H10
24MHz TVSS
510K
D 1 4 V29 RTC_INT_L D
X1 GND -- | -- | -- | AUPLL_CLK_IN_M0 | REF_CLK0_OUT | GPIO0_A0_d 1R24 TSADC_CTRL_M0
R0201 -- | TSADC_CTRL_ORG | TSADC_CTRL_M0 | -- | -- | GPIO0_A1_z
2 3 XIN_24M U28 1U23 32KOUT_RTC
GND X2 1% OSC_XIN I2C6_SCL_M0 | CLK0_32K_OUT | CLK_32K_IN | -- | -- | GPIO0_A2_d Y28 PMUIO0_VCC1V8
-- | TSADC_CTRL_M1 | PWR_CTRL1 | -- | -- | GPIO0_A3_d PMIC_PWR_CTRL1
C1100 CRY4_2R00X1R60X0R55 C1101 1T24 PMIC_PWR_CTRL2
18pF 18pF -- | -- | PWR_CTRL2 | -- | -- | GPIO0_A4_d Y29
I2C6_SDA_M0 | -- | PWR_CTRL3 | -- | -- | GPIO0_A5_d USB2_OTG0_PWREN_H
2 1

2 1

C0201 C0201 1T21 PMIC_INT_L R1121

C0G C0G -- | -- | PMIC_INT | -- | -- | GPIO0_A6_u 1U21 100K
-- | -- | SPI2_CSN1_M0 | -- | SDMMC0_DETN | GPIO0_A7_u SDMMC0_DET_L
25V 25V C1120 1 2 1nF R0201
1U22 C0201 X5R 25V WIFI_WAKE_HOST_H SDMMC0_DET_L
OSC_1V8 2J10 I2C0_SCL_M0 | -- | SPI2_CSN0_M0 | AUPLL_CLK_IN_M1 | -- | GPIO0_B0_z 1P23
VCCA_1V8_S0 OSC_AVDD1V8 I2C0_SDA_M0 | -- | SPI2_MISO_M0 | -- | -- | GPIO0_B1_z BT_WAKE_HOST_H PMUIO0_VCC1V8
R1119 C1102 1T22 I2C1_SCL_M0_RK806
0R 100nF I2C1_SCL_M0 | -- | SPI2_CLK_M0 | -- | -- | GPIO0_B2_z 1T23
I2C1_SDA_M0 | -- | SPI2_MOSI_M0 | -- | -- | GPIO0_B3_z I2C1_SDA_M0_RK806
2 1

R0402 X5R
6.3V PMUIO0_VCC1V8
C0201 R1127 R1128
VCCA1V8_PLDO6_S3 2K11 PMUIO0_VCC1V8 R1125 0R R0402 VCC_1V8_S3 2.2K 2.2K
PMUIO0_VCC1V8 C1103 R0201 R0201
R1124 100nF R1126 NC/0R R0402 VCCA1V8_PLDO6_S3 I2C1_SDA_M0_RK806

2 1
NC/0R X5R I2C1_SCL_M0_RK806
R0402 6.3V
PMUIO1 Domain C0201
PLL
Operating Voltage=1.8V/3.3V VCC_3V3_S3
AD28 GMAC1_INT/PMEB_3V3
-- | PWM1_CH0_M0 | -- | UART4_TX_M2 | I2C1_SCL_M1 | -- | -- | REF_CLK1_OUT | GPIO0_B4_d AD29
-- | PWM1_CH1_M0 | -- | UART4_RX_M2 | I2C1_SDA_M1 | -- | -- | REF_CLK2_OUT | GPIO0_B5_d LCD_BL_PWM1_CH1_M0
1Y24 SDMMC0_PWREN_H
-- | PWM1_CH2_M0 | -- | EDP_TX_HPDIN_M1 | HDMI_TX_HPDIN_M1 | -- | SDMMC1_DETN_M2 | SDMMC0_PWREN | GPIO0_B6_d 1W24 R1138 R1139
-- | PWM1_CH4_M0 | NPU_AVS | UART1_TX_M0 | I2C2_SCL_M0 | -- | -- | -- | GPIO0_B7_d PWM1_CH4_M0/GPIO0_B7
2.2K 2.2K
VDDA_0V75_S0 2G11 AB29 TP_RST_L R0201 R0201
C C1104 PLL_DVDD0V75 -- | PWM1_CH3_M0 | CPULIT_AVS | UART1_RX_M0 | I2C2_SDA_M0 | -- | -- | -- | GPIO0_C0_d AB28 I2C0_SCL_M1_TP C
-- | -- | I3C0_SCL_M0 | UART8_TX_M2 | I2C0_SCL_M1 | -- | -- | -- | GPIO0_C1_d I2C0_SCL_M1_TP
100nF 1V24 I2C0_SDA_M1_TP I2C0_SDA_M1_TP
-- | -- | I3C0_SDA_M0 | UART8_RX_M2 | I2C0_SDA_M1 | -- | -- | -- | GPIO0_C2_d
2 1

X5R 1W21 SPI0_CS1_M0/GPIO0_C3

6.3V -- | PWM0_CH1_M0 | SPI0_CSN1_M0 | -- | HDMI_TX_CEC_M1 | PDM0_CLK1_M0 | -- | -- | GPIO0_C3_d 1W22
-- | PWM0_CH0_M0 | -- | UART10_TX_M2 | -- | PDM0_CLK0_M0 | -- | SAI0_MCLK_M1 | GPIO0_C4_d LCD_PWREN_H
C0201 1AA22 TP_INT_L
-- | -- | I3C0_SDA_PU_M0 | UART10_RX_M2 | DP_HPDIN_M1 | -- | -- | SAI0_SDO0_M1 | GPIO0_C5_d 1Y21
-- | -- | SPI0_CSN0_M0 | -- | I2C3_SCL_M1 | -- | -- | SAI0_SCLK_M1 | GPIO0_C6_d SPI0_CS0_M0/GPIO0_C6
1Y23 SPI0_CLK_M0/GPIO0_C7
-- | -- | SPI0_CLK_M0 | -- | I2C3_SDA_M1 | -- | -- | SAI0_LRCK_M1 | GPIO0_C7_d
VCCA_1V8_S0 2H12 1W23 SPI0_MOSI_M0/GPIO0_D0
C1105 PLL_AVDD1V8 -- | -- | SPI0_MOSI_M0 | -- | -- | PDM0_SDI0_M0 | -- | SAI0_SDI0_M1 | GPIO0_D0_d AC28
-- | -- | SPI0_MISO_M0 | -- | -- | PDM0_SDI1_M0 | SAI0_SDO3_M1 | SAI0_SDI1_M1 | GPIO0_D1_d SPI0_MISO_M0/GPIO0_D1
100nF 1Y22 PCIE0_WAKEn
UART1_CTSN_M0 | PWM1_CH5_M0 | CPUBIG_AVS | PCIE0_WAKEN_M0 | I2C4_SCL_M0 | PDM0_SDI2_M0 | SAI0_SDO2_M1 | SAI0_SDI2_M1 | GPIO0_D2_d
2 1

X5R 1AA23 USB2_HOST_PWREN_H 注意PCIE wake要配成普通GPIO

6.3V UART1_RTSN_M0 | PWM2_CH0_M0 | GPU_AVS | PCIE1_WAKEN_M0 | I2C4_SDA_M0 | PDM0_SDI3_M0 | SAI0_SDO1_M1 | SAI0_SDI3_M1 | GPIO0_D3_d 1U24
-- | -- | -- | JTAG_TCK_M1 | UART0_TX_M0 | -- | -- | -- | GPIO0_D4_u UART0_TX_M0_DEBUG
C0201 AA28 UART0_RX_M0_DEBUG
-- | -- | -- | JTAG_TMS_M1 | UART0_RX_M0 | -- | -- | -- | GPIO0_D5_u
PMUIO1_VCC
待删除
2G12 1U20 PMUIO1_VCC R1141 0R VCC_3V3_S3
PLL_AVSS PMUIO1_VCC C1106 R0402
100nF

2 1
X5R
6.3V
PMUIO0/PMUIO1/VCCIO7 Domain Logic Power C0201
Operating Voltage=0.75V
2L2 VDD_0V75_S3
PMU_LOGIC_DVDD0V75_0 2L10
PMU_LOGIC_DVDD0V75_1 C1107 C1118
100nF 100nF

2 1

2 1
X5R X5R
B RK3576 6.3V 6.3V B
BGA698_16R1x17R2x1R18 C0201 C0201

U1000R
Note:
RK3576_R SARADC
12-bit 1MS/s
A25 SARADC_VIN0_BOOT
Note:This cap should be placed
close to RK3576
C1108 1nF 1 2 X5R 25V C0201
默认emmc配置，通过adc配置ufs Caps of between dashed red lines and U1000
should be placed under the U1000 package.
(SARADC)
SARADC_IN0_BOOT
Recovery/ 1A22 SARADC_VIN1_KEY/RECOVERY C1109 1nF 1 2 X5R 25V C0201 Other caps should be placed close to the U1000 package
SARADC_IN1

SARADC_IN2
1B19 SARADC_VIN2_HW_ID C1110 1nF 1 2 X5R 25V C0201 BOOT MODE CONFIG SARADC_VIN0_BOOT
1C19 SARADC_VIN3_HP_HOOK C1111 1nF 1 2 X5R 25V C0201 VCCA_1V8_S0
SARADC_IN3 SARADC_VIN1_KEY/RECOVERY
Config Table for SARADC_VIN0_BOOT SARADC_VIN2_HW_ID
1E18 SARADC_IN4_VOLDet C1112 1nF 1 2 X5R 25V C0201
SARADC_IN4
Item Rup Rdown ADC Value Boot Mode SARADC_IN4_VOLDet
1D19 R1102
SARADC_IN5 11.3K
R0201 Config1 DNP 10K 0 USB (Maskrom mode)
1D21
SARADC_IN6 1%
Config2 100K 11.3K 416 FSPI0->USB
1E19
SARADC_IN7 SARADC_VIN0_BOOT
Config3 100K 24.9K 816 FSPI1_M0->EMMC->USB
2A10 VCCA_1V8_S0 R1103
SARADC_AVDD1V8 C1116 100K Config4 100K 43K 1231 FSPI1_M1->EMMC->USB
100nF R0201
Config5 100K 68K 1658 FSPI0->UFS->USB
2 1

X5R 1%
A A
6.3V
C0201 Config6 100K 100K 2048 FSPI1_M0->UFS->USB
TSADC Config7 68K 100K 2438 UFS->USB
2F10
TSADC_TEST_OUT_TS
VCCA_1V8_S0 Config8 43K 100K 2864 UFS->SDMMC0->USB
OTP Rockchip Electronics Co., Ltd
2H11 VDDA_0V75_S0
OTP_DVDD0V75 C1117 Config9 24.9K 100K 3279 RFU
Project: TB-RK3576D0
100nF R1104
Config10 11.3K 100K 3679 EMMC->SDMMC0->USB
2 1

X5R 10K
6.3V R0201
File: 11.RK3576-OSC/PLL/PMUIO/SARADC
RK3576
BGA698_16R1x17R2x1R18 C0201 1% Config11 10K DNP 4095 EMMC->USB
Date: Monday, May 13, 2024 Rev: V1.0
SARADC_VIN1_KEY/RECOVERY
Designed by: Jason.Deng Reviewed by: Sheet: 12 of 50
5 4 3 2 1
 5 4 3 2 1

RK3576_A(DDRPHY) LPDDR4 Signal

DDR_DQ0_A LPDDR4_DQ0_A
U1000A DDR_DQ1_A LPDDR4_DQ1_A
DDR_DQ2_A LPDDR4_DQ2_A
LPDDR4 LPDDR4X LPDDR5 LPDDR4 LPDDR4X LPDDR5 DDR_DQ3_A LPDDR4_DQ3_A
DDR_DQ0_A W1 1D2 DDR_DQ0_B DDR_DQ4_A LPDDR4_DQ4_A
DDR_DQ1_A 1T1 LP4_DQ0_A | LP4X_DQ0_A | LP5_DQ0_A LP4_DQ0_B | LP4X_DQ0_B | LP5_DQ0_B 1F2 DDR_DQ1_B DDR_DQ5_A
LP4_DQ1_A | LP4X_DQ1_A | LP5_DQ1_A LP4_DQ1_B | LP4X_DQ1_B | LP5_DQ1_B LPDDR4_DQ5_A
DDR_DQ2_A 1P1 1G1 DDR_DQ2_B DDR_DQ6_A LPDDR4_DQ6_A
DDR_DQ3_A U1 LP4_DQ2_A | LP4X_DQ2_A | LP5_DQ2_A LP4_DQ2_B | LP4X_DQ2_B | LP5_DQ2_B K1 DDR_DQ3_B DDR_DQ7_A
LP4_DQ3_A | LP4X_DQ3_A | LP5_DQ3_A LP4_DQ3_B | LP4X_DQ3_B | LP5_DQ3_B LPDDR4_DQ7_A
DDR_DQ4_A 1V3 1C3 DDR_DQ4_B
DDR_DQ5_A 1W4 LP4_DQ4_A | LP4X_DQ4_A | LP5_DQ4_A LP4_DQ4_B | LP4X_DQ4_B | LP5_DQ4_B 1B3 DDR_DQ5_B DDR_DQS0P_A
LP4_DQ5_A | LP4X_DQ5_A | LP5_DQ5_A LP4_DQ5_B | LP4X_DQ5_B | LP5_DQ5_B LPDDR4_DQS0P_A
D DDR_DQ6_A AC1 A5 DDR_DQ6_B DDR_DQS0N_A LPDDR4_DQS0N_A D
DDR_DQ7_A AB1 LP4_DQ6_A | LP4X_DQ6_A | LP5_DQ6_A LP4_DQ6_B | LP4X_DQ6_B | LP5_DQ6_B G1 DDR_DQ7_B
LP4_DQ7_A | LP4X_DQ7_A | LP5_DQ7_A LP4_DQ7_B | LP4X_DQ7_B | LP5_DQ7_B DDR_DM0_A LPDDR4_DMI0_A
DDR_DM0_A 1V1 B4 DDR_DM0_B
LP4_DMI0_A | LP4X_DMI0_A | LP5_DMI0_A LP4_DMI0_B | LP4X_DMI0_B | LP5_DMI0_B
DDR_DQS0P_A 1U1 H1 DDR_DQS0P_B
DDR_DQS0N_A Y1 LP4_DQS0P_A | LP4X_DQS0P_A | LP5_RDQS0P_A LP4_DQS0P_B | LP4X_DQS0P_B | LP5_RDQS0P_B 1F1 DDR_DQS0N_B
LP4_DQS0N_A | LP4X_DQS0N_A | LP5_RDQS0N_A LP4_DQS0N_B | LP4X_DQS0N_B | LP5_RDQS0N_B DDR_DQ8_A LPDDR4_DQ8_A
1V5 1G5 DDR_DQ9_A LPDDR4_DQ9_A
1V4 -- | -- | LP5_WCK0P_A -- | -- | LP5_WCK0P_B 1G4 DDR_DQ10_A
-- | -- | LP5_WCK0N_A -- | -- | LP5_WCK0N_B LPDDR4_DQ10_A
DDR_DQ11_A LPDDR4_DQ11_A
DDR_DQ12_A LPDDR4_DQ12_A
DDR_DQ8_A AF1 1A1 DDR_DQ8_B DDR_DQ13_A LPDDR4_DQ13_A
DDR_DQ9_A 1AB1 LP4_DQ8_A | LP4X_DQ8_A | LP5_DQ8_A LP4_DQ8_B | LP4X_DQ8_B | LP5_DQ8_B B1 DDR_DQ9_B DDR_DQ14_A
LP4_DQ9_A | LP4X_DQ9_A | LP5_DQ9_A LP4_DQ9_B | LP4X_DQ9_B | LP5_DQ9_B LPDDR4_DQ14_A
DDR_DQ10_A 1AD1 B2 DDR_DQ10_B DDR_DQ15_A LPDDR4_DQ15_A
DDR_DQ11_A AH1 LP4_DQ10_A | LP4X_DQ10_A | LP5_DQ10_A LP4_DQ10_B | LP4X_DQ10_B | LP5_DQ10_B A2 DDR_DQ11_B
DDR_DQ12_A 1Y1 LP4_DQ11_A | LP4X_DQ11_A | LP5_DQ11_A LP4_DQ11_B | LP4X_DQ11_B | LP5_DQ11_B 1E1 DDR_DQ12_B DDR_DQS1P_A
LP4_DQ12_A | LP4X_DQ12_A | LP5_DQ12_A LP4_DQ12_B | LP4X_DQ12_B | LP5_DQ12_B LPDDR4_DQS1P_A
DDR_DQ13_A 1W2 1C1 DDR_DQ13_B DDR_DQS1N_A LPDDR4_DQS1N_A
DDR_DQ14_A 1AA3 LP4_DQ13_A | LP4X_DQ13_A | LP5_DQ13_A LP4_DQ13_B | LP4X_DQ13_B | LP5_DQ13_B E1 DDR_DQ14_B
DDR_DQ15_A 1AA1 LP4_DQ14_A | LP4X_DQ14_A | LP5_DQ14_A LP4_DQ14_B | LP4X_DQ14_B | LP5_DQ14_B D1 DDR_DQ15_B DDR_DM1_A
LP4_DQ15_A | LP4X_DQ15_A | LP5_DQ15_A LP4_DQ15_B | LP4X_DQ15_B | LP5_DQ15_B LPDDR4_DMI1_A
DDR_DM1_A AE1 1B1 DDR_DM1_B DDR_A0_A LPDDR4_A0_A
LP4_DMI1_A | LP4X_DMI1_A | LP5_DMI1_A LP4_DMI1_B | LP4X_DMI1_B | LP5_DMI1_B DDR_A1_A LPDDR4_A1_A
DDR_DQS1P_A 1AB4 A3 DDR_DQS1P_B DDR_A2_A LPDDR4_A2_A
DDR_DQS1N_A 1AB3 LP4_DQS1P_A | LP4X_DQS1P_A | LP5_RDQS1P_A LP4_DQS1P_B | LP4X_DQS1P_B | LP5_RDQS1P_B B3 DDR_DQS1N_B DDR_A3_A
LP4_DQS1N_A | LP4X_DQS1N_A | LP5_RDQS1N_A LP4_DQS1N_B | LP4X_DQS1N_B | LP5_RDQS1N_B LPDDR4_A3_A
DDR_A4_A LPDDR4_A4_A
1AA6 1D4 DDR_A5_A LPDDR4_A5_A
1AA5 -- | -- | LP5_WCK1P_A -- | -- | LP5_WCK1P_B 1E4
-- | -- | LP5_WCK1N_A -- | -- | LP5_WCK1N_B
C C
DDR_A0_A T1 L1 DDR_A0_B
DDR_A1_A 1N1 LP4_A0_A | LP4X_A0_A | LP5_A0_A LP4_A0_B | LP4X_A0_B | LP5_A0_B 1J1 DDR_A1_B
DDR_A2_A 1R3 LP4_A1_A | LP4X_A1_A | LP5_A1_A LP4_A1_B | LP4X_A1_B | LP5_A1_B 1J3 DDR_A2_B DDR_CLKP_A
LP4_A2_A | LP4X_A2_A | LP5_A2_A LP4_A2_B | LP4X_A2_B | LP5_A2_B LPDDR4_CLKP_A
DDR_A3_A 1T2 1G2 DDR_A3_B DDR_CLKN_A LPDDR4_CLKN_A
DDR_A4_A 1M5 LP4_A3_A | LP4X_A3_A | LP5_A3_A LP4_A3_B | LP4X_A3_B | LP5_A3_B 1F4 DDR_A4_B
DDR_A5_A 1P5 LP4_A4_A | LP4X_A4_A | LP5_A4_A LP4_A4_B | LP4X_A4_B | LP5_A4_B 1K5 DDR_A5_B DDR_DQ0_B
LP4_A5_A | LP4X_A5_A | LP5_A5_A LP4_A5_B | LP4X_A5_B | LP5_A5_B LPDDR4_DQ0_B
1R5 1H5 DDR_DQ1_B LPDDR4_DQ1_B
-- | -- | LP5_A6_A -- | -- | LP5_A6_B DDR_DQ2_B LPDDR4_DQ2_B
DDR_CLKP_A 1L1 1K1 DDR_CLKP_B DDR_DQ3_B LPDDR4_DQ3_B
DDR_CLKN_A P1 LP4_CLKP_A | LP4X_CLKP_A | LP5_CLKP_A LP4_CLKP_B | LP4X_CLKP_B | LP5_CLKP_B N1 DDR_CLKN_B DDR_DQ4_B
LP4_CLKN_A | LP4X_CLKN_A | LP5_CLKN_A LP4_CLKN_B | LP4X_CLKN_B | LP5_CLKN_B LPDDR4_DQ4_B
DDR_DQ5_B LPDDR4_DQ5_B
LPDDR4_CSN0_A 1R4 1J5 LPDDR4_CSN0_B DDR_DQ6_B LPDDR4_DQ6_B
LPDDR4_CSN1_A 1T4 LP4_CSN0_A | LP4X_CSN0_A | -- LP4_CSN0_B | LP4X_CSN0_B | -- 1K4 LPDDR4_CSN1_B DDR_DQ7_B
LP4_CSN1_A | LP4X_CSN1_A | -- LP4_CSN1_B | LP4X_CSN1_B | -- LPDDR4_DQ7_B
LPDDR4_CKE0/LPDDR5_CS0_A 1N3 1K2 LPDDR4_CKE0/LPDDR5_CS0_B DDR_DQS0P_B LPDDR4_DQS0P_B
LPDDR4_CKE1/LPDDR5_CS1_A 1N5 LP4_CKE0_A | LP4X_CKE0_A | LP5_CSN0_A LP4_CKE0_B | LP4X_CKE0_B | LP5_CSN0_B 1M3 LPDDR4_CKE1/LPDDR5_CS1_B DDR_DQS0N_B
LP4_CKE1_A | LP4X_CKE1_A | LP5_CSN1_A LP4_CKE1_B | LP4X_CKE1_B | LP5_CSN1_B LPDDR4_DQS0N_B
DDR_DM0_B LPDDR4_DMI0_B
VDDQ_DDR_S0 1U5 DDR_RESET VDDQ_DDR_S0
LP4_RESET | LP4X_RESET | LP5_RESET
R1200 240R ZQ_A 1R6 1J6 ZQ_B R1201 240R 1%
VDDA_DDR_PLL_S0 1% R0201 ZQ_A ZQ_B R0201
VDDQ_DDR_CKE_S3 DDR_DQ8_B
Note2 DDR_PLL Power LP4/4X_CKE&LP5_CS & Reset Power Note2 DDR_DQ9_B
LPDDR4_DQ8_B
2C3 LPDDR4_DQ9_B
VCCA_1V8_S0 DDRPHY_PLL_DVDD 2B2 DDR_DQ10_B
LPDDR4/4X=1.1V LPDDR4_DQ10_B
LPDDR5=1.05V DDRPHY_CKE_VDDQ DDR_DQ11_B LPDDR4_DQ11_B
DDR_PLL_AVDD1V8 2D2 DDR_DQ12_B LPDDR4_DQ12_B
DDRPHY_PLL_AVDD1V8 1.8V
R1202 C1212 C1213 DDR_DQ13_B LPDDR4_DQ13_B
B 0R 1uF 1uF DDR_DQ14_B B
CK Power LPDDR4_DQ14_B
2 1

2 1

R0402 Note1 X5R X5R LPDDR4/4X=0.6V 2D1 DDR_DQ15_B LPDDR4_DQ15_B

6.3V 6.3V LPDDR5=0.5V DDRPHY_CK_VDDQ
DDR_PLL_AVSS C0201 C0201 2C2 DDR_DQS1P_B LPDDR4_DQS1P_B
DDRPHY_PLL_AVSS VDDQ_DDR_S0 DDR_DQS1N_B
VDD_DDR_S0 LPDDR4_DQS1N_B
R1203 DDR Digital Core Power DDR IO Power
NC/0R (Except for ck, 2E1 DDR_DM1_B LPDDR4_DMI1_B
R0201 2E2 cke and reset) DDRPHY_VDDQ_0 2F1
2F3 DDRPHY_DVDD_0 LPDDR4/4X=0.6V DDRPHY_VDDQ_1 2F2 DDR_A0_B
DDRPHY_DVDD_1 DDRPHY_VDDQ_2 LPDDR4_A0_B
2G2 LPDDR5=0.5V 2G1 DDR_A1_B LPDDR4_A1_B
2G3 DDRPHY_DVDD_2 DDRPHY_VDDQ_3 2H1 DDR_A2_B
DDRPHY_DVDD_3 DDRPHY_VDDQ_4 LPDDR4_A2_B
2H2 2J2 DDR_A3_B LPDDR4_A3_B
DDRPHY_DVDD_4 DDRPHY_VDDQ_5 DDR_A4_B LPDDR4_A4_B
DDR_A5_B LPDDR4_A5_B
RK3576
BGA698_16R1x17R2x1R18

DDR FILTER
VDD_DDR_S0 DDR_CLKP_B
VDDQ_DDR_S0 LPDDR4_CLKP_B
DDR_CLKN_B
Note: LPDDR4_CLKN_B
C1219 C1220 (1) Power Sequence: VDD-VDDQ_CKE-VDDQ LPDDR4_CKE0/LPDDR5_CS0_A LPDDR4_CKE0_A
C1200 C1201 C1202 C1215 C1216 C1203 C1204 100nF 100nF LPDDR4_CKE1/LPDDR5_CS1_A
(2) Hold power of DDRPHY_CKE_VDDQ LPDDR4_CKE1_A
2 1

2 1

100nF 1uF 1uF 1uF 1uF 10uF 22uF X5R X5R

during retention times.
2 1

2 1

2 1

2 1

2 1

2 1

2 1

Note1 X5R X5R X5R X5R X5R X5R X5R 6.3V 6.3V LPDDR4_CKE0/LPDDR5_CS0_B LPDDR4_CKE0_B
6.3V 6.3V 6.3V 6.3V 6.3V 4V 6.3V C0201 C0201 LPDDR4_CKE1/LPDDR5_CS1_B LPDDR4_CKE1_B
C0201 C0201 C0201 C0201 C0201 C0402 C0603
DDR_RESET
A Note1: LPDDR4_RESET A
VDD_DDR_S0 LPDDR4_CSN0_A
VDDQ_DDR_CKE_S3
Caps in the red line dotted box LPDDR4_CSN1_A
LPDDR4_CSN0_A
should be placed under the U1000 package LPDDR4_CSN1_A
LPDDR4_CSN0_B LPDDR4_CSN0_B
C1206 C1208 C1209 C1217 C1207 C1210
Note2: LPDDR4_CSN1_B LPDDR4_CSN1_B Rockchip Electronics Co., Ltd
100nF 1uF 1uF 1uF 10uF 22uF C1214
2 1

2 1

2 1

2 1

2 1

2 1

2 1

Note1 X5R X5R X5R X5R X5R X5R Note1 1uF Resistors in the red line dotted box
6.3V 6.3V 6.3V 6.3V 4V 6.3V X5R
Project: TB-RK3576D0
C0201 C0201 C0201 C0201 C0402 C0603 6.3V should be placed under the U1000 package
C0201
File: 12.RK3576-DDR PHY
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 13 of 50

5 4 3 2 1
 5 4 3 2 1

RK3576_B U1000B
UFS2.1
PWM-G1/G2/G3/G4
U1000K
VCCIO7 Domain
Operating Voltage=1.2V/1.8V
(UFS2.1) HS-G1/G2/G3
UFS_TX_D0P
UFS_TX_D0N
1AD6
1AC6
UFS_TX_D0P
UFS_TX_D0N
UFS_RSTN | GPIO4_D0_d
UFS_REFCLK | GPIO4_D1_d
1AD2
AK4 UFS_SOC_REFCLK R1306 0R R0201
UFS_RSTn
UFS_REFCLK
1AD4 UFS_TX_D1P 2M3 VDDA_1V2_S0
UFS_TX_D1P 1AD5 VCCIO7_VCC
UFS_TX_D1N UFS_TX_D1N
C1300

2 1
AK8 1uF
UFS_RX_D0P UFS_RX_D0P
AL7 OSC for UFS X5R
UFS_RX_D0N UFS_RX_D0N
D 6.3V D
AK7
Operating Voltage=1.2V/1.8V C0201
UFS_RX_D1P UFS_RX_D1P
AL6 AL5 OSC_UFS_XOUT R1300 22R R0201
UFS_RX_D1N UFS_RX_D1N OSC_UFS_XOUT
2R2 UFS_TX_REXT R1301 8.2K R1302 Y1300
UFS_TX_REXT 1% R0201 510K 4 1
R0201 GND X1
2N2 UFS_AVDD0V85 R1320 0R VDDA_0V85_S0 AK5 OSC_UFS_XIN 1% 3 2 C1301
UFS_AVDD0V85 5% R0402 OSC_UFS_XIN C1304 X2 GND 18pF

2 1
C1302 C1310 Option 18pF 26.000MHz C0G

2 1

2 1

2 1
1uF 1uF C0G CRY4_2R00X1R60X0R55 25V
X5R X5R Ferrite Bead 25V C0201
6.3V 6.3V BLM18PG181SN1 C0201
C0201 C0201
2P2 UFS_AVDD1V8 R1323 0R VCCA_1V8_S0 2M2 VCCA_1V8_S0
UFS_AVDD1V8 5% R0402 OSC_UFS_AVDD
C1305 C1311 C1307

2 1

2 1

2 1
1uF 1uF 100nF
RK3576 X5R X5R RK3576 X5R
BGA698_16R1x17R2x1R18 6.3V 6.3V BGA698_16R1x17R2x1R18 6.3V
C0201 C0201 C0201

U1000C

RK3576_C VCCIO0 Domain

Operating Voltage=1.8V

C
(VCCIO0) --
--
--
|
|
|
--
--
--
|
|
|
I2C2_SCL_M1
I2C2_SDA_M1
UART6_RTSN_M2
|
|
|
UART7_RTSN_M1
UART7_CTSN_M1
UART7_TX_M1
|
|
|
--
--
PDM0_SDI3_M1
|
|
|
--
--
SAI0_SDI3_M2
|
|
|
SAI0_SCLK_M2
SAI0_LRCK_M2
SAI0_SDO1_M2
|
|
|
FSPI0_D0
FSPI0_D1
FSPI0_D2
|
|
|
EMMC_D0
EMMC_D1
EMMC_D2
|
|
|
GPIO1_A0_u
GPIO1_A1_u
GPIO1_A2_u
E28
E29
1C24
F28
eMMC_D0/FLASH_D0
eMMC_D1/FLASH_D1
eMMC_D2/FLASH_D2
eMMC_D3/FLASH_D3
C

-- | -- | UART6_CTSN_M2 | UART7_RX_M1 | PDM0_SDI1_M1 | SAI0_SDI2_M2 | SAI0_SDO2_M2 | FSPI0_D3 | EMMC_D3 | GPIO1_A3_u 1D24

-- | -- | -- | SPI0_CSN0_M2 | -- | SAI3_MCLK_M0 | SAI0_MCLK_M2 | FSPI0_D4 | EMMC_D4 | GPIO1_A4_u eMMC_D4/FLASH_D4
G28 eMMC_D5/FLASH_D5
-- | -- | I2C9_SCL_M0 | SPI0_MOSI_M2 | PDM0_SDI2_M1 | SAI3_SCLK_M0 | -- | FSPI0_D5 | EMMC_D5 | GPIO1_A5_u D28
-- | -- | I2C9_SDA_M0 | SPI0_MISO_M2 | PDM0_CLK1_M1 | SAI3_LRCK_M0 | -- | FSPI0_D6 | EMMC_D6 | GPIO1_A6_u eMMC_D6/FLASH_D6
1B24 eMMC_D7/FLASH_D7
-- | -- | -- | SPI0_CLK_M2 | -- | SAI3_SDI_M0 | SAI0_SDO0_M2 | FSPI0_D7 | EMMC_D7 | GPIO1_A7_u
1F22 eMMC_CMD/FLASH_RSTN
-- | -- | I2C7_SCL_M0 | UART6_TX_M2 | -- | -- | FSPI0_CSN1 | FSPI0_RSTN | EMMC_CMD | GPIO1_B0_u 1G23 R1367 22R R0201
PWM2_CH7_M1 | -- | -- | -- | PDM0_CLK0_M1 | SAI0_SDI1_M2 | SAI0_SDO3_M2 | FSPI0_CLK | EMMC_CLK | GPIO1_B1_d eMMC_CLKOUT/FLASH_CLK
1F23 eMMC_STROBE/FLASH_DQS
-- | -- | -- | SPI0_CSN1_M2 | PDM0_SDI0_M1 | SAI3_SDO_M0 | SAI0_SDI0_M2 | FSPI0_DQS | EMMC_STRB | GPIO1_B2_d 1D23
PWM2_CH1_M0 | MIPI_TE_M3 | I2C7_SDA_M0 | UART6_RX_M2 | -- | -- | -- | FSPI0_CSN0 | EMMC_RSTN | GPIO1_B3_u eMMC_RSTn/FLASH_CSN0
VCCIO_1V8_S0

1J20
VCCIO0_VCC1V8
C1308

2 1
RK3576 1uF
BGA698_16R1x17R2x1R18 X5R
6.3V
C0201

U1000D

RK3576_D VCCIO1 Domain

Operating Voltage=1.8V/3.3V

B
(VCCIO1) PWM2_CH2_M0
PWM2_CH3_M0
I3C1_SCL_M1
|
|
|
CAN0_RX_M0
CAN0_TX_M0
CAN1_RX_M0
|
|
|
SPI0_MOSI_M1
SPI0_MISO_M1
SPI0_CSN1_M1
|
|
|
I2C8_SCL_M0
I2C8_SDA_M0
--
|
|
|
UART7_RX_M2
UART7_TX_M2
UART5_RTSN_M2
|
|
|
UART0_RX_M1
UART0_TX_M1
JTAG_TCK_M0
|
|
|
--
--
--
|
|
|
--
SAI3_MCLK_M3
SAI3_LRCK_M3
|
|
|
DSM_AUD_LP_M0
DSM_AUD_LN_M0
DSM_AUD_RP_M0
|
|
|
FSPI1_D0_M0
FSPI1_D1_M0
FSPI1_D2_M0
|
|
|
SDMMC0_D0
SDMMC0_D1
SDMMC0_D2
|
|
|
GPIO2_A0_d
GPIO2_A1_d
GPIO2_A2_d
B24
B25
A23
B23
SDMMC0_D0
SDMMC0_D1
SDMMC0_D2
SDMMC0_D3
B

I3C1_SDA_M1 | CAN1_TX_M0 | -- | -- | UART5_CTSN_M2 | JTAG_TMS_M0 | -- | SAI3_SDI_M3 | DSM_AUD_RN_M0 | FSPI1_D3_M0 | SDMMC0_D3 | GPIO2_A3_d 1A21
PWM2_CH4_M0 | -- | SPI0_CSN0_M1 | I2C5_SDA_M0 | -- | UART5_RX_M2 | -- | SAI3_SDO_M3 | -- | FSPI1_CSN0_M0 | SDMMC0_CMD | GPIO2_A4_d SDMMC0_CMD
1B21 SDMMCCLK SDMMC0_CLK
I3C1_SDA_PU_M1 | -- | SPI0_CLK_M1 | I2C5_SCL_M0 | -- | UART5_TX_M2 | TEST_CLK_OUT | SAI3_SCLK_M3 | -- | FSPI1_CLK_M0 | SDMMC0_CLK | GPIO2_A5_d R1353 22R R0201

2A8 VCCIO_SD_S0
VCCIO1_VCC
C1309
RK3576 100nF

2 1
BGA698_16R1x17R2x1R18 X5R
6.3V
C0201

Note:
Caps of between dashed red lines and U1000
should be placed under the U1000 package.
Other caps should be placed close to the
U1000 package

A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 13.RK3576-eMMC/UFS/SD
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 14 of 50

5 4 3 2 1
 5 4 3 2 1
U1000L
USB3 OTG0/DP1.4 Alt
RK3576_L USB:USB3.2 Gen1x1 OTG0
DP :RBR/HBR/HBR2/HBR3

(USB3/DP) --
--
| DP_TX_AUXP
| DP_TX_AUXN
2T2
2T3

AK10
USB3_OTG0_SSRX1P | DP_TX_D0P USB3_OTG0_SSRX1P/DP_TX_D0P
AL10
USB3_OTG0_SSRX1N | DP_TX_D0N USB3_OTG0_SSRX1N/DP_TX_D0N
D D
AL11 USB3_OTG0_SSTX1P/DP_TX_D1P
USB3_OTG0_SSTX1P | DP_TX_D1P AK11
USB3_OTG0_SSTX1N | DP_TX_D1N USB3_OTG0_SSTX1N/DP_TX_D1N
AK12
USB3_OTG0_SSRX2P | DP_TX_D2P AL12
USB3_OTG0_SSRX2N | DP_TX_D2N
AL13
USB3_OTG0_SSTX2P | DP_TX_D3P AK13
USB3_OTG0_SSTX2N | DP_TX_D3N
2T7 USB3_OTG0_DP_TX_REXT R1400 8.2K 1%
USB3_OTG0_REXT | DP_TX_REXT R0201
2M5 VDDA_0V85_S0
USB3_OTG0_DP_TX_AVDD0V85 2N5 C1400
USB3_OTG0_DP_TX_DVDD0V85 1uF

2 1
X5R
6.3V
C0201
Note:
USB3_OTG0_DP_TX_AVDD1V8
2N4 VCCA_1V8_S0 Caps of between dashed red lines and U1000
C C1402 C
1uF should be placed under the U1000 package.
Other caps should be placed close to the

2 1
X5R
RK3576 6.3V U1000 package
BGA698_16R1x17R2x1R18 C0201

U1000M

RK3576_M USB2 OTG0

OTG/HOST/DEVICE
HS/FS/LS Download Port AK9 USB2_OTG0_DP

(USB2)
USB2_OTG0_DP AL9
USB2_OTG0_DM USB2_OTG0_DM
2R6
USB2_OTG0_ID
40K 2P3
USB2_OTG0_VBUSDET USB2_OTG0_VBUSDET
C1404
2R3 USB2_OTG0_REXT R1401 200R 1% 100nF

2 1
USB2_OTG0_REXT R0201 X5R
USB2 OTG1 6.3V
2T4 C0201
B OTG/HOST/DEVICE USB2_OTG1_DP USB2_HOST1_DP B
2T5
HS/FS/LS USB2_OTG1_DM USB2_HOST1_DM
2T9
USB2_OTG1_ID
40K 2T10
USB2_OTG1_VBUSDET USB2_OTG1_VBUSDET
C1410
2U8 USB2_HOST1_REXT R1402 200R 1% 100nF

2 1
USB2_OTG1_REXT R0201 X5R
2P5 USB2_OTG_DVDD0V75 R1407 0R VDDA_0V75_S0 6.3V
USB2_OTG_DVDD0V75 C1405 R0201 C0201
100nF
2 1

X5R
6.3V
C0201

2P4 USB2_OTG_AVDD1V8 R1409 0R VCCA_1V8_S0

USB2_OTG_AVDD1V8 C1406 R0201
100nF
2 1

X5R
A
6.3V A
C0201
Rockchip Electronics Co., Ltd
2P7 USB2_OTG_AVDD3V3 R1412 0R VCC_3V3_S0
USB2_OTG_AVDD3V3 C1408 R0201 Project: TB-RK3576D0
100nF
2 1

X5R File: 14.RK3576-TypeC/USB

RK3576 6.3V
BGA698_16R1x17R2x1R18 C0201 Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 15 of 50

5 4 3 2 1
 5 4 3 2 1

RK3576_O(MIPI DCPHY) RK3576_P(MIPI DPHY CSI RX)

D D

U1000P

U1000O
MIPI DPHY CSI1/2 RX
MIPI V1.2/2.5Gbps
MIPI DCPHY DSI TX
AE28
D-PHY:V2.0 4.5Gbps/Lane MIPI_DPHY_CSI1_RX_D0N | -- AE29
C-PHY:V1.1 5.7Gbps/Trio MIPI_DPHY_CSI1_RX_D0P | --
AF28
AK15 MIPI_DPHY_CSI1_RX_D1N | -- AF29
MIPI_DPHY_DSI_TX_D0N | MIPI_CPHY_DSI_TX_TRIO0_A MIPI_DPHY_DSI_TX_D0N MIPI_DPHY_CSI1_RX_D1P | --
AL15 MIPI_DPHY_DSI_TX_D0P
MIPI_DPHY_DSI_TX_D0P | MIPI_CPHY_DSI_TX_TRIO0_B 1AC23
AK16 MIPI_DPHY_CSI1_RX_CLKN | -- 1AC22
MIPI_DPHY_DSI_TX_D1N | MIPI_CPHY_DSI_TX_TRIO0_C MIPI_DPHY_DSI_TX_D1N MIPI_DPHY_CSI1_RX_CLKP | --
AL16 MIPI_DPHY_DSI_TX_D1P
MIPI_DPHY_DSI_TX_D1P | MIPI_CPHY_DSI_TX_TRIO1_A AG28
AK17 MIPI_DPHY_CSI1_RX_D2N | MIPI_DPHY_CSI2_RX_D0N AG29
MIPI_DPHY_DSI_TX_CLKN | MIPI_CPHY_DSI_TX_TRIO1_B MIPI_DPHY_DSI_TX_CLKN MIPI_DPHY_CSI1_RX_D2P | MIPI_DPHY_CSI2_RX_D0P
AL17 MIPI_DPHY_DSI_TX_CLKP
MIPI_DPHY_DSI_TX_CLKP | MIPI_CPHY_DSI_TX_TRIO1_C AH28
AK18 MIPI_DPHY_CSI1_RX_D3N | MIPI_DPHY_CSI2_RX_D1N AH29
MIPI_DPHY_DSI_TX_D2N | MIPI_CPHY_DSI_TX_TRIO2_A MIPI_DPHY_DSI_TX_D2N MIPI_DPHY_CSI1_RX_D3P | MIPI_DPHY_CSI2_RX_D1P
AL18 MIPI_DPHY_DSI_TX_D2P
MIPI_DPHY_DSI_TX_D2P | MIPI_CPHY_DSI_TX_TRIO2_B 1AD22
AK19 -- | MIPI_DPHY_CSI2_RX_CLKN 1AD21
MIPI_DPHY_DSI_TX_D3N | MIPI_CPHY_DSI_TX_TRIO2_C MIPI_DPHY_DSI_TX_D3N -- | MIPI_DPHY_CSI2_RX_CLKP
C AL19 MIPI_DPHY_DSI_TX_D3P C
MIPI_DPHY_DSI_TX_D3P | NO_USE
MIPI DCPHY CSI RX 2L11
MIPI_DPHY_CSI1/2_RX_AVDD0V75
D-PHY:V2.0 4.5Gbps/Lane
C-PHY:V1.1 5.7Gbps/Trio

AL20 MIPI_DPHY_CSI0_RX_D0N
MIPI_DPHY_CSI0_RX_D0N | MIPI_CPHY_CSI_RX_TRIO0_A AK20
MIPI_DPHY_CSI0_RX_D0P | MIPI_CPHY_CSI_RX_TRIO0_B MIPI_DPHY_CSI0_RX_D0P
1W20
AL21 MIPI_DPHY_CSI1/2_RX_AVDD1V8
MIPI_DPHY_CSI0_RX_D1N | MIPI_CPHY_CSI_RX_TRIO0_C MIPI_DPHY_CSI0_RX_D1N
AK21 MIPI_DPHY_CSI0_RX_D1P
MIPI_DPHY_CSI0_RX_D1P | MIPI_CPHY_CSI_RX_TRIO1_A
AL22 MIPI_DPHY_CSI0_RX_CLKN MIPI DPHY CSI3/4 RX
MIPI_DPHY_CSI0_RX_CLKN | MIPI_CPHY_CSI_RX_TRIO1_B AK22
MIPI_DPHY_CSI0_RX_CLKP | MIPI_CPHY_CSI_RX_TRIO1_C MIPI_DPHY_CSI0_RX_CLKP MIPI V1.2/2.5Gbps
AL23 MIPI_DPHY_CSI0_RX_D2N H29 MIPI_DPHY_CSI3_RX_D0N
MIPI_DPHY_CSI0_RX_D2N | MIPI_CPHY_CSI_RX_TRIO2_A AK23 MIPI_DPHY_CSI3_RX_D0N | -- H28
MIPI_DPHY_CSI0_RX_D2P | MIPI_CPHY_CSI_RX_TRIO2_B MIPI_DPHY_CSI0_RX_D2P MIPI_DPHY_CSI3_RX_D0P | -- MIPI_DPHY_CSI3_RX_D0P
AL24 MIPI_DPHY_CSI0_RX_D3N J29 MIPI_DPHY_CSI3_RX_D1N
MIPI_DPHY_CSI0_RX_D3N | MIPI_CPHY_CSI_RX_TRIO2_C AK24 MIPI_DPHY_CSI3_RX_D1N | -- J28
MIPI_DPHY_CSI0_RX_D3P | NO_USE MIPI_DPHY_CSI0_RX_D3P MIPI_DPHY_CSI3_RX_D1P | -- MIPI_DPHY_CSI3_RX_D1P
1H23 MIPI_DPHY_CSI3_RX_CLKN
MIPI_DCPHY_VREG 1 2 X5R 6.3V MIPI_DPHY_CSI3_RX_CLKN | --
MIPI_DCPHY_VREG
2N7 C1503 1uF
C0201 MIPI_DPHY_CSI3_RX_CLKP | --
1H22 MIPI_DPHY_CSI3_RX_CLKP PI5
2M7 VDDA_0V75_S0 K29 MIPI_DPHY_CSI3_RX_D2N
MIPI_DCPHY_AVDD C1504 MIPI_DPHY_CSI3_RX_D2N | MIPI_DPHY_CSI4_RX_D0N K28
MIPI_DPHY_CSI3_RX_D2P | MIPI_DPHY_CSI4_RX_D0P MIPI_DPHY_CSI3_RX_D2P
1uF
2 1

X5R L29 MIPI_DPHY_CSI3_RX_D3N

B 6.3V D-PHY 4.5Gbps & C-PHY 2.5Gsps 0.85V MIPI_DPHY_CSI3_RX_D3N | MIPI_DPHY_CSI4_RX_D1N L28 B
MIPI_DPHY_CSI3_RX_D3P | MIPI_DPHY_CSI4_RX_D1P MIPI_DPHY_CSI3_RX_D3P
C0201 D-PHY 2.5Gbps & C-PHY 1.5Gsps 0.75V
1K23
2M8 -- | MIPI_DPHY_CSI4_RX_CLKN 1K22
MIPI_DCPHY_AVDD1V2 VDDA_1V2_S0 -- | MIPI_DPHY_CSI4_RX_CLKP
C1506
1uF
2 1

X5R 2D11 VDDA_0V75_S0

6.3V MIPI_DPHY_CSI3/4_RX_AVDD0V75 C1507
C0201 100nF

2 1
X5R
2P8 VCCA_1V8_S0 6.3V
MIPI_DCPHY_AVDD1V8 C1509 C0201
1uF
2 1

X5R 2D12 VCCA_1V8_S0

RK3576 6.3V MIPI_DPHY_CSI3/4_RX_AVDD1V8 C1510
BGA698_16R1x17R2x1R18 C0201 1uF

2 1
X5R
RK3576 6.3V
BGA698_16R1x17R2x1R18 C0201

Note:
Caps of between dashed red lines and U1000
Note:
should be placed under the U1000 package. Caps of between dashed red lines and U1000
Other caps should be placed close to the should be placed under the U1000 package.
U1000 package Other caps should be placed close to the
U1000 package
A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 15.RK3576-MIPI DSI/CSI
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 16 of 50

5 4 3 2 1
 5 4 3 2 1

RK3576_Q(HDMI/eDP)
D D

Note:
HDMI 2.1 supports up to 4Kx2K@120Hz
U1000Q
HDMI TX/eDP TX Combo Phy
HDMI:V2.1 12Gbps
eDP :V1.3 5.4Gbps
2T12 HDMI_TX_SBDP
HDMI_TX_SBDP | EDP_TX_AUXP 2U12
HDMI_TX_SBDN | EDP_TX_AUXN HDMI_TX_SBDN
1AE24 HDMI_TX_D0P
HDMI_TX_D0P | EDP_TX_D0P AK27
HDMI_TX_D0N | EDP_TX_D0N HDMI_TX_D0N
AK28 HDMI_TX_D1P
HDMI_TX_D1P | EDP_TX_D1P AL28
C HDMI_TX_D1N C
HDMI_TX_D1N | EDP_TX_D1N
AJ28 HDMI_TX_D2P
HDMI_TX_D2P | EDP_TX_D2P AK29
HDMI_TX_D2N | EDP_TX_D2N HDMI_TX_D2N
AL26 HDMI_TX_D3P
HDMI_TX_D3P | EDP_TX_D3P AK26
HDMI_TX_D3N | EDP_TX_D3N HDMI_TX_D3N
1AA20 HDMI_TX_REXT/eDP_TX_REXT R1600 8.2K 1%
HDMI_TX_REXT | EDP_TX_REXT R0201

2N11 VDDA0V75_HDMI_S0
HDMI_TX_EDP_TX_AVDDD0V75 2P11 C1600 C1601
HDMI_TX_EDP_TX_AVDDC0V75 1uF 4.7uF

2 1

2 1
X5R X5R
6.3V 6.3V
C0201 C0402_BGA

2N10 HDMI_TX/eDP_TX_AVDD1V8 VCCA_1V8_S0

HDMI_TX_EDP_TX_AVDDIO1V8 2P10 C1602 C1603
B B
HDMI_TX_EDP_TX_AVDDCMN1V8 1uF 4.7uF

2 1

2 1
X5R X5R
6.3V 6.3V
RK3576 C0201 C0402_BGA
BGA698_16R1x17R2x1R18

Note:
Caps of between dashed red lines and U1000
should be placed under the U1000 package.
Other caps should be placed close to the
U1000 package

A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 16.RK3576-HDMI/eDP
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 17 of 50

5 4 3 2 1
 5 4 3 2 1

RK3576_N(PCIE/SATA/USB3) Note:
Caps of between dashed red lines and U1000
should be placed under the U1000 package.
U1000N
Other caps should be placed close to the
PCIE0/SATA0 Combo PHY0 U1000 package
1N22 PCIE0_REFCLKP
D PCIE0_REFCLKP | -- 1N23 D
PCIE0_REFCLKN | -- PCIE0_REFCLKN

PCIe0 (RC) P29 PCIE0_TXP

PCIE0_TXP | SATA0_TXP P28
Controller PCIE0_TXN | SATA0_TXN PCIE0_TXN

MUX
R28 PCIE0_RXP
PCIE0_RXP | SATA0_RXP R29
PCIE0_RXN | SATA0_RXN PCIE0_RXN
SATA0 HOST
Controller
2F11 VDDA_0V85_S0
PCIE0_SATA0_AVDD0V85 C1700
PCIE0:Gen1/Gen2 1uF
SATA0:Gen1/Gen2/Gen3

2 1
X5R
6.3V
C0201

2F12 VCCA_1V8_S0
PCIE0_SATA0_AVDD1V8 C1701
100nF

2 1
X5R
C 6.3V C
PCIE1/SATA1/USB3_OTG1 Combo PHY1 C0201

1L23
PCIe1 (RC) PCIE1_REFCLKP | -- | -- 1M23
Controller PCIE1_REFCLKN | -- | --
N28 PCIE1_TXP/USB3_HOST1_SSTXP USB3_HOST1_SSTXP
PCIE1_TXP | SATA1_TXP | USB3_OTG1_SSTXP N29 PCIE1_TXN/USB3_HOST1_SSTXN
PCIE1_TXN | SATA1_TXN | USB3_OTG1_SSTXN USB3_HOST1_SSTXN
SATA1 HOST M28 PCIE1_RXP/USB3_HOST1_SSRXP
MUX

PCIE1_RXP | SATA1_RXP | USB3_OTG1_SSRXP USB3_HOST1_SSRXP

Controller PCIE1_RXN | SATA1_RXN | USB3_OTG1_SSRXN
M29 PCIE1_RXN/USB3_HOST1_SSRXN USB3_HOST1_SSRXN

2E11 PCIE_ComboPHY_AVDD0V85 VDDA_0V85_S0

PCIE1_SATA1_USB3_OTG1_AVDD0V85
USB3 OTG1 C1702
Controller 4.7uF

2 1
X5R
6.3V
PCIE1:Gen1/Gen2 C0402
SATA1:Gen1/Gen2/Gen3
B B
USB :USB3.2 Gen1x1 OTG1 2E12 PCIE_ComboPHY_AVDD1V8
PCIE1_SATA1_USB3_OTG1_AVDD1V8 VCCA_1V8_S0
C1703 C1704
1uF 4.7uF

2 1

2 1
X5R X5R
6.3V 6.3V
RK3576 C0201 C0402
BGA698_16R1x17R2x1R18

A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 17.RK3576-PCIE/SATA/USB3
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 18 of 50

5 4 3 2 1
 5 4 3 2 1

RK3576_F(VCCIO2)
U1000F
VCCIO2 Domain
Operating Voltage=1.8V/3.3V
1D6 GPIO4_A2
PWM2_CH5_M0 | -- | -- | -- | -- | -- | AUPLL_CLK_IN_M2 | SAI4_MCLK_M0 | SAI1_MCLK_M0 | GPIO4_A2_d 1C6
PWM2_CH4_M1 | PCIE1_WAKEN_M2 | I2C2_SCL_M2 | UART5_RTSN_M1 | SPI3_CSN0_M2 | FLEXBUS1_CSN_M4 | -- | -- | SAI1_SCLK_M0 | GPIO4_A3_d GPIO4_A3/I2C2_SCL_M2
1C5 GPIO4_A4/I2C2_SDA_M2
CAN0_TX_M2 | -- | I2C4_SCL_M1 | UART6_TX_M0 | SPI3_MOSI_M2 | FLEXBUS0_D13_M1 | PDM1_SDI3_M1 | SAI4_SCLK_M0 | -- | GPIO4_A4_d 1B6
-- | PCIE1_CLKREQN_M2 | I2C2_SDA_M2 | UART5_CTSN_M1 | SPI4_CSN1_M2 | FLEXBUS1_D12_M1 | -- | -- | SAI1_LRCK_M0 | GPIO4_A5_d GPIO4_A5
D 1B5 GPIO4_A6 D
CAN0_RX_M2 | -- | I2C4_SDA_M1 | UART6_RX_M0 | SPI3_MISO_M2 | FLEXBUS0_D14_M1 | PDM1_CLK0_M1 | SAI4_LRCK_M0 | -- | GPIO4_A6_d A7
PWM2_CH6_M0 | -- | -- | -- | SPI3_CLK_M2 | -- | -- | SAI4_SDI_M0 | SAI1_SDO0_M0 | GPIO4_A7_d GPIO4_A7
1A5 GPIO4_B0
-- | UART2_RTSN_M1 | UART6_RTSN_M0 | UART5_TX_M1 | SPI4_CLK_M2 | FLEXBUS1_D13_M1 | PDM1_CLK1_M1 | SAI1_SDI3_M0 | SAI1_SDO1_M0 | GPIO4_B0_d B7
-- | UART2_CTSN_M1 | UART6_CTSN_M0 | UART5_RX_M1 | SPI4_MOSI_M2 | FLEXBUS1_D14_M1 | PDM1_SDI2_M1 | SAI1_SDI2_M0 | SAI1_SDO2_M0 | GPIO4_B1_d GPIO4_B1
B6 GPIO4_B2
-- | -- | MIPI_TE_M0 | -- | SPI4_MISO_M2 | FLEXBUS1_D15_M1 | PDM1_SDI1_M1 | SAI1_SDI1_M0 | SAI1_SDO3_M0 | GPIO4_B2_d 1A6
PWM2_CH7_M0 | -- | -- | SPI3_CSN1_M2 | SPI4_CSN0_M2 | -- | PDM1_SDI0_M1 | SAI4_SDO_M0 | SAI1_SDI0_M0 | GPIO4_B3_d GPIO4_B3
B8 GPIO4_B4/I2C3_SDA_M0
CAN1_RX_M2 | PCIE0_WAKEN_M2 | I2C3_SDA_M0 | UART2_RX_M1 | -- | FLEXBUS0_CSN_M4 | -- | -- | SPDIF_RX0_M0 | GPIO4_B4_d 1A4
CAN1_TX_M2 | PCIE0_CLKREQN_M2 | I2C3_SCL_M0 | UART2_TX_M1 | -- | FLEXBUS0_D15_M1 | -- | -- | SPDIF_TX0_M0 | GPIO4_B5_d GPIO4_B5/I2C3_SCL_M0

2A2 VCC_3V3_S0
VCCIO2_VCC C1800
100nF

2 1
RK3576 X5R
BGA698_16R1x17R2x1R18 6.3V
C0201

Note:
Caps of between dashed red lines and U1000
RK3576_G(VCCIO3) should be placed under the U1000 package.
Other caps should be placed close to the
U1000 package
U1000G
C VCCIO3 Domain C
Operating Voltage=1.8V/3.3V
A28 GMAC1_RXD2_M1
PWM1_CH0_M1 | PCIE1_CLKREQN_M1 | SPI1_CLK_M0 | I2C9_SDA_M1 | -- | -- | -- | SAI3_SCLK_M1 | -- | SDMMC1_D0_M0 | ETH1_RXD2_M1 | GPIO1_B4_d B27
PWM1_CH1_M1 | PCIE1_WAKEN_M1 | SPI1_MOSI_M0 | I2C9_SCL_M1 | -- | -- | -- | SAI3_LRCK_M1 | -- | SDMMC1_D1_M0 | ETH1_RXD3_M1 | GPIO1_B5_d GMAC1_RXD3_M1
1A23 GMAC1_RXCLK_M1
-- | PCIE0_CLKREQN_M1 | SPI1_MISO_M0 | -- | UART3_CTSN_M2 | -- | -- | SAI3_SDO_M1 | -- | SDMMC1_D2_M0 | ETH1_RXCLK_M1 | GPIO1_B6_d A27
-- | PCIE0_WAKEN_M1 | SPI1_CSN0_M0 | -- | UART3_RTSN_M2 | -- | -- | SAI3_SDI_M1 | -- | SDMMC1_D3_M0 | ETH1_TXD2_M1 | GPIO1_B7_d GMAC1_TXD2_M1 VCCIO_1V8_S0
B26 GMAC1_TXD3_M1
PWM0_CH0_M1 | -- | SPI1_CSN1_M0 | -- | UART3_TX_M2 | -- | PDM0_SDI2_M2 | -- | -- | SDMMC1_CMD_M0 | ETH1_TXD3_M1 | GPIO1_C0_d 1B22
-- | -- | -- | -- | UART3_RX_M2 | -- | PDM0_CLK0_M2 | SAI3_MCLK_M1 | -- | SDMMC1_CLK_M0 | ETH1_TXCLK_M1 | GPIO1_C1_d GMAC1_TXCLK_M1
B29 I2C6_SCL_M1_mipiCSI3
PWM1_CH2_M1 | -- | SPI2_CSN1_M1 | I2C6_SCL_M1 | UART4_RTSN_M1 | -- | -- | FSPI1_CSN1_M1 | FSPI1_RSTN_M1 | SDMMC1_PWREN_M0 | ETH1_PPSCLK_M1 | GPIO1_C2_u 1C23 R1800 R1801
-- | -- | SPI2_CSN0_M1 | I2C6_SDA_M1 | UART4_CTSN_M1 | -- | -- | -- | FSPI1_CSN0_M1 | SDMMC1_DETN_M0 | ETH1_PPSTRIG_M1 | GPIO1_C3_u I2C6_SDA_M1_mipiCSI3
1B23 2.2K 2.2K
-- | PCIE0_BUTTONRSTN | SPI2_MOSI_M1 | UART2_RTSN_M0 | UART4_TX_M1 | -- | -- | -- | FSPI1_D0_M1 | -- | ETH1_TXD0_M1 | GPIO1_C4_d GMAC1_TXD0_M1
B28 R0201 R0201
-- | PCIE1_BUTTONRSTN | SPI2_MISO_M1 | UART2_CTSN_M0 | UART4_RX_M1 | -- | -- | -- | FSPI1_D1_M1 | -- | ETH1_TXD1_M1 | GPIO1_C5_d GMAC1_TXD1_M1
A26 I2C6_SCL_M1_mipiCSI3
-- | SATA_CPPOD | -- | I2C8_SCL_M1 | UART2_TX_M0 | -- | PDM0_SDI0_M2 | -- | FSPI1_D2_M1 | -- | ETH1_TXCTL_M1 | GPIO1_C6_d GMAC1_TXEN_M1
1C22 GMAC1_RXD0_M1 I2C6_SDA_M1_mipiCSI3
-- | SATA_CPDET | -- | I2C8_SDA_M1 | UART2_RX_M0 | -- | PDM0_SDI1_M2 | -- | FSPI1_D3_M1 | -- | ETH1_RXD0_M1 | GPIO1_C7_d
C29 GMAC1_RXD1_M1
-- | -- | -- | -- | UART10_TX_M1 | -- | -- | SAI2_SDO_M0 | FSPI1_D4_M1 | -- | ETH1_RXD1_M1 | GPIO1_D0_d 1D22
-- | -- | -- | I3C0_SDA_PU_M1 | UART10_RX_M1 | -- | -- | SAI2_SCLK_M0 | FSPI1_D5_M1 | -- | ETH1_RXCTL_M1 | GPIO1_D1_d GMAC1_RXDV_CRS_M1
1A24 GPIO2_D4_d GMAC1_MDC_M1
PWM1_CH3_M1 | -- | -- | I3C0_SCL_M1 | -- | -- | -- | SAI2_LRCK_M0 | FSPI1_D6_M1 | -- | ETH1_MDC_M1 | GPIO1_D2_d C28 GPIO2_D5_d
PWM1_CH4_M1 | -- | -- | I3C0_SDA_M1 | -- | -- | -- | SAI2_SDI_M0 | FSPI1_D7_M1 | -- | ETH1_MDIO_M1 | GPIO1_D3_d GMAC1_MDIO_M1
1E21 MIPI_DPHY_CSI3_PDN_H
-- | -- | -- | I2C5_SCL_M1 | UART10_RTSN_M1 | SPDIF_RX1_M2 | PDM0_SDI3_M2 | SAI2_MCLK_M0 | FSPI1_DQS_M1 | -- | ETH1_MCLK_M1 | GPIO1_D4_d 1E22 R1803 0R R0201
CLK1_32K_OUT | SATA_MPSWIT | SPI2_CLK_M1 | I2C5_SDA_M1 | UART10_CTSN_M1 | SPDIF_TX1_M2 | PDM0_CLK1_M2 | -- | FSPI1_CLK_M1 | -- | ETH_CLK1_25M_OUT_M1 | GPIO1_D5_d ETH_CLK1_25M_OUT_M1

2B10 VCCIO_1V8_S0
VCCIO3_VCC C1801
100nF

2 1
B RK3576 X5R B
BGA698_16R1x17R2x1R18 6.3V
C0201

RK3576_J(VCCIO6)
U1000J
VCCIO6 Domain
Operating Voltage=1.8V/3.3V
AK3 HDMI_TX_CEC_M0
PWM1_CH5_M1 | UART11_TX_M2 | SPI4_CSN1_M0 | I2C7_SCL_M3 | PCIE1_WAKEN_M3 | HDMI_TX_CEC_M0 | -- | SAI4_MCLK_M2 | DSM_AUD_LP_M1 | GPIO4_C0_d AK2
PWM0_CH1_M1 | UART11_RX_M2 | EDP_TX_HPDIN_M0 | I2C7_SDA_M3 | PCIE1_CLKREQN_M3 | HDMI_TX_HPDIN_M0 | -- | -- | DSM_AUD_LN_M1 | GPIO4_C1_d HDMI_TX_HPDIN_M0
AL2 HDMI_TX_SCL
PWM2_CH0_M1 | UART9_TX_M2 | CAN0_TX_M1 | I2C2_SCL_M3 | -- | HDMI_TX_SCL | -- | -- | DSM_AUD_RP_M1 | GPIO4_C2_d 1AE2
PWM2_CH1_M1 | UART9_RX_M2 | CAN0_RX_M1 | I2C2_SDA_M3 | -- | HDMI_TX_SDA | -- | -- | DSM_AUD_RN_M1 | GPIO4_C3_d HDMI_TX_SDA
AL3 HDMI_TX_ON_H
PWM2_CH6_M1 | UART6_TX_M3 | SPI4_CSN0_M0 | I2C3_SCL_M3 | DP_HPDIN_M0 | -- | -- | SAI4_LRCK_M2 | ISP_PRELIGHT_TRIG_M1 | GPIO4_C4_d AK1
PWM2_CH5_M1 | UART6_RX_M3 | SPI4_MOSI_M0 | I2C3_SDA_M3 | SATA1_ACTLED_M1 | PCIE0_WAKEN_M3 | VP0_SYNC_OUT | SAI4_SDO_M2 | ISP_FLASH_TRIGOUT_M1 | GPIO4_C5_d LCD_RESET_L
1AE1 PCIE0_CLKREQn
PWM2_CH2_M1 | CAN1_TX_M1 | SPI4_MISO_M0 | I2C6_SCL_M3 | SATA0_ACTLED_M1 | PCIE0_CLKREQN_M3 | VP1_SYNC_OUT | SAI4_SDI_M2 | -- | GPIO4_C6_d AJ1
PWM2_CH3_M1 | CAN1_RX_M1 | SPI4_CLK_M0 | I2C6_SDA_M3 | -- | -- | VP2_SYNC_OUT | SAI4_SCLK_M2 | -- | GPIO4_C7_d PCIE0_PERSTn

2N3 VCC_3V3_S0
VCCIO6_VCC C1802
A A
100nF
2 1

RK3576 X5R
BGA698_16R1x17R2x1R18 6.3V
C0201

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 18.RK3576-GPIO VCCIO2/3/6
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 19 of 50

5 4 3 2 1
 5 4 3 2 1

RK3576_H(VCCIO4)
U1000H
VCCIO4 Domain
Operating Voltage=1.8V/3.3V
B22 SDMMC1_D0
-- | -- | I2C4_SCL_M2 | SPI4_CSN1_M3 | UART8_TX_M1 | -- | SAI0_SDO0_M0 | ETH0_RXD0_M1 | SDMMC1_D0_M1 | VI_CIF_D15 | GPIO2_A6_d B20
-- | -- | I2C4_SDA_M2 | -- | UART8_RX_M1 | -- | SAI0_SDO1_M0 | ETH0_TXCTL_M1 | SDMMC1_D1_M1 | VI_CIF_D14 | GPIO2_A7_d SDMMC1_D1
B19 SDMMC1_D2
-- | -- | -- | -- | UART1_TX_M1 | PDM0_SDI3_M3 | SAI0_SDI0_M0 | ETH0_TXD1_M1 | SDMMC1_D2_M1 | VI_CIF_D13 | GPIO2_B0_d 1A18
-- | -- | -- | -- | UART1_RX_M1 | PDM0_SDI2_M3 | SAI0_SDI1_M0 | ETH0_TXD0_M1 | SDMMC1_D3_M1 | VI_CIF_D12 | GPIO2_B1_d SDMMC1_D3
1A17 SDMMC1_CMD
-- | -- | PCIE0_CLKREQN_M0 | SPI4_CSN0_M3 | UART1_CTSN_M1 | PDM0_SDI1_M3 | SAI0_SDI2_M0 | ETH0_TXD3_M1 | SDMMC1_CMD_M1 | VI_CIF_D11 | GPIO2_B2_d 1B16
D -- | -- | PCIE1_CLKREQN_M0 | SPI4_CLK_M3 | UART1_RTSN_M1 | PDM0_CLK1_M3 | SAI0_SDO2_M0 | ETH0_TXCLK_M1 | SDMMC1_CLK_M1 | VI_CIF_D10 | GPIO2_B3_d SDMMC1_CLK D
A19 UART7_CTSN_M0
-- | SATA0_ACTLED_M0 | -- | SPI4_MOSI_M3 | UART7_CTSN_M0 | PDM0_SDI0_M3 | SAI0_SDI3_M0 | ETH0_TXD2_M1 | SDMMC1_PWREN_M1 | VI_CIF_D9 | GPIO2_B4_d 1C18
-- | SATA1_ACTLED_M0 | -- | SPI4_MISO_M3 | UART7_RTSN_M0 | PDM0_CLK0_M3 | SAI0_MCLK_M0 | ETH0_RXCLK_M1 | SDMMC1_DETN_M1 | VI_CIF_D8 | GPIO2_B5_d UART7_RTSN_M0
-- | -- | I2C8_SCL_M2 | UART8_RTSN_M1 | UART7_TX_M0 | -- | SAI0_SCLK_M0 | ETH0_RXD3_M1 | ETH1_PTP_REFCLK_M1 | VI_CIF_D7 | GPIO2_B6_d
A21 UART7_TX_M0 For BT
B21 UART7_RX_M0
-- | -- | I2C8_SDA_M2 | UART8_CTSN_M1 | UART7_RX_M0 | -- | SAI0_LRCK_M0 | ETH0_RXD2_M1 | -- | VI_CIF_D6 | GPIO2_B7_d
A17 WIFI_REG_ON_H
PWM1_CH0_M2 | -- | -- | -- | UART9_RX_M0 | PDM1_SDI1_M0 | -- | ETH0_PTP_REFCLK_M1 | ETH1_RXD2_M0 | VI_CIF_D5 | GPIO2_C0_d 1A15
PWM1_CH1_M2 | -- | -- | SPI1_CSN1_M1 | UART9_TX_M0 | PDM1_CLK1_M0 | SAI2_MCLK_M1 | ETH0_PPSCLK_M1 | ETH1_RXD3_M0 | VI_CIF_D4 | GPIO2_C1_d BT_REG_ON_H
1D15 SAI2_SCLK_M1
PWM1_CH2_M2 | -- | -- | SPI1_MOSI_M1 | UART11_CTSN_M1 | PDM1_SDI2_M0 | SAI2_SCLK_M1 | ETH0_PPSTRIG_M1 | ETH1_RXCLK_M0 | VI_CIF_D3 | GPIO2_C2_d A15
PWM0_CH0_M2 | -- | -- | SPI1_MISO_M1 | UART11_RTSN_M1 | PDM1_SDI3_M0 | SAI2_LRCK_M1 | -- | ETH1_TXD2_M0 | VI_CIF_D2 | GPIO2_C3_d SAI2_LRCK_M1 VCC_1V8_S3
PWM1_CH3_M2 | -- | -- | SPI1_CSN0_M1 | UART11_TX_M1 | PDM1_SDI0_M0 | SAI2_SDO_M1 | -- | ETH1_TXD3_M0 | VI_CIF_D1 | GPIO2_C4_d
1A13 SAI2_SDO_M1 For BT
1C15 SAI2_SDI_M1
PWM1_CH4_M2 | -- | -- | SPI1_CLK_M1 | UART11_RX_M1 | PDM1_CLK0_M0 | SAI2_SDI_M1 | -- | ETH1_TXCLK_M0 | VI_CIF_D0 | GPIO2_C5_d 1A14
PWM1_CH5_M2 | -- | I2C5_SCL_M2 | -- | UART4_CTSN_M0 | -- | SAI4_SCLK_M3 | -- | ETH1_TXD0_M0 | -- | GPIO2_C6_d HOST_WAKE_BT_H
B15 PCIE30_PWREN_H
PWM0_CH1_M2 | -- | I2C5_SDA_M2 | -- | UART4_RTSN_M0 | -- | SAI4_LRCK_M3 | -- | ETH1_TXD1_M0 | -- | GPIO2_C7_d R1926 R1927
B16 MIPI_DPHY_CSI0_PDN_H 2.2K 2.2K
PWM2_CH0_M2 | -- | I2C6_SCL_M2 | -- | UART4_TX_M0 | -- | SAI4_SDI_M3 | -- | ETH1_TXCTL_M0 | -- | GPIO2_D0_d 1A16 R0201 R0201
PWM2_CH1_M2 | -- | I2C6_SDA_M2 | -- | UART4_RX_M0 | -- | SAI4_SDO_M3 | -- | ETH1_RXD0_M0 | -- | GPIO2_D1_d PD_Status_1V8
B17 CAM_CLK0_OUT_M1
PWM2_CH2_M2 | I3C1_SCL_M0 | -- | -- | UART6_TX_M1 | -- | SAI4_MCLK_M3 | -- | ETH1_RXD1_M0 | CAM_CLK0_OUT_M1 | GPIO2_D2_d B18 I2C9_SCL_M2_MIPI_CSI0
PWM2_CH3_M2 | I3C1_SDA_M0 | -- | -- | UART6_RX_M1 | -- | -- | -- | ETH1_RXCTL_M0 | -- | GPIO2_D3_d MIPI_DPHY_CSI_PWREN_H
1B13 I2C9_SDA_M2_MIPI_CSI0 I2C9_SDA_M2_MIPI_CSI0
PWM2_CH4_M2 | -- | I2C9_SDA_M2 | -- | UART6_RTSN_M1 | -- | -- | -- | ETH1_MDC_M0 | ISP_PRELIGHT_TRIG_M0 | GPIO2_D4_d 1B15
PWM2_CH5_M2 | -- | I2C9_SCL_M2 | -- | UART6_CTSN_M1 | -- | -- | -- | ETH1_MDIO_M0 | ISP_FLASH_TRIGOUT_M0 | GPIO2_D5_d I2C9_SCL_M2_MIPI_CSI0
1D18 MIPI_DPHY_CSI3_PWREN_H
PWM2_CH6_M2 | I3C1_SDA_PU_M0 | -- | -- | UART9_RTSN_M0 | SPDIF_RX0_M2 | SAI3_MCLK_M2 | ETH0_MCLK_M1 | ETH_CLK1_25M_OUT_M0 | CAM_CLK1_OUT_M1 | GPIO2_D6_d 1E15
PWM2_CH7_M2 | -- | -- | SPI3_CSN1_M0 | UART9_CTSN_M0 | SPDIF_TX0_M2 | SAI0_SDO3_M0 | ETH_CLK0_25M_OUT_M1 | ETH1_MCLK_M0 | CAM_CLK2_OUT_M1 | GPIO2_D7_d CAM_CLK2_OUT_M1
1D16
-- | -- | I2C7_SCL_M1 | SPI3_CLK_M0 | UART3_TX_M0 | -- | SAI3_SCLK_M2 | ETH0_MDIO_M1 | -- | VI_CIF_HREF | GPIO3_A0_d 1B18
-- | -- | I2C7_SDA_M1 | SPI3_MOSI_M0 | UART3_RX_M0 | -- | SAI3_LRCK_M2 | ETH0_MDC_M1 | ETH1_PPSTRIG_M0 | VI_CIF_VSYNC | GPIO3_A1_d 1A20
-- | MIPI_TE_M1 | CAN1_TX_M3 | SPI3_MISO_M0 | UART3_CTSN_M0 | SPDIF_RX1_M1 | SAI3_SDO_M2 | ETH0_RXCTL_M1 | ETH1_PPSCLK_M0 | VI_CIF_CLKO | GPIO3_A2_d 1A19
-- | -- | CAN1_RX_M3 | SPI3_CSN0_M0 | UART3_RTSN_M0 | SPDIF_TX1_M1 | SAI3_SDI_M2 | ETH0_RXD1_M1 | ETH1_PTP_REFCLK_M0 | VI_CIF_CLKI | GPIO3_A3_d
C C

2A7 VCC_1V8_S3
VCCIO4_VCC C1901
1uF

2 1
RK3576 X5R
BGA698_16R1x17R2x1R18 6.3V
C0201

Note:
RK3576_I(VCCIO5)
U1000I
Caps of between dashed red lines and U1000
should be placed under the U1000 package.
Other caps should be placed close to the
VCCIO5 Domain
Operating Voltage=1.8V/3.3V U1000 package
1D13 ETH_CLK0_25M_OUT_M0
PWM1_CH0_M3 | -- | SPI2_CLK_M2 | UART1_CTSN_M2 | FLEXBUS0_CSN_M0 | -- | FLEXBUS1_D11 | DSMC_RDYN | SAI4_SDI_M1 | ETH_CLK0_25M_OUT_M0 | VO_EBC_SDSHR | VO_LCDC_D23 | GPIO3_A4_d A9 GPIO3_A5_d
PWM1_CH1_M3 | -- | SPI2_CSN1_M2 | UART1_RTSN_M2 | -- | -- | FLEXBUS0_D7 | DSMC_DATA15 | PDM1_SDI3_M2 | ETH0_MDIO_M0 | VO_EBC_GDSP | VO_LCDC_D22 | GPIO3_A5_d GMAC0_MDIO_M0
1A7 GPIO3_A6_d GMAC0_MDC_M0
PWM1_CH2_M3 | -- | UART10_CTSN_M0 | UART1_RX_M2 | -- | -- | FLEXBUS0_D6 | DSMC_DATA14 | PDM1_SDI2_M2 | ETH0_MDC_M0 | VO_EBC_GDOE | VO_LCDC_D21 | GPIO3_A6_d B13
-- | -- | UART10_RTSN_M0 | UART1_TX_M2 | -- | -- | FLEXBUS0_D5 | DSMC_DATA13 | PDM1_CLK1_M2 | ETH0_RXCTL_M0 | VO_EBC_VCOM | VO_LCDC_D20 | GPIO3_A7_d GMAC0_RXCTL_M0
B14 GMAC1_RSTn_3V3
PWM0_CH0_M3 | -- | SPI2_MOSI_M2 | UART10_RX_M0 | -- | -- | FLEXBUS0_D8 | DSMC_CSN1 | SAI4_MCLK_M1 | ETH0_MCLK_M0 | VO_EBC_SDCE3 | VO_LCDC_D19 | GPIO3_B0_d 1A11
PWM1_CH3_M3 | -- | SPI4_CSN0_M1 | UART10_TX_M0 | -- | -- | FLEXBUS0_D4 | DSMC_DATA12 | PDM1_CLK0_M2 | ETH0_RXD1_M0 | VO_EBC_SDCE2 | VO_LCDC_D18 | GPIO3_B1_d GMAC0_RXD1_M0
A13 GMAC0_RXD0_M0
-- | I2C8_SDA_M3 | -- | UART9_RX_M1 | -- | -- | FLEXBUS0_D3 | DSMC_DATA11 | PDM1_SDI1_M2 | ETH0_RXD0_M0 | VO_EBC_SDCE1 | VO_LCDC_D17 | GPIO3_B2_d A11 GPIO3_B3_d
-- | I2C8_SCL_M3 | -- | UART9_TX_M1 | -- | -- | FLEXBUS0_D2 | DSMC_DATA10 | PDM1_SDI0_M2 | ETH0_TXCTL_M0 | VO_EBC_SDCE0 | VO_LCDC_D16 | GPIO3_B3_d GMAC0_TXCTL_M0
B10 GPIO3_B4_d GMAC0_TXD1_M0
B PWM1_CH4_M3 | -- | -- | UART9_RTSN_M1 | -- | -- | FLEXBUS0_D1 | DSMC_DATA9 | SPDIF_RX1_M0 | ETH0_TXD1_M0 | VO_EBC_SDDO15 | VO_LCDC_D15 | GPIO3_B4_d 1A9 GPIO3_B5_d B
PWM1_CH5_M3 | -- | -- | UART9_CTSN_M1 | -- | -- | FLEXBUS0_D0 | DSMC_DATA8 | SPDIF_TX1_M0 | ETH0_TXD0_M0 | VO_EBC_SDDO14 | VO_LCDC_D14 | GPIO3_B5_d GMAC0_TXD0_M0
B11 GPIO3_B6_d GMAC0_TXCLK_M0
PWM0_CH1_M3 | -- | SPI3_CSN0_M1 | -- | -- | -- | FLEXBUS0_CLK | DSMC_DQS1 | -- | ETH0_TXCLK_M0 | VO_EBC_SDDO13 | VO_LCDC_D13 | GPIO3_B6_d 1D12
-- | I2C4_SDA_M3 | UART3_CTSN_M1 | UART2_RX_M2 | FLEXBUS1_CSN_M0 | -- | FLEXBUS1_D10 | DSMC_DQS0 | SAI1_SDI0_M1 | ETH0_PPSTRIG_M0 | VO_EBC_SDDO12 | VO_LCDC_D12 | GPIO3_B7_d GMAC0_RSTn_3V3
1E9 IO_LED
-- | I2C4_SCL_M3 | UART3_RTSN_M1 | UART2_TX_M2 | -- | -- | FLEXBUS1_D9 | DSMC_DATA7 | SAI1_SDO3_M1 | ETH0_PPSCLK_M0 | VO_EBC_SDDO11 | VO_LCDC_D11 | GPIO3_C0_d 1B10
CAN0_RX_M3 | I2C5_SDA_M3 | SPI2_MISO_M2 | UART11_RX_M0 | -- | -- | FLEXBUS1_D8 | DSMC_DATA6 | SAI1_SDO2_M1 | ETH0_PTP_REFCLK_M0 | VO_EBC_SDDO10 | VO_LCDC_D10 | GPIO3_C1_d B9 GPIO3_C2_d R1906
PWM2_CH0_M3 | I2C9_SCL_M3 | SPI4_MISO_M1 | UART11_RTSN_M0 | -- | -- | FLEXBUS0_D9 | DSMC_INT1 | SAI2_SCLK_M2 | ETH0_TXD3_M0 | VO_EBC_SDDO9 | VO_LCDC_D9 | GPIO3_C2_d GMAC0_TXD3_M0
1A8 GPIO3_C3_d GMAC0_TXD2_M0 510R
PWM2_CH1_M3 | I2C9_SDA_M3 | SPI4_MOSI_M1 | UART11_CTSN_M0 | FLEXBUS0_CSN_M2 | -- | FLEXBUS0_D10 | DSMC_INT3 | SAI2_LRCK_M2 | ETH0_TXD2_M0 | VO_EBC_SDDO8 | VO_LCDC_D8 | GPIO3_C3_d 1D9 R0201
CAN0_TX_M3 | I2C5_SCL_M3 | SPI2_CSN0_M2 | UART11_TX_M0 | -- | -- | FLEXBUS1_D7 | DSMC_DATA5 | SAI1_SDO1_M1 | -- | VO_EBC_SDDO7 | VO_LCDC_D7 | GPIO3_C4_d GPIO3_C4
1B9 GPIO3_C5/UART8_RX_M0
PWM2_CH2_M3 | -- | SPI1_MISO_M2 | UART8_RX_M0 | -- | -- | FLEXBUS1_D6 | DSMC_DATA4 | SAI1_SDO0_M1 | -- | VO_EBC_SDDO6 | VO_LCDC_D6 | GPIO3_C5_d
-- | -- | SPI1_MOSI_M2 | UART8_TX_M0 | -- | -- | FLEXBUS1_D5 | DSMC_DATA3 | SAI1_LRCK_M1 | -- | VO_EBC_SDDO5 | VO_LCDC_D5 | GPIO3_C6_d
1D7 GPIO3_C6/UART8_TX_M0 考虑更换侧面LED型号
1C7 GPIO3_C7 LED1900
-- | -- | SPI1_CLK_M2 | UART8_RTSN_M0 | -- | -- | FLEXBUS1_D4 | DSMC_DATA2 | SAI1_SCLK_M1 | -- | VO_EBC_SDDO4 | VO_LCDC_D4 | GPIO3_C7_d LED_GREEN
1C12 GPIO3_D0 LED0603
PWM2_CH3_M3 | -- | SPI1_CSN0_M2 | UART8_CTSN_M0 | -- | -- | FLEXBUS1_D3 | DSMC_DATA1 | SAI1_MCLK_M1 | -- | VO_EBC_SDDO3 | VO_LCDC_D3 | GPIO3_D0_d 1A12 POWER_LED
-- | I3C1_SDA_PU_M2 | SPI4_CLK_M1 | -- | FLEXBUS1_CSN_M2 | -- | FLEXBUS0_D11 | DSMC_CSN2 | SAI2_MCLK_M2 | ETH0_RXCLK_M0 | VO_EBC_SDDO2 | VO_LCDC_D2 | GPIO3_D1_d GMAC0_RXCLK_M0 VCC_3V3_S0
1A10 GMAC0_RXD3_M0
PWM2_CH4_M3 | I3C1_SDA_M2 | SPI4_CSN1_M1 | UART2_RTSN_M2 | FLEXBUS0_CSN_M3 | FLEXBUS1_D15_M0 | FLEXBUS0_D12 | DSMC_CSN3 | SAI2_SDI_M2 | ETH0_RXD3_M0 | VO_EBC_SDDO1 | VO_LCDC_D1 | GPIO3_D2_d B12
PWM2_CH5_M3 | I3C1_SCL_M2 | -- | UART2_CTSN_M2 | -- | -- | FLEXBUS1_D2 | DSMC_CSN0 | SAI2_SDO_M2 | ETH0_RXD2_M0 | VO_EBC_SDDO0 | VO_LCDC_D0 | GPIO3_D3_d GMAC0_RXD2_M0
1E12 GPIO3_D4
-- | I2C3_SCL_M2 | SPI3_CLK_M1 | UART5_RX_M0 | -- | -- | FLEXBUS1_D1 | DSMC_DATA0 | SAI1_SDI1_M1 | -- | VO_EBC_SDLE | VO_LCDC_DEN | GPIO3_D4_d 1D10
-- | I2C3_SDA_M2 | SPI3_MISO_M1 | UART5_TX_M0 | -- | -- | FLEXBUS1_D0 | DSMC_CLKP | SAI1_SDI2_M1 | -- | VO_EBC_GDCLK | VO_LCDC_HSYNC | GPIO3_D5_d GPIO3_D5
1C10 GPIO3_D6 R1902 R1903
PWM2_CH6_M3 | -- | SPI3_MOSI_M1 | UART5_CTSN_M0 | -- | -- | FLEXBUS1_CLK | DSMC_CLKN | SAI1_SDI3_M1 | -- | VO_EBC_SDCLK | VO_LCDC_VSYNC | GPIO3_D6_d 1E7 2.2K 2.2K
PWM2_CH7_M3 | -- | SPI3_CSN1_M1 | UART5_RTSN_M0 | FLEXBUS1_CSN_M1 | FLEXBUS1_D12_M0 | FLEXBUS0_D15_M0 | DSMC_RESETN | SAI4_SCLK_M1 | CAM_CLK0_OUT_M0 | VO_EBC_SDOE | VO_LCDC_CLK | GPIO3_D7_d GPIO3_D7
R0201 R0201
1B12 I2C7_SCL_M2_CC_RTC I2C7_SCL_M2_CC_RTC
MIPI_TE_M2 | I2C7_SCL_M2 | SPI1_CSN1_M2 | UART3_TX_M1 | FLEXBUS1_CSN_M3 | FLEXBUS1_D14_M0 | FLEXBUS0_D13_M0 | DSMC_INT0 | SAI4_LRCK_M1 | CAM_CLK1_OUT_M0 | SPDIF_RX0_M1 | -- | GPIO4_A0_d 1B7 I2C7_SDA_M2_CC_RTC
-- | I2C7_SDA_M2 | -- | UART3_RX_M1 | FLEXBUS0_CSN_M1 | FLEXBUS1_D13_M0 | FLEXBUS0_D14_M0 | DSMC_INT2 | SAI4_SDO_M1 | CAM_CLK2_OUT_M0 | SPDIF_TX0_M1 | VO_POST_EMPTY | GPIO4_A1_d I2C7_SDA_M2_CC_RTC

2A4
VCCIO5_VCC_0 2A5
VCCIO5_VCC_1 VCC_3V3_S0
C1903
A A
1uF

2 1
RK3576 X5R
BGA698_16R1x17R2x1R18 6.3V
C0201

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 19.RK3576-GPIO VCCIO4/5
Date: Friday, July 12, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 20 of 50

5 4 3 2 1
 5 4 3 2 1

Power_IN
VBUS_TypeC_Power
PD_Status_1V8 VCCIO_1V8_S0
J2000 VBUS_TypeC_Power
USC4_16FX_NAM1_21 C2000 C2001 C2003

1
D A4 22uF 22uF 100nF C2021 R2014 D

2 1
VBUS_1 B9 X5R X5R X5R VBUS_TypeC_Power VDD_CK224K 1uF U2001 2.2K

2 1
VBUS_2 B4 25V 25V 25V X5R CH224K R0201 R2015
VBUS_3 A9

2
C0805 C0805 C0201 25V 11 10K
VBUS_4 R2009 1K C0402 1 GND0 10 PD_Status_1V8 R0201
Type C-16Pin
B8 R0402 CFG2 2 VDD PG 9 CFG1
SUB2 A5 TypeC0_CC1R2001 CFG3 3 CFG2 CFG1 8
CC1 B7 NC/5.1K IN_DP 4 CFG3 VBUS 7 TypeC0_CC1
DN2 A6 R0201 IN_DP IN_DM 5 DP CC1 6 TypeC0_CC2
DP1 A7 IN_DM DM CC2
DN1 B6
DP2 A8 VDD_CK224K VDD_CK224K
SUB1
CC2
B5 TypeC0_CC2R2000 CFG1:1/0
NC/5.1K CFG1 R2006 NC/0R R0201 CFG3 R2008 0R R0201
A1 R0201 CFG2: X/0
GND_1 B12 R2013 0R R0201 CFG3: X/1
GND_2
GND_3
B1 Out: 5V/12V
A12 CFG2
GND_4
G1
G1 Default 12V
G2
G2 G3
C C
G3 G4
G4

VCC5V0_SYS 1 2
R2021
VBUS_TypeC_Power 3.3R
R0402 C2006

1
4.5V<VIN<18V U2000 5% 220nF
>4V---> ON NB679GD X5R

8
QFN12_2R00X3R00X1R00 25V

2
VCC5V0_SYS_S5
C2002 C2004 C2005 C0201 Default 5V 8A
BST
1

B 22uF 22uF 100nF B

2 1

X5R X5R X5R R2018 1 7

25V 25V 25V 100K VIN SW
2

C0805 C0805 C0201 R0201 L2000 C2013 C2014 C2011 C2016

8A SPM5020T-2R2M 22uF 22uF 100nF 22uF

2 1

2 1

2 1

2 1
IND_505020 C0603 C0603 X5R C0603
X5R X5R 10V X5R
R2016 VENH=1.05V 10V 10V C0201 10V
120K 11 5
1% C2009 EN VOUT
R0201 R2019 100nF 12 C2008
2 1

1 2
51K X5R EN_LDO 100nF
SARADC_IN4_VOLDet R0201 25V C0201
C0201 6 2 X5R
C2020 LDO PGND 10 25V
R2017 100nF 4 AGND
2 1

11K X5R NC
1% 10V
VCC
PG

R0201 C0201
3

A TypeC 5V EN=1.67V, Enter USM Mode A

TypeC 12V EN=4V, Enter Normal Mode Rockchip Electronics Co., Ltd
TypeC=5V,ADC_IN4=0.42V 1 2 C2010 1 2
R2020 1uF 6.3V Project: TB-RK3576D0
TypeC=12V,ADC_IN4=1.008V 100K X5R C0201
TypeC=20V,ADC_IN4=1.679V R0201 File: 20.Power_IN
5%
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 21 of 50

5 4 3 2 1
 5 4 3 2 1

I2C1_SDA_M0_RK806
I2C1_SCL_M0_RK806 PMIC RK806S-5 BUCK VDD_GPU_S0
VCC5V0_SYS_S5
U2300A

VCC5V0_SYS_S5
VDD_CPU_BIG_S0
OUT
VDD

PMIC_PWR_CTRL1 C2300 22uF 2 1 X5R 10V C0603 44 52 C2301 22uF 1 2 X5R 10V C0603
VCC5 VCC1_1 53
PMIC_PWR_CTRL2 VCC1_2

100R
PMIC1_SW5 PMIC1_SW1
45
SW5 SW1_1
50 RK3576
C2304 C2305 R2302 R2303 C2306 L2300 0.47uH
BUCK5 BUCK1 SW1_2
51 L2301 0.24uH C2307 C2308 C2309 FB
PMIC_INT_L 22uF 22uF 49.9K 100R 1uF 4.4A 33mohm 7.8A 0.019ohm C2311 22uF 22uF 22uF

2 1

2 1

2 1
3.0A 6.5A

2 1

2 1

2 1
X5R X5R 1% R0201 X5R IND_201610 46 IND_252012 1uF R2304 X5R X5R X5R DCDC

2 1
6.3V 6.3V R0201 10V VOUT5 49 X5R 100R 6.3V 6.3V 6.3V
RESET_L VOUT1
C0603 C0603 C0201 10V R0201 C0603 C0603 C0603
C0201
PMIC1_FB5 47
PMIC_EXT_EN_OUT FB5 (FB=0.5V) VDD_CPU_BIG_S0

PWRON_L R2305 VDD_GPU_S0

100K Feedback from RK3576
R0201 48
D
1% Feedback from RK3576 (FB=0.5V)FB1 D

Def:Slot2 Def:Slot2@0.75V

VCC5V0_SYS_S5 VCC5V0_SYS_S5
VDDQ_DDR_S0 VDD_NPU_S0
C2312 22uF 2 1 X5R 10V C0603 28 33 C2313 22uF 1 2 X5R 10V C0603
VCC6 VCC2_1 34
VCC2_2
PMIC_SW6 29 35 PMIC1_SW2
C2315 C2316 C2317 L2302 0.47uH SW6 SW2_1 36 L2303 0.24uH C2318 C2319 C2320
SW2_2
22uF 22uF R2308 100pF 4.4A 33mohm
BUCK6 BUCK2 7.8A 0.019ohm C2323 22uF 22uF 22uF

2 1

2 1

2 1

2 1

2 1

2 1
X5R X5R 22K
Ru C0G IND_201610 30 IND_252012 1uF R2309 X5R X5R X5R

2 1
6.3V 6.3V 1% 25V VOUT6
3.0A 5A VOUT2
37 X5R 100R 6.3V 6.3V 6.3V
C0603 C0603 R0201 C0201 10V R0201 C0603 C0603 C0603
C0201
Default:0.61V PMIC_FB6 31
FB6 (FB=0.5V) VDD_NPU_S0

R2310 Feedback from RK3576

100K 38
DDR Type Voltage Ru R0201 (FB=0.5V) FB2
LPDDR4/4X 0.61V 22K 1% 1% Def:Slot7 Def:Slot2@0.75V
LPDDR5 0.51V 2K 1%
VCC5V0_SYS_S5 VCC5V0_SYS_S5

VDD2_DDR_S3 C2324 10uF 2 1 X5R 10V C0402 1 54 C2325 22uF 1 2 X5R 10V C0603 VDD_CPU_LIT_S0
VCC9 VCC3

PMIC1_SW9 68
C2327 C2328 L2304 0.47uH SW9 55 PMIC1_SW3
SW3
22uF 22uF R2313 C2329 4.4A 33mohm
BUCK9 BUCK3 L2305 0.24uH C2330 C2331 C2332

2 1

2 1
X5R X5R 120K 100pF IND_201610 67 7.8A 0.019ohm C2334 22uF 22uF 22uF

2 1

2 1

2 1

2 1
6.3V 6.3V
Ru
R0201 C0G VOUT9
3.0A 5A IND_252012 1uF R2314 X5R X5R X5R

2 1
Default:1.1V C0603 C0603 1% 25V X5R 100R 6.3V 6.3V 6.3V
C0201 10V R0201 C0603 C0603 C0603
PMIC_FB9 66 C0201
FB9 (FB=0.5V) 56
VOUT3 VDD_CPU_LIT_S0
R2315
DDR Type Voltage Ru 100K
LPDDR4/4X 1.1V 120K 1% R0201 Feedback from RK3576
C LPDDR5 1.05V 110K 1% 1% C
Def:Slot4 Def:Slot2@0.75V

VCC5V0_SYS_S5 VCC5V0_SYS_S5

C2335 10uF 2 1 X5R 10V C0402 7 22 C2336 22uF 1 2 X5R 10V C0603
VCC8 VCC4
VCC_1V8_S3 VCC_3V3_S3

Default:1.8V PMIC1_SW8 PMIC1_SW4

C2337 C2338 L2306 0.47uH
6
SW8 BUCK8 BUCK4 SW4
23
L2307 0.24uH C2339 C2340
22uF 22uF 4.4A 33mohm 3.0A 5A 7.8A 0.019ohm 22uF 22uF

2 1

2 1

2 1

2 1
X5R X5R IND_201610 IND_252012 X5R X5R
6.3V 6.3V 5 24 6.3V 6.3V
C0603 C0603 VOUT8 VOUT4 C0603 C0603

Def:Slot3@1.8V Def:Slot5@3.3V

VCC5V0_SYS_S5 VCC5V0_SYS_S5

VCC5V0_SYS_S5 IF TVS UNMOUNTED, VDD_DDR_S0

COM PIN28 27
VCC10 VCC7
43 COM PIN44 VDD_LOGIC_S0

ESD OR SURGE SHOULD BE

DAMAGE THE PMIC!!! BUCK10 BUCK7
1

PMIC1_SW10 26 42 PMIC1_SW7
D2300 This device must be mounted.Replacing TVS mode is not
recommended, if must, please choose the same specifications
Default:0.85V C2344 C2345 C2346 L2308 0.47uH SW10
3.0A 3.0A SW7 L2309 0.47uH C2347 C2348 C2349 C2350
PSUR1610DNV07 22uF 22uF 22uF C2351 4.4A 33mohm 4.4A 33mohm C2352 22uF 22uF 22uF 22uF
Low frequency:
2 1

2 1

2 1

2 1

2 1

2 1

2 1
PSUR1610DNV07 Operating Supply Vltage ：5.5V(5.25-6V) X5R X5R X5R R2320 1uF IND_201610 IND_201610 1uF R2321 X5R X5R X5R X5R
0.85V-->0.75V

2 1

2 1
RSD8535MA PeakPulse Current：>10A（tp=8/20uS) 6.3V 6.3V 6.3V 100R X5R 25 41 X5R 100R 6.3V 6.3V 6.3V 6.3V
VOUT10 VOUT7
2

BTRD06B800A Surge Clamping Voltage：<6.5V C0603 C0603 C0603 R0201 10V 10V R0201 C0603 C0603 C0603 C0603
ESD0603 C0201 C0201
Def:Slot2@0.85V Def:Slot2@0.75V
DO NOT DELETE IT! VDD_DDR_S0
RK806S-5
VDD_LOGIC_S0
QFN68_7R00X7R00X0R80_T
Feedback from RK3576 Feedback from RK3576

B
Note: B

PMIC RK806S-5 Managerment I2C Mode:CS(pin18) connected to VCCA(pin21);

SPI Mode(Def):CS(pin18) floating or connected to GND
PMIC RK806S-5 LDO VCCA_1V8_S0

VCC_2V0_PLDO_S3 U2300B VCCA_1V8_S0_P

Default:1.8V
59 0.5A 60 C2353 2.2uF 1 2 X5R 6.3V C0402 VCC_1V8_S0
VCC5V0_SYS_S5 C2354 VCC11 Def:Slot3@1.8V PLDO1
1uF VCC_1V8_S0_P
2 1

Default:1.8V X5R Default:1.8V

U2300C R2324 6.3V 0.3A 58 C2355 2.2uF 1 2 X5R 6.3V C0402 VDDA_1V2_S0
VCCA1V8_PLDO6_S3 PLDO2
Def:Slot3@1.8V
VCCIO 0R
R0201
C0201 Def:Slot3@1.8V
VDDA_1V2_S0_P
20 18 I2C_MODE_SEL Default:1.2V
VCCIO (IIC/SPI)CS 0.3A 57 C2356 2.2uF 1 2 X5R 6.3V C0402 VCCA3V3_CODEC
I2C1_SDA_M0_RK806 PLDO3
C2357
(SDA)MOSI
15
VCC5V0_SYS_S5
Def:Slot4@1.2V
VCCA_3V3_S0_P
floating
1uF
2 1

X5R 17 I2C1_SCL_M0_RK806 Default:3.0V

6.3V PLDO6 (SCL)CLK 64 0.5A 63 C2358 2.2uF 1 2 X5R 6.3V C0402 VCCIO_SD_S0
300mA VCC12 PLDO4
C0201 16 C2359 Def:Slot5@3.0V
VCC5V0_SYS_S5 (PWRCTRL3)SO 1uF VCCIO_SD_S0_P
2 1

61 PMIC_PWR_CTRL2 X5R Default:3.3V

21 PWRCTRL2 10V 0.3A 65 C2360 2.2uF 1 2 X5R 6.3V C0402
VCCA 62 PMIC_PWR_CTRL1 C0201 Def:Slot5@3.3V PLDO5
PWRCTRL1 VDD_0V75_S3
C2361
4.7uF
C2362
1uF PLDO
2 1

2 1

X5R X5R VCC_1V1_NLDO_S3 VDD_0V75_S3_P

10V 10V VCCA Default:0.75V
C0402 C0201 3 39 PMIC_EXT_EN_OUT 13 0.3A 14 C2363 2.2uF 1 2 X5R 6.3V C0402 VDDA_DDR_PLL_S0
SYNC_CLK (M/S)EXT_EN C2364 VCC13 Def:Slot2@0.75V NLDO1
2 19 PMIC_INT_L 1uF VDDA_DDR_PLL_S0_P
2 1

SYNC INT X5R Default:0.85V;Low frequency:0.85V-->0.75V

R2330 200K PMIC_VDC 32 40 RESET_L 6.3V 0.3A 12 C2365 2.2uF 1 2 X5R 6.3V C0402 VDDA0V75_HDMI_S0
45K

R0201 VDC RESETB C0201 Def:Slot2@0.85V NLDO2

Def:Slot12
2

PWRON_L 4 69 VDDA0V75_HDMI_S0_P
PWRON ePAD
2

D2301 R2332 C2368 C2369 C2366 Default:0.75V

B5819WS 200K 1nF 100nF 10nF 0.5A 11 C2367 1uF 1 2 X5R 6.3V C0201 VDDA_0V85_S0
2 1

2 1

SOD_323 R0201 X5R X5R RK806S-5 X5R NLDO3

Def:Slot2@0.75V
1

25V 10V QFN68_7R00X7R00X0R80_T 25V VCC_1V1_NLDO_S3 VDDA_0V85_S0_P

1

C0201 C0201 C0201 Default:0.85V

A 9 0.5A 10 C2370 2.2uF 1 2 X5R 6.3V C0402 VDDA_0V75_S0 A
C2371 VCC14 Def:Slot2@0.85V NLDO4
1uF VDDA_0V75_S0_P
2 1

X5R Default:0.75V
RK3576 Note: 6.3V 0.3A 8 C2372 2.2uF 1 2 X5R 6.3V C0402
C0201 NLDO5
nPOR Def:Slot2@0.75V

Reset Key Control Path NLDO

Reset Key

TSADC_CTRL RK806S-5

Note:
QFN68_7R00X7R00X0R80_T
TSADC_SHUT Control Path
Rockchip Electronics Co., Ltd
RK806S-5 The RK806 LDO power distribution of the reference chematics is only suitable
RK806S-5 Control Path
for the interface used in the reference schematics. Project: TB-RK3576D0
RESETB If other interface functions are to be added to the reference schematics,
the RK806 LDO distribution needs to be re evaluated, otherwise the added File: 23.Power-PMIC RK806S-5
functions may exceed the maximum current provided by the LDO Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 22 of 50

5 4 3 2 1
 5 4 3 2 1

I2C7_SDA_M2_CC_RTC
VCC_2V0_PLDO_S3 VCC_1V1_NLDO_S3 VCC_1V1_NLDO_S3
I2C7_SCL_M2_CC_RTC VCC5V0_SYS_S5 VCC_2V0_PLDO_S3 VCC5V0_SYS_S5
RTC_INT_L U2400 2.094V U2401
4 3 4 3
C2400 VIN LX L2400 C2401 VIN LX L2401 C2402
32KOUT_RTC
10uF 2 1.0uH C2403 C2404 C2405 4.7uF 2 1.0uH 100pF R2403 C2406 C2407
GND GND

2 1

2 1

2 1
PWRON_L X5R 3.22A 100pF R2404 22uF 100nF X5R 3.22A C0G 100K 22uF 100nF

2 1

2 1

2 1

2 1

2 1
10V 1 5 0.065ohm C0G 249K X5R X5R 10V 1 5 0.065ohm 25V R0201 X5R X5R
C0402 C2408 EN FB/OUT IND_252010 25V R0201 6.3V 6.3V C0402 C2409 EN FB/OUT IND_252010 C0201 1% 6.3V 6.3V
R2405 NC/100nF TCS4203 FB=0.6V C0201 1% C0603 C0201 R2406 NC/100nF TCS4203 FB=0.6V C0603 C0201

2 1

2 1
D 100K X5R SOT_23_5 10K X5R SOT_23_5 R2407 D
PMIC_EXT_EN_OUT R0201 6.3V R2408 PMIC_EXT_EN_OUT R0201 6.3V 120K
C0201 100K C0201 R0201
PMIC_EXT_EN_OUT R0201 1%
1%

VCCIO_1V8_S0 VCC_3V3_S0
VCC_1V8_S0 VCCIO_1V8_S0 VCC_3V3_S3 VCC_3V3_S0
U2402
5 1
IN VOUT
VCCA_1V8_S0 2
GND
4 3
C2413 EN OCB C2414
10uF TCS9163 R2414 10uF

2 1

2 1
X5R SOT_23_5 4.7K X5R
6.3V Default:TCS9163 R0201 6.3V
C0402 Ilim=6800/RILIMA) C0402

C C

RTC

TCS8563在5V供电下，clkout上拉电源支持3v3/1V8，int和i2c只支持3V3
VCC_RTC VCC5V0_SYS_S5

D2200 2 1

3
C2421 1 2 12pF B5819WS
C0201 C0G 25V SOD_323 GND
1

Y2400 D2201 2 1VBatt_RTC 1 CON2400

32.768KHz U2404 B5819WS 2 1 CN2M_1R25_H_SMT
CRY2_3R20x1R50x0R90 1 8 SOD_323 2 CN2MR_1R25_H_SMT
OSCI VDD C2423 GND
2

PMUIO0_VCC1V8 C2422 1 2 NC/12pF 2 7 32KOUT_RTC 100nF

OSCO CLKOUT
2 1

4
C0201 C0G 25V X5R
RTC_INT 3 6 I2C7_SCL_M2_CC_RTC 10V
R2411 INT SCL C0201
10K 4 5 I2C7_SDA_M2_CC_RTC
R0201 VSS SDA
32KOUT_RTC TCS8563
TSSOP8_3R10X3R10X1R10
B B

WIFI/BT Power
RTC POWERON
VCC5V0_SYS_S5
PWRON_L
VCC_RTC

R2425
2M
3

Q2400 R0201 R2428

WNM2021-3/TR 51K
SOT_323 1 R0201
2

Q2401
WNM2021-3/TR
SOT_323 1 RTC_INT
2
3

Q2402
WNM2021-3/TR
SOT_323 1 R2426 10K R0201 VCC_3V3_S3
2

A A

D2400
1N4148WS
SOD_323
RTC_INT_L 1 2 RTC_INT
Rockchip Electronics Co., Ltd
R2427 NC/0R R0201
Project: TB-RK3576D0
File: 24.Power-Ext Discrete/RTC
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 23 of 50

5 4 3 2 1
 5 4 3 2 1

OTG0/USB3
USB2_OTG0_DP
USB2_OTG0_DM

2
USB3_OTG0_SSRX1P/DP_TX_D0P
USB3_OTG0_SSRX1N/DP_TX_D0N ED2500
USB3_OTG0_SSTX1P/DP_TX_D1P ESDH0402WV05U J2500
USB3_OTG0_SSTX1N/DP_TX_D1N R2510 0R R0201ED0402 USB30AX2_DIP
VCC5V0_USB_OTG0
USB2_OTG0_DP R2512 2.2R R0201 L2501 2 1 NC USB2_OTG0DP 1
VBUS0

1
USB2_OTG0_VBUSDET RP2_0405 USB2_OTG0DM 2
USB2_OTG0_DM R2513 2.2R R0201 4 3 USB2_OTG0DM USB2_OTG0DP 3 D0- 20
D0+ SHLD1

1
USB2_OTG0_PWREN_H USB3_OTG0SSRXN 5 21
R2516 0R R0201 ED2501 USB3_OTG0SSRXP 6 RX0- SHLD2 22
ED0402 USB3_OTG0SSTXN 8 RX0+ SHLD3 19
D TX0- SHLD4 D
ESDH0402WV05U USB3_OTG0SSTXP
USB2_HOST1_DP
USB2_HOST1_DM
Note: VCC5V0_USB30_HOST1
9
TX0+
If common mode inductors are needed, 10
VBUS1

2
it is recommended to keep 2.2ohm in series USB2_HOST1DM 11
USB3_HOST1_SSRXP to improve the antistatic ability D1-
USB3_HOST1_SSRXN USB2_HOST1DP 12 4
USB3_HOST1SSRXN 14 D1+ GND1 7
USB3_HOST1_SSTXP RX1- GND2
USB3_HOST1_SSTXN USB3_HOST1SSRXP 15 13
USB3_HOST1SSTXN 17 RX1+ GND3 16
USB3_HOST1SSTXP 18 TX1- GND4
TX1+

USB2_HOST_PWREN_H

2
Download firmware
ED2502
ESDH0402WV05U
ED0402
ED2503
ESDH0402WV05U
ED0402
双层USB3.0座子
Note:

1
VCC5V0_USB_OTG0 USB3_OTG0_SSTX1N/DP_TX_D1N C2508 100nF 1 2 X5R 10V C0201 USB3_OTG0SSTXN USB3信号的ESD不能随便换掉
USB2_OTG0_VBUSDET USB3_OTG0_SSTX1P/DP_TX_D1P C2509 100nF 1 2 X5R 10V C0201 USB3_OTG0SSTXP 如需换那么必须选择相同的规格。
R2514
R2517
20K
10K
R0201 USB3_OTG0_SSRX1N/DP_TX_D0N USB3_OTG0SSRXN
Cj<=0.4pF
R0201 5%
USB3_OTG0_SSRX1P/DP_TX_D0P USB3_OTG0SSRXP
C C

1
ED2504 ED2505
ED0402 ED0402
ESDH0402WV05U ESDH0402WV05U

2
USB POWER USB3_HOST1 USB2_OTG1_VBUSDET
VCC5V0_USB30_HOST1

USB2_OTG1_VBUSDET
R2515
R2518 10K
VCC5V0_SYS_S5 U2503 VCC5V0_USB30_HOST1 20K R0201

2
TCS9163 R0201 5%
C2522 2 1 1uF 5 1 ED2506 ED2507
X5R 10V C0201 IN VOUT C2521 C2520 C2523 ESDH0402WV05U ESDH0402WV05U
1

2 22uF 22uF 100nF ED0402 ED0402

GND
2 1

X5R X5R X5R

USB2_HOST_PWREN_H 4 3 10V 10V 10V
EN OCB
2

1
C0603 C0603 C0201
TCS9163 EN>1.2V SOT_23_5 R2501 USB3_HOST1_SSTXN C2506 100nF 1 2 X5R 10V C0201 USB3_HOST1SSTXN
B 3.6K B

Ilim(A)=6800/Rset R0201 USB3_HOST1_SSTXP C2507 100nF 1 2 X5R 10V C0201 USB3_HOST1SSTXP

USB3_HOST1_SSRXN USB3_HOST1SSRXN

USB3_HOST1_SSRXP USB3_HOST1SSRXP

VCC5V0_SYS_S5 U2501 VCC5V0_USB_OTG0

1

TCS9163 ED2508 ED2509

C2510 2 1 1uF 5 1 ED0402 ED0402
X5R 10V C0201 IN VOUT C2511 C2513 C2512 ESDH0402WV05U ESDH0402WV05U
1

2 22uF 22uF 100nF

GND
2 1

X5R X5R X5R

2

USB2_OTG0_PWREN_H 4 3 10V 10V 10V

EN OCB
2

C0603 C0603 C0201

TCS9163 EN>1.2V SOT_23_5 R2500
3.6K
Ilim(A)=6800/Rset R0201 2

ED2512
ESDH0402WV05U
ED0402

R2529 0R R0201
1

USB2_HOST1_DM R2530 2.2R R0201 2 1 USB2_HOST1DM

NC
A A
USB2_HOST1_DP R2531 2.2R R0201 L2500 4 3RP2_0405 USB2_HOST1DP
R2532 0R R0201
1

ED2513
ED0402
Note: ESDH0402WV05U Rockchip Electronics Co., Ltd
If common mode inductors are needed,
it is recommended to keep 2.2ohm in series
Project: TB-RK3576D0
2

to improve the antistatic ability

File: 25.USB30x2 TypeA Port

Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 24 of 50

5 4 3 2 1
 5 4 3 2 1

LPDDR4/4X U3800A VDD1_1V8_DDR_S3 F1

U3800B

VDD1_1 VDD1 VSS_1

A3

LPDDR4_DQ0_A LPDDR4_DQ0_B
CH A CH B F12
G4 VDD1_2
VDD1_3
VSS_2
VSS_3
A10
C1
LPDDR4_DQ1_A LPDDR4_DQ1_B LPDDR4_DQ0_A B2 AA2 LPDDR4_DQ0_B G9 C5
LPDDR4_DQ2_A LPDDR4_DQ2_B LPDDR4_DQ1_A C2 DQ0_A
DQ1_A
DQ0_B
DQ1_B
Y2 LPDDR4_DQ1_B T4 VDD1_4
VDD1_5
1.8V VSS_4
VSS_5
C8
LPDDR4_DQ3_A LPDDR4_DQ3_B LPDDR4_DQ2_A E2 V2 LPDDR4_DQ2_B T9 C12
LPDDR4_DQ3_A F2 DQ2_A DQ2_B U2 LPDDR4_DQ3_B U1 VDD1_6 VSS_6 D2
LPDDR4_DQ4_A LPDDR4_DQ4_B DQ3_A DQ3_B VDD1_7 VSS_7
LPDDR4_DQ5_A LPDDR4_DQ5_B LPDDR4_DQ4_A F4 U4 LPDDR4_DQ4_B U12 D4
LPDDR4_DQ5_A E4 DQ4_A DQ4_B V4 LPDDR4_DQ5_B VDD1_8 VSS_8 D9
LPDDR4_DQ6_A LPDDR4_DQ6_B DQ5_A DQ5_B VSS_9
LPDDR4_DQ7_A LPDDR4_DQ7_B LPDDR4_DQ6_A C4 Y4 LPDDR4_DQ6_B D11
LPDDR4_DQ7_A B4 DQ6_A DQ6_B AA4 LPDDR4_DQ7_B A4 VSS_10 E1
D VDD2_DDR_S3 D
LPDDR4_DQS0P_A LPDDR4_DQS0P_B
DQ7_A DQ7_B A9 VDD2_1
VDD2_2
VDD2 VSS_11
VSS_12
E5
LPDDR4_DQS0N_A LPDDR4_DQS0N_B LPDDR4_DQS0P_A D3 W3 LPDDR4_DQS0P_B F5 E8
LPDDR4_DQS0N_A E3 DQS0_T_A DQS0_T_B V3 LPDDR4_DQS0N_B F8 VDD2_3 VSS_13 E12
LPDDR4_DMI0_A LPDDR4_DMI0_B
LPDDR4_DMI0_A
DQS0_C_A DQS0_C_B
LPDDR4_DMI0_B
H1 VDD2_4
VDD2_5 1.1V VSS_14
VSS_15
G1
C3 Y3 H5 G3
DMI0_A DMI0_B H8 VDD2_6 VSS_16 G5
LPDDR4_DQ8_A LPDDR4_DQ8_B VDD2_7 VSS_17
LPDDR4_DQ9_A LPDDR4_DQ9_B LPDDR4_DQ8_A B11 AA11 LPDDR4_DQ8_B H12 G8
LPDDR4_DQ9_A C11 DQ8_A DQ8_B Y11 LPDDR4_DQ9_B K1 VDD2_8 VSS_18 G10
LPDDR4_DQ10_A LPDDR4_DQ10_B DQ9_A DQ9_B VDD2_9 VSS_19
LPDDR4_DQ11_A LPDDR4_DQ11_B LPDDR4_DQ10_A E11 V11 LPDDR4_DQ10_B K3 G12
LPDDR4_DQ11_A F11 DQ10_A DQ10_B U11 LPDDR4_DQ11_B K10 VDD2_10 VSS_20 J1
LPDDR4_DQ12_A LPDDR4_DQ12_B DQ11_A DQ11_B VDD2_11 VSS_21
LPDDR4_DQ13_A LPDDR4_DQ13_B LPDDR4_DQ12_A F9 U9 LPDDR4_DQ12_B K12 J3
LPDDR4_DQ13_A E9 DQ12_A DQ12_B V9 LPDDR4_DQ13_B N1 VDD2_12 VSS_22 J10
LPDDR4_DQ14_A LPDDR4_DQ14_B DQ13_A DQ13_B VDD2_13 VSS_23
LPDDR4_DQ15_A LPDDR4_DQ15_B LPDDR4_DQ14_A C9 Y9 LPDDR4_DQ14_B N3 J12
LPDDR4_DQ15_A B9 DQ14_A DQ14_B AA9 LPDDR4_DQ15_B N10 VDD2_14 VSS_24 K2
DQ15_A DQ15_B N12 VDD2_15 VSS_25 K4
LPDDR4_DQS1P_A LPDDR4_DQS1P_B VDD2_16 VSS_26
LPDDR4_DQS1N_A LPDDR4_DQS1N_B LPDDR4_DQS1P_A D10 W10 LPDDR4_DQS1P_B R1 K9
LPDDR4_DQS1N_A E10 DQS1_T_A DQS1_T_B V10 LPDDR4_DQS1N_B R5 VDD2_17 VSS_27 K11
DQS1_C_A DQS1_C_B R8 VDD2_18 VSS_28 N2
LPDDR4_DMI1_A LPDDR4_DMI1_B VDD2_19 VSS_29
LPDDR4_DMI1_A C10 Y10 LPDDR4_DMI1_B R12 N4
DMI1_A DMI1_B U5 VDD2_20 VSS_30 N9
LPDDR4_A0_A LPDDR4_A0_B VDD2_21 VSS_31
LPDDR4_A1_A LPDDR4_A1_B LPDDR4_A0_A H2 R2 LPDDR4_A0_B U8 N11
LPDDR4_A1_A J2 CA0_A CA0_B P2 LPDDR4_A1_B AB4 VDD2_22 VSS_32 P1
LPDDR4_A2_A LPDDR4_A2_B CA1_A CA1_B VDD2_23 VSS_33
LPDDR4_A3_A LPDDR4_A3_B LPDDR4_A2_A H9 R9 LPDDR4_A2_B AB9 P3
LPDDR4_A3_A H10 CA2_A CA2_B R10 LPDDR4_A3_B VDD2_24 VSS_34 P10
LPDDR4_A4_A LPDDR4_A4_B CA3_A CA3_B VSS_35
LPDDR4_A5_A LPDDR4_A5_B LPDDR4_A4_A H11 R11 LPDDR4_A4_B P12
LPDDR4_A5_A J11 CA4_A CA4_B P11 LPDDR4_A5_B B3 VSS_36 T1
LPDDR4_CLKP_A LPDDR4_CLKP_B
CA5_A CA5_B VDDQ_DRAM_S0
B5 VDDQ_1
VDDQ_2
VDDQ VSS_37
VSS_38
T3
LPDDR4_CLKN_A LPDDR4_CLKN_B LPDDR4_CLKP_A J8 P8 LPDDR4_CLKP_B B8 T5
C LPDDR4_CLKN_A J9 CK_T_A CK_T_B P9 LPDDR4_CLKN_B B10 VDDQ_3 VSS_39 T8 C
LPDDR4_CSN0_A LPDDR4_CSN0_B
CK_C_A CK_C_B D1 VDDQ_4
VDDQ_5
LP4 VSS_40
VSS_41
T10
LPDDR4_CKE0_A J4 P4 LPDDR4_CKE0_B D5 T12
LPDDR4_CSN1_A LPDDR4_CSN1_B
LPDDR4_CKE1_A J5 CKE0_A CKE0_B P5 LPDDR4_CKE1_B D8 VDDQ_6 1.1V VSS_42 V1
K8 CKE1_A CKE1_B N8 D12 VDDQ_7 VSS_43 V5
LPDDR4_CKE0_A LPDDR4_CKE0_B CKE2_A_NC CKE2_B_NC VDDQ_8 VSS_44
F3 V8
LPDDR4_CKE1_A LPDDR4_CKE1_B
F10 VDDQ_9
VDDQ_10
LP4x VSS_45
VSS_46
V12
LPDDR4_RESET LPDDR4_CSN0_A
LPDDR4_CSN1_A
H4
H3 CS0_A CS0_B
R4
R3
LPDDR4_CSN0_B
LPDDR4_CSN1_B
U3
U10 VDDQ_11 0.6V VSS_47
W2
W4
K5 CS1_A CS1_B N5 W1 VDDQ_12 VSS_48 W9
CS2_A_NC CS2_B_NC W5 VDDQ_13 VSS_49 W11
G2 T2 W8 VDDQ_14 VSS_50 Y1
VDD2_DDR_S3 ODT_CA_A ODT_CA_B VDD2_DDR_S3 VDDQ_15 VSS_51
PMIC_PWR_CTRL2 W12 Y5
AA3 VDDQ_16 VSS_52 Y8
AA5 VDDQ_17 VSS_53 Y12
R3802 240R 1% R0201 A5 AA8 VDDQ_18 VSS_54 AB3
VDDQ_DRAM_S0 ZQ0 VDDQ_19 VSS_55
R3804 240R 1% R0201 A8 AA10 AB5
G11 ZQ1 T11 LPDDR4_RESET VDDQ_20 VSS_56 AB8
ZQ2_NC RESET_n VSS_57 AB10
C3800 VSS_58
NC/1nF

2 1
LPDDR4_200P X5R
BGA200_15R00X10R00X0R90 25V A1 AA1
C0201 A2 DNU_1 DNU_7 AA12
A11 DNU_2 DNU_8 AB1
A12 DNU_3 DNU_9 AB2
B1 DNU_4 DNU_10 AB11
B12 DNU_5 DNU_11 AB12
DNU_6 DNU_12
B B
LPDDR4_200P
BGA200_15R00X10R00X0R90

VDDQ_DRAM_S0
Note： VDD1_1V8_DDR_S3 VCCA1V8_PLDO6_S3
Sequence:VDD1-VDD2-VDDQ
R3812 NC/0R C3801 C3802 C3803 C3804 C3805 C3806 C3807 C3808 C3809 C3810 C3811 C3812 C3813 C3814 C3815 C3816 C3817 C3818 C3819
LPDDR4 LPDDR4X R0402 22uF 10uF 10uF 1uF 1uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1
VCC_1V8_S3 X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
VDD1: 1.70-1.95 1.70-1.95 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VDD2: 1.06-1.17 1.06-1.17 R3806 0R R0402 C0603 C0603 C0603 C0402 C0402 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
VDDQ: 1.06-1.17 0.57-0.65 C3820
10uF
2 1

X5R
10V
C0603 VDD2_DDR_S3
OPTION:LPDDR4
VDD2_DDR_S3 VDDQ_DRAM_S0 VDDQ_DRAM_S0 VDDQ_DDR_S0 C3821 C3822 C3823 C3824 C3825 C3826 C3827 C3828 C3829 C3830 C3831 C3832 C3833 C3834 C3835
0.6V 22uF 10uF 10uF 1uF 1uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1
3 2 1.1V R3807 0R R0603 X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
Q3800 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
NC/WNM2016-3/TR C0603 C0603 C0603 C0402 C0402 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
VCC5V0_SYS_S5 SOT_23 OPTION:LPDDR4x(default)
1

A A
R3810
NC/100K
R0201 R3811 C3845 VDD1_1V8_DDR_S3
2 1

NC/10K NC/1nF
R0201 C0201
EN=2.8V X5R Rockchip Electronics Co., Ltd
3

25V C3836 C3837 C3838 C3839 C3840 C3841 C3842 C3843 C3844
RC Delay 54us Q3801 10uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
Project: TB-RK3576D0
2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

PMIC_PWR_CTRL2 1 NC/WNM2021-3/TR X5R X5R X5R X5R X5R X5R X5R X5R X5R
SOT_323 VDDQ_DDR_CKE_S3 VDD2_DDR_S3 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
File: 38.DRAM-LPDDR4X_1X32bit_200P
2

C0603 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201

R3809 0R R0402 Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 25 of 50

5 4 3 2 1
 5 4 3 2 1

eMMC_D0/FLASH_D0
eMMC FLASH / UFS Note:
For particles that require VCCQ and VCCQ2,
the following timing needs to be met:
eMMC_D1/FLASH_D1
eMMC_D2/FLASH_D2
eMMC_D3/FLASH_D3 Sequence: VDDA_1V2_S0->VCCQ2->VCCQ
eMMC_D4/FLASH_D4
eMMC_D5/FLASH_D5 VDDA_1V2_S0 is the power of REF_CK & RST_N
D D
eMMC_D6/FLASH_D6
eMMC_D7/FLASH_D7 in RK SOC, which needs to be powered on before
UFS particles
eMMC_CMD/FLASH_RSTN

eMMC_CLKOUT/FLASH_CLK

eMMC_STROBE/FLASH_DQS VCCQ VCCQ2 VCC

eMMC_RSTn/FLASH_CSN0 UFS2.0 1.2V 1.8V 3.3V
UFS2.1 No Connect 1.8V 3.3V
Default
UFS2.2 No Connect 1.8V 3.3V UFS device
UFS3.0 1.2V No Connect 2.5V/3.3V UFS2.2
1 2
GND1 GND2
VCCIO_1V8_S0
eMMC_D5/FLASH_D5 3
D5 D6
4 eMMC_D6/FLASH_D6 UFS3.1 1.2V No Connect 2.5V/3.3V
5 6
GND3 GND4
eMMC_D4/FLASH_D4 7
D4 D7
8 eMMC_D7/FLASH_D7 UFS4.0 1.2V No Connect 2.5V
C 9 10 C
eMMC_D0/FLASH_D0 11 GND5 GND6 12 eMMC_D1/FLASH_D1
D0 D1
R4003 13
GND7 GND8
14 Sequence:VCCQ2->VCCQ, VCC is independent
10K eMMC_CLKOUT/FLASH_CLK 15 16 eMMC_D2/FLASH_D2
R0201 17 CLK D2 18
eMMC_D3/FLASH_D3 19 GND9 GND10 20 eMMC_CMD/FLASH_RSTN
D3 CMD VCCIO_1V8_S0
21 22 R4005
eMMC_RSTn/FLASH_CSN0 GND11 GND12
23
RSTN VDD1
24 VCC_3V3_S010K
R4004 25 26 R0201
10K 27 GND13 VDD2 28
GND14 VDDIO1 VCCIO_1V8_S0
R0201 eMMC_STROBE/FLASH_DQS 29 30
31 RCLK VDDIO2 32
33 GND15 GND16 34
GND17 GND18

SARADC_VIN0_BOOT SARADC_VIN0_BOOT 35 36
37 GND19 GND20 38
GND21 GND22 UFS_TX_D0P
39 40 UFS_TX_D0N
VCC_3V3_S0 41 GND23 GND24 42
43 GND25 GND26 44
B UFS_TX_D1P B
VCC_1V8_S3 45 GND27 GND28 46
GND29 GND30 UFS_TX_D1N VCCIO_1V8_S0 VCC_3V3_S0
47 48
VDDA_1V2_S0 49 GND31 GND32 50
GND33 GND34 UFS_RX_D0P
51 52 UFS_RX_D0N
VCC5V0_SYS_S5 53 GND35 GND36 54
55 GND37 GND38 56 C4004 C4005 C4007 C4008
GND39 GND40 UFS_RX_D1P
57 58 UFS_RX_D1N 100nF 4.7uF 100nF 4.7uF

2 1

2 1

2 1

2 1
59 GND41 GND42 60 X5R X5R X5R X5R
61 GND43 GND44 62 10V 6.3V 10V 6.3V
GND45 GND46 UFS_RSTn
63 64 C0201 C0402 C0201 C0402
65 GND47 GND48 66
GND49 GND66 UFS_REFCLK
67 68
GND51 GND52

69 70
71 GND53 GND54 72
73 GND55 GND56 74
GND57 GND58
75
GND59 GND60
76
Note:
A The power ball that is not used at the particle A
J4001
YXT-BB10-34P-02x2 must be kept floating. Rockchip Electronics Co., Ltd
YXT-BB10-34P-02x2
Note: Project: TB-RK3576D0
For particles above UFS4.0, Pin B13, P3, File: 40.Flash connect-eMMC/UFS
and P6 need to refer to the particle
datasheet for design Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 26 of 50

5 4 3 2 1
 5 4 3 2 1

TF CARD
VCC_3V3_S3 VCC3V3_SD
SDMMC0_D0 U4200
SDMMC0_D1 5 1
C4200 IN VOUT C4201
SDMMC0_D2
SDMMC0_D3 1uF 2 1uF

2 1

2 1
D X5R GND X5R D

SDMMC0_CMD 6.3V SDMMC0_PWREN_H 4 3 6.3V

C0201 EN OCB C0201
SDMMC0_CLK TCS9163
SDMMC0_DET_L SOT_23_5
R4202 Default:TCS9163 R4203
1M Ilim=6800/RILIM(A) 4.7K
SDMMC0_PWREN_H
R0201 R0201

Note:
SDMMC_PWREN=H VCC3V3_SD(Default)
SDMMC_PWREN=L VCC3V3_SD=0V

C C

12
9
G4

G3
VCC3V3_SD SDMMC0_D2 1
SDMMC0_D3 2 DATA2
SDMMC0_CMD 3 CD/DATA3
4 CMD
VDD
1

SDMMC0_CLK 5
ED4207 6 CLK
D1006WV05C150BT SDMMC0_D0 7 VSS
ED0402 SDMMC0_D1 8 DATA0
C4203 C4204 G1 DATA1
10uF 100nF CD

G1

G2
2 1

2 1
2

X5R X5R 1 J4200

1
6.3V 10V D4201 D4202 D4203 D4204 D4205 D4206 TF150-016

10

11
C0402 C0201 D4200 ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U TF-123-ARP9H1R5
B ESD0402 ED0402 ED0402 ED0402 ED0402 ED0402 ED0402 B
ESD5471X

Close to MicroSD Card

2

2
SDMMC0_DET_L
3

Q4200 1
S8050 R4205
SOT_23 10K
2

R0201 R4201
100K
R0201

A A

Rockchip Electronics Co., Ltd

Note: Project: TB-RK3576D0
SDMMC_DET_L:
SDCARD PLUG: Pull-down to GND File: 42.Flash-MicroSD Card
SDCARD UNPLUG: Pull-up to PMUIO0_VCC1V8. Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 28 of 50

5 4 3 2 1
 5 4 3 2 1

MIPI DCPHY Camera MIPI DPHY Camera

MIPI_DPHY_CSI0_RX_D0N CAM_CLK0_OUT_M1 MIPI_DPHY_CSI3_RX_D0N
MIPI_DPHY_CSI0_RX_D0P I2C9_SDA_M2_MIPI_CSI0 MIPI_DPHY_CSI3_RX_D0P
MIPI_DPHY_CSI0_RX_D1N I2C9_SCL_M2_MIPI_CSI0 MIPI_DPHY_CSI3_RX_D1N
MIPI_DPHY_CSI0_RX_D1P MIPI_DPHY_CSI0_PDN_H MIPI_DPHY_CSI3_RX_D1P
MIPI_DPHY_CSI0_RX_CLKN MIPI_DPHY_CSI_PWREN_H MIPI_DPHY_CSI3_RX_CLKN
D D
MIPI_DPHY_CSI0_RX_CLKP MIPI_DPHY_CSI3_RX_CLKP
MIPI_DPHY_CSI0_RX_D2N MIPI_DPHY_CSI3_RX_D2N
MIPI_DPHY_CSI0_RX_D2P MIPI_DPHY_CSI3_RX_D2P
MIPI_DPHY_CSI0_RX_D3N MIPI_DPHY_CSI3_RX_D3N
MIPI_DPHY_CSI0_RX_D3P MIPI_DPHY_CSI3_RX_D3P
CAM_CLK2_OUT_M1

J4702

33

32
J4701 CNN30_1R00_FP05SL_V

33

32
CNN30_1R00_FP05SL_V

GND_9

GND_8
1

GND_9

GND_8
1 MIPI_DPHY_CSI3_RX_D3N 2 GND_0
MIPI_DPHY_CSI0_RX_D3N 2 GND_0 MIPI_DPHY_CSI3_RX_D3P 3 MIPI_D3N
MIPI_DPHY_CSI0_RX_D3P 3 MIPI_D3N 4 MIPI_D3P
C C
4 MIPI_D3P MIPI_DPHY_CSI3_RX_D2N 5 GND_1
MIPI_DPHY_CSI0_RX_D2N 5 GND_1 MIPI_DPHY_CSI3_RX_D2P 6 MIPI_D2N
MIPI_DPHY_CSI0_RX_D2P 6 MIPI_D2N 7 MIPI_D2P
7 MIPI_D2P MIPI_DPHY_CSI3_RX_CLKN 8 GND_2
MIPI_DPHY_CSI0_RX_CLKN 8 GND_2 MIPI_DPHY_CSI3_RX_CLKP 9 MIPI_CLKN
MIPI_DPHY_CSI0_RX_CLKP 9 MIPI_CLKN 10 MIPI_CLKP
10 MIPI_CLKP MIPI_DPHY_CSI3_RX_D1N 11 GND_3
MIPI_DPHY_CSI0_RX_D1N 11 GND_3 MIPI_DPHY_CSI3_RX_D1P 12 MIPI_D1N
MIPI_DPHY_CSI0_RX_D1P 12 MIPI_D1N 13 MIPI_D1P
13 MIPI_D1P MIPI_DPHY_CSI3_RX_D0N 14 GND_4
MIPI_DPHY_CSI0_RX_D0N 14 GND_4 MIPI_DPHY_CSI3_RX_D0P 15 MIPI_D0N
MIPI_DPHY_CSI0_RX_D0P 15 MIPI_D0N 16 MIPI_D0P
16 MIPI_D0P 17 GND_5
GND_5 NC1
17
NC1 CAM_CLK2_OUT_M1 1V8 18
CAM_MCLK
CAM_CLK0_OUT_M1 MIPI_MCLK0 1V8 18
CAM_MCLK VCC_3V3_S3 19
VCC_IO
VCC_3V3_S3 19 20
20 VCC_IO 21 NC2
NC2 MIPI_DPHY_CSI3_PDN_H MIPI_PDN
MIPI_DPHY_CSI0_PDN_H MIPI_CAM_PDN_L 21 22
22 MIPI_PDN 23 NC3
NC3 I2C6_SCL_M1_mipiCSI3 MIPI_SCL
B I2C9_SCL_M2_MIPI_CSI0 23 I2C6_SDA_M1_mipiCSI3 24 B
24 MIPI_SCL 25 MIPI_SDA
I2C9_SDA_M2_MIPI_CSI0 MIPI_SDA NC4
25 MIPI_DPHY_CSI3_PWREN_H 26
26 NC4 27 MIPI_RST
MIPI_DPHY_CSI_PWREN_H MIPI_RST GND6
27 28
28 GND6 29 VCC_SYS_0
VCC5V0_SYS_S5

GND_10
VCC_SYS_0 VCC_SYS_1

GND_7
VCC5V0_SYS_S5 29 30
GND_10

VCC_SYS_1 VCC_SYS_2
GND_7

30
VCC_SYS_2

34

31
VCC5V0_SYS_S5 VCC_3V3_S3
34

31

C4700 C4701 C4702

R4700 4.7uF 100nF 100nF
2 1

2 1

2 1

1M X5R X5R X5R

R0201 10V 10V 10V
C0402 C0201 C0201

A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 47.VI-Camera_MIPI-CSI
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 31 of 50

5 4 3 2 1
 5 4 3 2 1

Diff 100 Ohm ±10%

MIPI_DPHY_DSI_TX_D0N
MIPI_DPHY_DSI_TX_D0P

MIPI_DPHY_DSI_TX_D1N
MIPI_DPHY_DSI_TX_D1P

MIPI_DPHY_DSI_TX_D2N
MIPI_DPHY_DSI_TX_D2P
LCD_RESET_L R5010 0R R0201 LCD_RST
MIPI_DPHY_DSI_TX_D3N C5015
MIPI_DPHY_DSI_TX_D3P 100nF

2 1
X5R
D MIPI_DPHY_DSI_TX_CLKN 6.3V D
MIPI_DPHY_DSI_TX_CLKP C0201

I2C0_SCL_M1_TP
I2C0_SDA_M1_TP
TP_INT_L
TP_RST_L

LCD_BL_PWM1_CH1_M0
LCD_PWREN_H
LCD_RESET_L
I2C0_SDA_M1_TP TP_SDA/SPI_DO
I2C0_SCL_M1_TP TP_SCL/SPI_DI
TP_INT_L TP_INT
TP_RST_L TP_RST

C C

32

33
J5000

GND_32

GND_33
CNN30_1R00_FP05SL_V
CNN30_1R00_FP055SL_Z

1 VCC5V0_SYS_S5 VCC_3V3_S3
1 2
2 MIPI_DPHY_DSI_TX_D0N
MIPI_DPHY_DSI_TX_D0P 3
3 4 C5000 C5001 C5002
5 4 R5000 4.7uF 100nF 100nF
MIPI_DPHY_DSI_TX_D1N 5

2 1

2 1

2 1
6 MIPI_DPHY_DSI_TX_D1P 1M X5R X5R X5R
7 6 R0201 10V 10V 10V
7 8 C0402 C0201 C0201
8 MIPI_DPHY_DSI_TX_CLKN
MIPI_DPHY_DSI_TX_CLKP 9
9 10
11 10
MIPI_DPHY_DSI_TX_D2N 11 12 MIPI_DPHY_DSI_TX_D2P
13 12
B 13 14 B
14 MIPI_DPHY_DSI_TX_D3N
MIPI_DPHY_DSI_TX_D3P 15
15 16
LCD_BL_PWM1_CH1_M0 17 16
17 18
19 18
VCC_3V3_S3 19 20 LCD_RST
21 20
21 22 LCD_PWREN_H
TP_SCL/SPI_DI 23 22
23 24 TP_SDA/SPI_DO
TP_INT 25 24
25 26 TP_RST
27 26
27 28
29 28
VCC5V0_SYS_S5 29 30 VCC5V0_SYS_S5
30
GND_31

GND_34
31

34

A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 50.VO-LCM MIPI DPHY TX
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason.Deng Reviewed by: Sheet: 32 of 50

5 4 3 2 1
 5 4 3 2 1

HDMI 2.1
HDMI_TX_SBDP
HDMI_TX_SBDN
Support video output up to 4Kx2K@120Hz
HDMI_TX_D0P
HDMI_TX_D0N
HDMI_TX_D1P
Note:
HDMI_TX_D1N Close to HDMI Connector Diff 100 Ohm ±10%
HDMI_TX_D2P
HDMI_TX_D2N HDMI_TX_D0P C5600 1 2 220nF C0201 X5R 10V HDMI_TX0P
HDMI_TX_D3P HDMI_TX_D0N C5601 1 2 220nF C0201 X5R 10V HDMI_TX0N
HDMI_TX_D3N
HDMI_TX_D1P C5602 1 2 220nF C0201 X5R 10V HDMI_TX1P
HDMI_TX_D1N C5603 1 2 220nF C0201 X5R 10V HDMI_TX1N
D HDMI_TX_SDA D
HDMI_TX_SCL HDMI_TX_D2P C5604 1 2 220nF C0201 X5R 10V HDMI_TX2P
HDMI_TX_D2N C5605 1 2 220nF C0201 X5R 10V HDMI_TX2N
HDMI_TX_CEC_M0
HDMI_TX_D3P C5606 1 2 220nF C0201 X5R 10V HDMI_TX3P
HDMI_TX_HPDIN_M0 HDMI_TX_D3N C5607 1 2 220nF C0201 X5R 10V HDMI_TX3N

HDMI_TX_ON_H
Note: R5600 R5601 R5602 R5603 R5604 R5605 R5606 R5607
Close to 590R
1%
590R
1%
590R
1%
590R
1%
590R
1%
590R
1%
590R
1%
590R
1%
HDMI Connector R0201 R0201 R0201 R0201 R0201 R0201 R0201 R0201

3
Q5600 Q5601 Q5602 Q5603

HDMI_TX_ON_H
WNM6002-3/TR
SOT_323 1
WNM6002-3/TR
SOT_323 1
WNM6002-3/TR
SOT_323 1
WNM6002-3/TR
SOT_323
Rds=1.7ohm/2.6V
1
Coss=7.33pf

2
C
Note: Note: C
The controller only support AC coupled
The HDMI2.1 trace length is less than 100mm. link. In order to backward compatibility
The HDMI2.1 differential trace impedance is 100 OHM. or to meet HDMI2.0 (1.4b) DC common
mode spec and Voff, need do R based
level-shift.
Switch on in HDMI2.0(TMDS) mode
Switch off in HDMI2.1(FRL) mode.

VCC5V0_SYS_S5 VCC5V_HDMI_TX HDMI TX ARC

Cj<=0.2pF

23

22
D5600 1 2 B5819W HDMI_TX_SBDP C5608 1 2 1uF HDMITX_SBDP
SOD_123 C0201 X5R 10V

G4

G3
HDMI_TX_SBDN C5609 1 2 1uF HDMITX_HPDIN/HDMITX_SBDN ED5600 CES0D44033LUQ
R5610 NC/0R R0402 C0201 X5R 10V SON10_2R50X1R00X0R50
HDMI_TX2P 1 10 HDMI_TX2P 1
HDMI_TX2N 2 IO1 NC_10 9 HDMI_TX2N 2 D2P
3 IO2 NC_9 8 3 D2_G

B
HDMI TX DDC HDMI TX HPD HDMI_TX1P
HDMI_TX1N
4
5
GND
IO3
GND 7
NC_7 6
HDMI_TX1P
HDMI_TX1N
4
5
D2N
D1P B
VCC_3V3_S0 IO4 NC_6 6 D1_G
VCC5V0_SYS_S5 HDMI_TX0P 1 10 HDMI_TX0P 7 D1N
HDMI_TX0N 2 IO1 NC_10 9 HDMI_TX0N 8 D0P

Type A
3 IO2 NC_9 8 9 D0_G
GND GND D0N
1

HDMI_TX3P 4 7 HDMI_TX3P 10
D5601 R5611 R5612 HDMI_TX3N 5 IO3 NC_7 6 HDMI_TX3N 11 CLKP
B5819WS 47K 47K IO4 NC_6 12 CLK_G
VCC_3V3_S0 SOD_323 R0201 R0201 HDMI_TX_CEC_PORT ED5601 CES0D44033LUQ 13 CLKN
HDMI_TX_HPDIN_M0 SON10_2R50X1R00X0R50 HDMITX_SBDP 14 CEC
Utility
2

HDMI_TX_SCL_PORT 15
SCL
3

3.3V IO HDMI_TX_SDA_PORT 16
17 SDA
R5613 Q5605 R5614 1 18 GND
VCC5V_HDMI_TX +5V
20K 2SK3018 1.8K Q5604 Q5606 2.4-5.3V HDMITX_HPDIN/HDMITX_SBDN 19
HPD
2
1

R0201 SOT_323 R0201 2SK3018 2SK3018

R5616
SOT_323 SOT_323

2
HDMI_TX_SCL 2 3 HDMI_TX_SCL_PORT 1 HDMITX_HPDIN/HDMITX_SBDN ED5605 ED5606 ED5602 ED5603 ED5604
R5615 ESDH0402WV05UESDH0402WV05UESDH0402WV05UESDH0402WV05U ESDH0402WV05U C5610

G1

G2
2

100R R5617 ED0402 ED0402 ED0402 ED0402 ED0402 1uF

1.2K

2 1
R0201 47K X5R J5600

20

21
VCC_3V3_S0 R0201 R0201 10V HDMI_A
C0402 HDMIA19_HDMI_01A

1
R5618
0R
R0201 HDMI TX CEC
A VCC_3V3_S0 VCC5V0_SYS_S5 A
C5611
R5619 NC/100pF Q5607 R5620
2 1

20K C0G 2SK3018 1.8K

1

R0201 25V SOT_323 R0201

C0201 R5622 Q5608
HDMI_TX_SDA 2 3 HDMI_TX_SDA_PORT 27K 2SK3018 Rockchip Electronics Co., Ltd
1

R5621 R0201 SOT_323

100R
R0201 HDMI_TX_CEC_M0 HDMI_TX_CEC_PORT
Project: TB-RK3576D0
2 3
R5623 100R R0201
File: 56.VO-HDMI TX
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 32 of 49

5 4 3 2 1
 5 4 3 2 1

SAI2_SCLK_M1
SAI2_LRCK_M1 ANT_JACK
SDMMC1_D0 SAI2_SDO_M1 ANT6400 ANT_JACK
SDMMC1_D1 SAI2_SDI_M1 1
VCC_3V3_S3 ANT
SDMMC1_D2
2 1 2

BT_WAKE_HOST_H
HOST_WAKE_BT_H
SDMMC1_D3 UART7_TX_M0 VCC_3V3_S3 GND1
UART7_RX_M0 3
C6402 C6400 GND2
SDMMC1_CMD UART7_RTSN_M0
UART7_CTSN_M0 10pF NC
SDMMC1_CLK

2 1
D C6418 C6149 C0G C0201 D

BT_REG_ON_H 100nF 4.7uF 25V

2 1

2 1
BT_WAKE_HOST_H X5R X5R C0201 2 1
HOST_WAKE_BT_H 10V 6.3V
WIFI_REG_ON_H C0201 C0402 C6405
32KOUT_RTC WIFI_WAKE_HOST_H NC
C0201 U6200
AW-CM467-SUR-I

11
10
9
8
7
6
5
4
3
2
1
SDIO WIFI/BT5.0 Module
MD44_AP6XXX

XTAL_OUT
XTAL_IN
VBAT
BT_VIO/N_HOST_WAKE
BT_HOST_WAKE
BT_WAKE
N_WAKE
FM_RX
GND2
WL_BT_ANT
GND1
47
N_VDDSWP_IN
VBAT 必须同时或者先于 VDDIO上电; N_VDDSWP_OUT
46
45
若不满足，则需要wl_reg_on最后上电 N_VDDSWPIO

WIFI_REG_ON_H 12
WIFI_WAKE_HOST_H 13 WL_REG_ON 44 UART7_RTSN_M0
C C
VCC_1V8_S3 VCCIO_WL SDMMC1_D2 14 WL_HOST_WAKE UART_CTS_N 43 UART7_TX_M0
SDMMC1_D3 15 SDIO_DATA_2 UART_RXD 42 UART7_RX_M0
SDMMC1_CMD 16 SDIO_DATA_3 UART_TXD 41 UART7_CTSN_M0
SDMMC1_CLK 17 SDIO_DATA_CMD UART_RTS_N 40
VCCIO_WL SDMMC1_D0 18 SDIO_DATA_CLK TX1 39
SDMMC1_D1 19 SDIO_DATA_0 TX2 38
VCCIO_WL 20 SDIO_DATA_1 N_REG_PU 37
C6422 C6423 21 GND3 N_I2C_SCL 36
100nF 4.7uF 22 VIN_LDO_OUT GND6 35
2 1

2 1

X5R X5R VDDIO N_I2C_SDA 34 BT_REG_ON_H

10V 6.3V BT_RST_N
C0201 C0402

1A_DCR<=80mohm

L6400
2.2uH

PCM_SYNC
VDD_TCXO
IND_252012

VIN_LDO

PCM_OUT
PCM_CLK

TCXO_IN
PCM_IN

GPS_RF
B B

GND4

GND5
LPO
23
24
25
26
27
28
29
30
31
32
33
C6415
4.7uF VCCIO_WL
2 1

X5R
6.3V
C0402 R6018
32KOUT_RTC R6408 0R R0201 WIFIBT_32KIN_2T2R 10K
32.768KHZ: R0201 配置SDIO为1V8
C6421
+/-25ppm/30-70%/1.8V
2 1

NC VBAT:(3.1-3.8V)/1.2A
C0201 R6004
NC/10K VDDIO:(1.68-1.98V)/300mA.
R0201

SAI2_SDI_M1
A
SAI2_SCLK_M1 A
SAI2_SDO_M1
SAI2_LRCK_M1 Rockchip Electronics Co., Ltd
Project: TB-RK3576D0
File: 64.WIFI6/BT-PCIE+UART_2T2R
Date: Friday, July 12, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 34 of 50

5 4 3 2 1
 5 4 3 2 1
OPTION1 Y6800
25.000MHz DNP

2
PHY1_XTALOUT 1 4 ESD6801 ESD6803 ESD6805 ESD6807
X1 GND ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U
GMAC1_TXD0_M1
2 3 PHY1_XTALIN ED0402 ED0402 ED0402 ED0402
GMAC1_TXD1_M1 GND X2 DNP ESD6802 DNP ESD6804 DNP ESD6806 DNP ESD6808 J6800

21

22
GMAC1_TXD2_M1
C6800 CRY4_2R00X1R60X0R55 C6801 ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U SYT111Q334AB2A2DP057
GMAC1_TXD3_M1

1
18pF 18pF ED0402 ED0402 ED0402 ED0402
GMAC1_TXEN_M1

21

22
1

1
C0G C0G PHY1_MDI0+ DNP DNP PHY1_MDI_0+ DNP DNP 1
50V 50V PHY1_MDI0- PHY1_MDI_0- 2 TDI1+
GMAC1_TXCLK_M1 TDI1-

2
C0201 C0201 PHY1_MDI1+ PHY1_MDI_1+ 3
DNP 优先级低，考虑删除 DNP PHY1_MDI1- PHY1_MDI_1- 6 TDI2+
GMAC1_RXD0_M1 TDI2-
GMAC1_RXD1_M1
GMAC1_RXD2_M1 PHY1_MDI2+ PHY1_MDI_2+ 7
TDI3+
D GMAC1_RXD3_M1 OPTION2 default PHY1_MDI2-
PHY1_MDI3+
PHY1_MDI_2-
PHY1_MDI_3+
8
TDI3- D
GMAC1_RXDV_CRS_M1 9
ETH_CLK1_25M_OUT_M1 R6808 0R R0201 PHY1_XTALIN PHY1_MDI3- PHY1_MDI_3- 10 TDI4+
4 TDI4-
GMAC1_RXCLK_M1 4
J6802 C6802 1 2 100nF X5R 5
5
ETH_CLK1_25M_OUT_M1 OPTION3 4
4 2
2 TR0 C0201 10V 11
VC1
TR1 12
3 1 TR2 13 VC2
3 1 14 VC3
CON2*2 TR3
VC4
GMAC1_MDC_M1
GMAC1_MDIO_M1
PHY1_LED1/CFG_LDO0 15
R6811 510R R0201 16 G+
R6813 510R R0201 17 G-
VCC3V3_PHY1 Y+
GMAC1_INT/PMEB_3V3 18
R6841 1 DNP Y-
GMAC1_RSTn_3V3 2 0R Tab down

19

20
R0201 5%
PHY1_LED2/CFG_LDO1 R6842 0R R0201

19

20
R6801 1M
R6843 NC/510R R0603 PHY1_CHASSIS_GND
R0201 C6803 2 1 1000pF 2KV
C1206

R6815 1 4.7K 2 R0201 5% PHY1_LED0/CFG_EXT R6812 1 4.7K 2 R0201 5% VCC3V3_PHY1

DNP RGMII Power Source CFG_EXT CFG_LDO[1:0] PHY1_LED2
R6814 1 4.7K 2 R0201 5% PHY1_LED2/CFG_LDO1 R6816 1 4.7K 2 R0201 5%
VDD10_PHY1 DNP External 3.3V(default) 1'b1 2'b00 String 510R to GND
VCC3V3_PHY1 R6817 1 4.7K 2 R0201 5% PHY1_LED1/CFG_LDO0
PHY1_LED2/CFG_LDO1
PHY1_LED1/CFG_LDO0
PHY1_LED0/CFG_EXT

R6818 2.49K External 1.8V 1'b1 2'b10 String 510R to VCC3V3_PHY

C 1% R0201
VCC_PHY0_IO Voltage Config 默认内部1V8 C

2
Internal 1.8V(default) 1'b0 2'b10 String 510R to VCC3V3_PHY
PHY1_XTALOUT
PHY1_XTALIN

R6845
VCC3V3_PHY1 4.7K PHY1_RXD3/PHYAD0 R6819 1 4.7K 2 R0201 5% VCCIO_PHY1
R0201
RSET1

GMAC1_INT/PMEB_3V3 1 5% R6821 1 4.7K 2 R0201 5% PHY1_RXCLK/PHYAD1 R6822 1 4.7K 2 R0201 5% VCCIO_PHY1 PHY1_LED2/CFG_LDO1 PHY1_LED1/CFG_LDO0
od DNP
OD,pull up 3.3V R6823 1 4.7K 2 R0201 5% PHY1_RXDV/PHYAD2 C6805 C6806 Reserve for EMI.

1
100pF 100pF
Connect to the GPIO in C0G C0G
41

40
39
38
37
36
35
34
33
32
31

U6800 SOC 3.3V power domain. PHY Address Config PHY Address PHYAD[2:0] 50V 50V

2
1 (default) 3'b001 C0201 C0201
E_Pad

AVDD33
RSET
AVDD10
XTAL_OUT/EXT_CLKIN
XTAL_IN
CLKOUT
LED2/CFG_LDO1
LED1/CFG_LDO0
LED0/CFG_EXT
INTB/PMEB

DNP DNP

R6824 1 4.7K 2 R0201 5% PHY1_RXD0/RXDLY R6825 1 4.7K 2 R0201 5% VCCIO_PHY1

DNP
PHY1_MDI0+ 1 30 PHY1_REG_OUT
PHY1_MDI0- MDI[0]+ REG_OUT
2
3 MDI[0]- DVDD33
29
28
VCC3V3_PHY1 Pull-up for additional 2ns delay to RXC for data latching
VDD10_PHY1 AVDD10 DVDD_RG VCCIO_PHY1
PHY1_MDI1+ 4 27 PHY1_RXCLK/PHYAD1
PHY1_MDI1- 5 MDI[1]+ RXC/PHYAD1 26 PHY1_RXDV/PHYAD2
PHY1_MDI2+ 6 MDI[1]- RXCTL/PHYAD2 25 PHY1_RXD0/RXDLY R6826 1 4.7K 2 R0201 5% PHY1_RXD1/TXDLY R6827 1 4.7K 2 R0201 5%
MDI[2]+ RXD0/RXDLY VCCIO_PHY1
PHY1_MDI2- 7 24 PHY1_RXD1/TXDLY DNP
8 MDI[2]- RXD1/TXDLY 23 PHY1_RXD2/PLLOFF
VDD10_PHY1 AVDD10 RXD2/PLLOFF VCC_3V3_S0 VCCIO_PHY1
PHY1_MDI3+
PHY1_MDI3-
9
MDI[3]+ RXD3/PHYAD0
22 PHY1_RXD3/PHYAD0
Pull-up for additional 2ns delay to TXC for data latching 默认内部1V8 Close to PIN28
10 21 VDD10_PHY1
MDI[3]- DVDD10 R6828 NC/0R
R6829 1 4.7K 2 R0201 5% PHY1_RXD2/PLLOFF R6830 1 4.7K 2 R0201 5% VCCIO_PHY1 R0402
B DNP VCCIO_1V8_S0 C6807 C6808 C6809 B

1
4.7uF 1uF 100nF
PHYRSTB
AVDD33

2 1

2 1
R6810 NC/0R X5R X5R X5R
TXCTL

Pull-up to disable PLL @ ALDPS mode(Low power mode)

MDIO
TXD3
TXD2
TXD1
TXD0

R0402 6.3V 6.3V 10V

MDC

TXC

2
C0402 C0201 C0201
RK631A
11
12
13
14
15
16
17
18
19
20

QFN40_5R00X5R00X0R90_T
GMAC1_TXCLK_M1
GMAC1_MDIO_M1
GMAC1_TXD3_M1
GMAC1_TXD2_M1
GMAC1_TXD1_M1
GMAC1_TXD0_M1
GMAC1_TXEN_M1
GMAC1_MDC_M1

VCC3V3_PHY1
RTL8211F-CG(SW Mode)
PHY1_RSTn

RTL8211FI-CG(SW Mode)Industrial VDD10_PHY1 VCC_3V3_S0 VCC3V3_PHY1

Close to PIN11,40
PHY1_REG_OUT
Close to PIN21 R6831 0R
L6800 R0402 C6814 C6810 C6815

1
2.2uH C6811 C6812 C6813 4.7uF 100nF 100nF

2 1
1

1
IND_252012 4.7uF 100nF 100nF X5R X5R X5R
VCC3V3_PHY1 R6832 1 4.7K 2 R0201 5% R6833 1.8K VCCIO_PHY1 X5R X5R X5R 6.3V 10V 10V

2
DNP C6816 R0201 4V 10V 10V C0402 C0201 C0201
2

2
1

100nF C0201 C0201 C0201

GMAC1_RSTn_3V3 R6834 0R R0201 X5R
10V
Close to PIN30
2

PHYRSTB is 3.3V IO C0201 RTL8211F-CG(SW Mode)

RTL8211FI-CG(SW Mode)Industrial C6817 C6818

1
4.7uF 100nF

2 1
X5R X5R
C6821 C6819 C6820 6.3V 10V

2
1

1
PHY1_RXD0/RXDLY GMAC1_RXD0_M1 100nF 100nF 100nF C0402 C0201
PHY1_RXD1/TXDLY GMAC1_RXD1_M1 X5R X5R X5R
PHY1_RXD2/PLLOFF GMAC1_RXD2_M1 10V 10V 10V
A A
2

2
PHY1_RXD3/PHYAD0 GMAC1_RXD3_M1 C0201 C0201 C0201
Close to PIN29
PHY1_RXCLK/PHYAD1 R6839 22R R0201 GMAC1_RXCLK_M1
C6822
Close to PIN3,8,38
1

PHY1_RXDV/PHYAD2 R6840 22R R0201 GMAC1_RXDV_CRS_M1 100pF

C0G Rockchip Electronics Co., Ltd
50V
Close to PHY
2

C0201
DNP
Project: TB-RK3576D0
File: 68.Ethernet-GEPHY_RGMII1

Rockchip Confidential Date:

Designed by:
Monday, May 13, 2024

Jason Deng Reviewed by: Default

Rev:
Sheet:
V1.0
34 of 42
5 4 3 2 1
 5 4 3 2 1
Option1

16
Y6700 DNP J6700

RGMII0_M0 PHY0_XTALOUT 1 4

16
X1 GND
2 3 PHY0_XTALIN PHY0_MDI3- R6700 0R R0201 PHY0_MDI_3- 9
C6700 GND X2 C6701 PHY0_MDI3+ R6701 0R R0201 PHY0_MDI_3+ MDI3-
NC/18pF 25.000MHz NC/18pF 8
MDI3+

2 1

2 1
GMAC0_TXD0_M0 C0G C0G PHY0_MDI2- R6703 0R R0201 PHY0_MDI_2- 6
50V CRY4_2R00X1R60X0R55 50V PHY0_MDI2+ R6704 0R R0201 PHY0_MDI_2+ MDI2-
GMAC0_TXD1_M0
GMAC0_TXD2_M0 C0201 C0201 5
PHY0_MDI1- R6705 0R R0201 PHY0_MDI_1- 7 MDI2+
GMAC0_TXD3_M0 MDI1-
GMAC0_TXCTL_M0 PHY0_MDI1+ R6706 0R R0201 PHY0_MDI_1+
GMAC0_TXCLK_M0 4
MDI1+
Option2 PHY0_MDI0-
PHY0_MDI0+
R6707
R6708
0R
0R
R0201
R0201
PHY0_MDI_0-
PHY0_MDI_0+
3
MDI0-
D GMAC0_RXD0_M0 D
GMAC0_RXD1_M0 ETH_CLK0_25M_OUT_M0 R6709 0R R0201 PHY0_XTALIN 2
MDI0+
GMAC0_RXD2_M0 MAC -----> PHY C6702 10nF1 2X5R 25V C0201 1
TCT

1
GMAC0_RXD3_M0
GMAC0_RXCTL_M0 PHY0_CHASSIS_GND 10
PHY0_LED1/CFG_LDO0 11 Earth
GMAC0_RXCLK_M0 G+
R6711 510R R0201 12
G-
Option3 ED6700
ESDH0402WV05U
ED6702 ED6704 ED6706
ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U
VCC3V3_PHY0 R6712 510R R0201 14
Y+
ETH_CLK0_25M_OUT_M0 13
Y-

2
ED0402 ED0402 ED0402 ED0402 R6714 NC/510R

15
GMAC0_MDC_M0 DNP DNP DNP DNP R0201
GMAC0_MDIO_M0 ED6701 ED6703 ED6705 ED6707 PHY0_LED2/CFG_LDO1 R6715 510R R0201 SYT-320DNL Tab down

15
GMAC0_RSTn_3V3 ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U ESDH0402WV05U RJ45_HR911130C
ED0402 ED0402 ED0402 ED0402 C6704 R6716 NC/0R
DNP DNP DNP DNP NC/100pF R0201

2 1
C0G R6717 1M PHY0_CHASSIS_GND
50V R0603
C0201 C6705 2 1 1000pF 2KV
C1206
Reserve for EMI.
RK SOC clock
mode recommended RK631A clock mode selected PHY0_LED0/CFG_EXT RGMII Power Source CFG_EXT CFG_LDO[1:0] PHY0_LED2
R6718 NC/4.7K R6719 4.7K VCC3V3_PHY0
Clock R0201 R0201
RK3576 mode1,mode2 Option1 Option2 Option3 R6720 4.7K PHY0_LED2/CFG_LDO1 R6721 NC/4.7K External 3.3V (default) 1'b1 2'b00 String 510R to GND
mode R0201 R0201
R6722 4.7K PHY0_LED1/CFG_LDO0 External 1.8V 1'b1 2'b10 String 510R to VCC3V3_PHY
mode1 No Yes No R0201
Internal 1.8V 1'b0 2'b10 String 510R to VCC3V3_PHY
C
VCC_PHY0_IO Voltage Config C
mode2 Yes No No
R6723 NC/4.7K PHY0_RXD2/PLLOFF R6724 4.7K VCCIO_PHY0
mode3 Yes No Yes R0201 R0201
Pull-up to disable PLL @ ALDPS mode(Low power mode)
VDD10_PHY0 R6725 NC/4.7K PHY0_RXD0/RXDLY R6726 4.7K VCCIO_PHY0
R0201 R0201
PHY0_LED2/CFG_LDO1
PHY0_LED1/CFG_LDO0
PHY0_LED0/CFG_EXT

R6727 2.49K
1% R0201
Pull-up for additional 2ns delay to RXC for data latching
PHY0_XTALOUT
PHY0_XTALIN

VCC3V3_PHY0 VCCIO_1V8_S0 VCCIO_PHY0

R6728 4.7K PHY0_RXD1/TXDLY R6729 NC/4.7K
Close to PIN28
VCC3V3_PHY0 VCCIO_PHY0
R0201 R0201 R6730 NC/0R
RSET0

GMAC0_INT/PMEB R6731 4.7K R0402

R0201 C6706 C6707 C6708
Pull-up for additional 2ns delay to TXC for data latching VCC_3V3_S0
OD,pull up 3.3V 4.7uF 1uF 100nF

2 1

2 1

2 1
X5R X5R X5R
Connect to the GPIO in
41

40
39
38
37
36
35
34
33
32
31

U6700 R6732 NC/4.7K PHY0_RXD3/PHYAD0 R6734 4.7K VCCIO_PHY0 R6733 0R 6.3V 6.3V 6.3V
SOC 3.3V power domain. R0201 R0201 R0402 C0402 C0201 C0201
E_Pad

AVDD33
RSET
AVDD10
XTAL_OUT/EXT_CLKIN
XTAL_IN
CLKOUT
LED2/CFG_LDO1
LED1/CFG_LDO0
LED0/CFG_EXT
INTB/PMEB

R6735 4.7K PHY0_RXCLK/PHYAD1

R0201
R6736 4.7K PHY0_RXDV/PHYAD2
R0201 VCC_3V3_S0 VCC3V3_PHY0
PHY Address PHYAD[2:0]
Close to PIN11,40
PHY0_MDI0+ 1 30 PHY0_REG_OUT
PHY Address Config 1 (default) 3'b001 R6737 0R
PHY0_MDI0- 2 MDI[0]+ REG_OUT 29 R0402 C6709 C6710 c6711
B MDI[0]- DVDD33 VCC3V3_PHY0 B
VDD10_PHY0 3 28 VCCIO_PHY0 4.7uF 100nF 100nF
AVDD10 DVDD_RG

2 1

2 1

2 1
PHY0_MDI1+ 4 27 PHY0_RXCLK/PHYAD1 From system Power X5R X5R X5R
PHY0_MDI1- 5 MDI[1]+ RXC/PHYAD1 26 PHY0_RXDV/PHYAD2 VDD10_PHY0 6.3V 10V 10V
PHY0_MDI2+ 6 MDI[1]- RXCTL/PHYAD2 25 PHY0_RXD0/RXDLY C0402 C0201 C0201
PHY0_MDI2- 7 MDI[2]+ RXD0/RXDLY 24 PHY0_RXD1/TXDLY
8 MDI[2]- RXD1/TXDLY 23 PHY0_RXD2/PLLOFF PHY0_REG_OUT
VDD10_PHY0 AVDD10 RXD2/PLLOFF
PHY0_MDI3+ 9 22 PHY0_RXD3/PHYAD0 L6700 C6714 C6715 C6716 C6717
PHY0_MDI3- 10 MDI[3]+ RXD3/PHYAD0 21 2.2uH C6712 C6713 100nF 100nF 100nF 100nF
MDI[3]- DVDD10 VDD10_PHY0

2 1

2 1

2 1

2 1
1

IND_252012 4.7uF 100nF X5R X5R X5R X5R C6718 c6719

2 1
X5R X5R 6.3V 6.3V 6.3V 6.3V 4.7uF 100nF

2 1

2 1
4V 6.3V C0201 C0201 C0201 C0201 X5R X5R
2

C0201 C0201 6.3V 10V

PHYRSTB
AVDD33

C0402 C0201
TXCTL

Close to PIN30
MDIO
TXD3
TXD2
TXD1
TXD0
MDC

TXC

Close to PIN21 Close to PIN3,8,38

RK631A
Close to PIN29
11
12
13
14
15
16
17
18
19
20

QFN40_5R00X5R00X0R90_T
GMAC0_TXCTL_M0
GMAC0_TXCLK_M0
GMAC0_MDIO_M0
GMAC0_TXD3_M0
GMAC0_TXD2_M0
GMAC0_TXD1_M0
GMAC0_TXD0_M0
GMAC0_MDC_M0

VCC3V3_PHY0
PHY0_RSTn

PHYRSTB is 3.3V IO C6720 1 2 NC/3.0pF

C0G 25V C0201

GMAC0_RSTn_3V3 R6739 0R R0201 PHY0_RSTn

C6721 R6738 1.8K VCCIO_PHY0
100nF R0201
2 1

X5R
A Close to PIN12 6.3V
A

C0201

PHY0_RXD0/RXDLY GMAC0_RXD0_M0
PHY0_RXD1/TXDLY GMAC0_RXD1_M0 Rockchip Electronics Co., Ltd
PHY0_RXD2/PLLOFF GMAC0_RXD2_M0
PHY0_RXD3/PHYAD0 GMAC0_RXD3_M0
Project: TB-RK3576D0
Close to PHY PHY0_RXCLK/PHYAD1 R6744 22R R0201 GMAC0_RXCLK_M0
C6722 1 2 NC/10pF
C0G 25V C0201
File: 67.Ethernet-GEPHY_RGMII0
PHY0_RXDV/PHYAD2 R6745 22R R0201 GMAC0_RXCTL_M0 Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 35 of 49

5 4 3 2 1
 5 4 3 2 1

PCIe2.0 x1 RC Mode-EDGE
PCIE0_REFCLKP
PCIE0_REFCLKN
PCIE0_TXP PCIE0_PERSTn R8600 22R R0201 PCIE0_PERSTn_3V3_L
PCIE0_TXN
PCIE0_RXP PCIE0_WAKEn R8605 22R R0201 PCIE0_WAKEn_3V3_L
PCIE0_RXN
PCIE0_CLKREQn R8606 22R R0201 PCIE0_CLKREQn_3V3_L
PCIE0_CLKREQn
PCIE0_WAKEn
D PCIE0_PERSTn D

VCC3V3_PCIE J8600

VCC3V3_PCIE
1
C8605 C8606 C8607 3 C8610 GND14 2
22uF 22uF 100nF 5 100nF GND13 3.3V1 4
PERn3 3.3V2
2 1

2 1

2 1

2 1

X5R X5R X5R 7 X5R 6

6.3V 6.3V 10V 9 10V PERp3 NC1 8
C0603 C0603 C0201 11 C0201 GND12 NC2 10
13 PETn3 DAS/DSS# 12
PETp3 3.3V3
Note: 15
GND11 3.3V4
14
17 16
PERn2 3.3V5
The supply power needs to 19
PERp2 3.3V6
18
21 20
meet the current demand 23 GND10 NC3 22
25 PETn2 NC4 24
27 PETp2 NC5 26
29 GND9 NC6 28
31 PERn1 NC7 30
33 PERp1 NC8 32
35 GND8 NC9 34
37 PETn1 NC10 36
39 PETp1 NC11 38
PCIE0_RXN 41 GND7 DEVSLP 40
C PCIE0_RXP 43 PERn0/SATA-B+ NC12 42 C
45 PERp0/SATA-B- NC13 44
PCIE0_TXN X5R C0201 C8621 1 2 220nF 10VPCIE0_RC_TXN 47 GND6 NC14 46
PCIE0_TXP X5R C0201 C8622 1 2 220nF 10VPCIE0_RC_TXP 49 PERn0/SATA-A- NC15 48
51 PERp0/SATA-A+ NC16 50 PCIE0_PERSTn_3V3_L
PCIE0_REFCLKN R8601 0R R0201 PCIE0_CLKN_CON 53 GND5 PERST# 52 PCIE0_CLKREQn_3V3_L
PCIE0_REFCLKP R8602 0R R0201 PCIE0_CLKP_CON 55 REFCLKN CLKREQ# 54 PCIE0_WAKEn_3V3_L
57 REFCLKP PEWake# 56
GND4 NC17 58
NC18
PCIE M.2 NGFF
M-KEY SOCKET VCC3V3_PCIE
67 68
69 NC19 SUSCLK 70
71 PEDET 3.3V7 72
73 GND3 3.3V8 74
75 GND2 3.3V9
GND1
GND16

GND15

M-KEY
77

76

B B

VCC3V3_PCIE
PCIE30_PWREN_H

VCC5V0_SYS_S5 VCC3V3_PCIE

4.5V<VIN<18V 5
U8205
6 L8020
Default 3.31V
C8040 C8041 VIN LX 6.8uH
1

10uF 100nF 2 1 C8043 1 2 X5R IND_505020 C8044 C8045 C8046 C8047

GND BS
1

X5R X5R R8041 100nF 25V C0201 22pF R8042 22uF 22uF 100nF
10V 10V NC/10K 4 3 C0G 150K C0603 C0603 X5R
EN FB/OUT
2

C0603 C0201 R0201 50V 1% X5R X5R 10V

2

TCS4513D C0201 R0201 10V 10V C0201

PCIE30_PWREN_H R8040 10K SOT_23_6 DNP
R0201 FB=0.6V
A A
R8043
EN > 1.3V 33.2K
TCS4513C 1%
R0201
Vout=0.6*(R1/R2+1)=0.6*(150K/33.2K+1)=0.6*5.518=3.31V
Rockchip Electronics Co., Ltd
Project: TB-RK3576D0
File: 86.PCIE2.0 x 1Lanes
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Default Sheet: 38 of 42

5 4 3 2 1
 5 4 3 2 1

Extboard Debug Port

D D

J9100
VCC_3V3_S3 P101-2x20SGF01 VCC5V0_SYS_S5
CNN40M_2R54_V_DIP
1 2
GPIO4_B4/I2C3_SDA_M0 3 4
GPIO4_B5/I2C3_SCL_M0 5 6
GPIO4_B0 7 8 GPIO3_C6/UART8_TX_M0
9 10 GPIO3_C5/UART8_RX_M0
GPIO4_B1 11 12 GPIO4_A2
GPIO4_B2 13 14
GPIO4_B3 15 16 GPIO4_A5
VCC_3V3_S3 17 18 GPIO4_A6
19 20
SPI0_MOSI_M0/GPIO0_D0
C
SPI0_MISO_M0/GPIO0_D1 21 22 GPIO4_A7 C
SPI0_CLK_M0/GPIO0_C7 23 24 SPI0_CS0_M0/GPIO0_C6
25 26
SPI0_CS1_M0/GPIO0_C3
27 28 GPIO4_A3/I2C2_SCL_M2
GPIO4_A4/I2C2_SDA_M2
GPIO3_D4 29 30
GPIO3_D5 31 32 GPIO3_D0
GPIO3_D6 33 34
GPIO3_D7 35 36 GPIO3_C7
UART0_TX_M0_DEBUG R9100 22R R0201 TX_DEBUG 37 38 GPIO3_C4
1

39 40 RX_DEBUGR9101 22R R0201 UART0_RX_M0_DEBUG

1
D9100 D9101
ESDH0402WV05U 不带防护墙 ESDH0402WV05U
ED0402 ED0402
2

B B

Debug UART 考虑单独的3pin接口

UART2_M0(pin37,pin40,Default UART Debug )

A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 91.EXT INTERFACE & Debug UART
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Default Sheet: 40 of 42

5 4 3 2 1
 5 4 3 2 1

KEY
SW9000
SARADC_VIN1_KEY/RECOVERY TS1010GS-C
PWRON_L R9000 100R R0201 1 4
1 4

1
PWRON_L 2 5
ED9000 3 2 5 6
D D1006WV05C150BT 3 H1 7 D
ED0402 H2

2
默认星坤TS1010GS-C，layout封装兼容杰之盟TS1030
SW9001

SARADC_VIN1_KEY/RECOVERY R9001 100R R0201 2 1

2 1

1
ED9001
D1006WV05C150BT TS-3220S
ED0402 TS-3220S

2
C C

FAN 3PIN Interface

VCC5V0_SYS_S5
4

GND
1 CON9000
2 1 CN3M_1R25_H_SMT
3 2 CN3MR_1R25_H_SMT
PWM1_CH4_M0/GPIO0_B7 3
GND
5

B B

A A

Rockchip Electronics Co., Ltd

Note: Project: TB-RK3576D0
If BOOT_SARADC_IN0=0V after power-on reset,
then system will enter into Maskrom mode. File: 90.Key/Connecter
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 43 of 50

5 4 3 2 1
 5 4 3 2 1

SARADC_VIN2_HW_ID

UART0_TX_M0_DEBUG
HW_ID
UART0_RX_M0_DEBUG
Config Table for SARADC_VIN2_HW_ID

Item Rup Rdown ADC Value VERSION

D D
VCCA_1V8_S0 HW_ID1 DNP 10K 0 RESERVE

HW_ID2 100K 11.3K 416 RESERVE

R9600
NC HW_ID3 100K 24.9K 816 RESERVE
R0201
HW_ID4 100K 43K 1231 RESERVE
SARADC_VIN2_HW_ID
HW_ID5 100K 68K 1658 RESERVE

R9601 HW_ID6 100K 100K 2048 RESERVE

10K
5% HW_ID7 68K 100K 2438 RESERVE
R0201
HW_ID8 43K 100K 2864 RESERVE

HW_ID9 24.9K 100K 3279 RESERVE

HW_ID10 11.3K 100K 3679 RESERVE

C C
HW_ID11 10K DNP 4095 RESERVE

B B

A A

Rockchip Electronics Co., Ltd

Project: TB-RK3576D0
File: 96.HW_ID
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 47 of 50

5 4 3 2 1
 5 4 3 2 1

D D

C C

Hole

B B

Mark TOP Mark BOTTOM Mark

M9900 M9901 M9902 M9903 M9904 M9905

MARK MARK MARK MARK MARK MARK
MARK MARK MARK MARK MARK MARK

A A
Mark考虑放到拼版工艺边上 Rockchip Electronics Co., Ltd
Project: TB-RK3576D0
File: 99.Mark/Hole
Date: Monday, May 13, 2024 Rev: V1.0

Designed by: Jason Deng Reviewed by: Sheet: 50 of 50

5 4 3 2 1