a Dual Very Low Noise Precision

Operational Amplifier
OP270
FEATURES CONNECTION DIAGRAMS
Very Low Noise 5 nV/÷ ÷ Hz @ 1 kHz Max
16-Lead SOIC 8-Lead PDIP (P-Suffix)
Excellent Input Offset Voltage 75 ␮V Max
Low Offset Voltage Drift 1 ␮V/ⴗC Max (S-Suffix) 8-Lead CERDIP
Very High Gain 1500 V/mV Min (Z-Suffix)
–IN A 1 16 OUT A
Outstanding CMR 106 dB Min
Slew Rate 2.4 V/␮s Typ +IN A 2 15 NC

Gain Bandwidth Product 5 MHz Typ NC 3 14 NC OUT A 1 8 V+

Industry-Standard 8-Lead Dual Pinout V– 4 OP270 13 V+ –IN A 2 A B 7 OUT B

NC 5 12 NC +IN A 3 6 –IN B
GENERAL DESCRIPTION +IN B 6 11 NC V– 4 OP270 5 +IN B
The OP270 is a high performance, monolithic, dual operational –IN B 7 10 OUT B
amplifier with exceptionally low voltage noise, 5 nV/÷Hz max at NC 8 9 NC
1 kHz. It offers comparable performance to ADI’s industry
standard OP27. NC = NO CONNECT

The OP270 features an input offset voltage below 75 mV and an

offset drift under 1 mV/∞C, guaranteed over the full military tem-
perature range. Open-loop gain of the OP270 is over 1,500,000 The OP270 offers excellent amplifier matching, which is important
into a 10 kW load, ensuring excellent gain accuracy and linearity, for applications such as multiple gain blocks, low noise instru-
even in high gain applications. Input bias current is under 20 nA, mentation amplifiers, dual buffers, and low noise active filters.
which reduces errors due to signal source resistance. The OP270’s
CMR of over 106 dB and PSRR of less than 3.2 mV/V signifi- The OP270 conforms to the industry-standard 8-lead DIP pinout.
cantly reduce errors due to ground noise and power supply It is pin compatible with the MC1458, SE5532/A, RM4558, and
fluctuations. Power consumption of the dual OP270 is one-third HA5102 dual op amps, and can be used to upgrade systems
less than two OP27s, a significant advantage for power conscious using those devices.
applications. The OP270 is unity-gain stable with a gain bandwidth For higher speed applications, the OP271, with a slew rate of
product of 5 MHz and a slew rate of 2.4 V/ms. 8 V/ms, is recommended. For a quad op amp, see the OP470.

SIMPLIFIED SCHEMATIC
(One of Two Amplifiers Is Shown)
V+

BIAS

OUT

–IN +IN

V–

REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
OP270–SPECIFICATIONS (V S = ⴞ15 V, TA = 25ⴗC, unless otherwise noted.)
OP270E OP270F OP270G
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT
Input Offset Voltage VOS 10 75 20 150 50 250 mV
Input Offset Current lOS VCM = 0 V 1 10 3 15 5 20 nA
Input Bias Current IB VCM = 0 V 5 20 10 40 15 60 nA
Input Noise Voltage en p-p 0.1 Hz to 10 Hz 80 200 80 200 80 nV p-p
(Note 1)
Input Noise fO = 10 Hz 3.6 6.5 3.6 6.5 3.6 ÷Hz
nV/÷
Voltage Density fO = 100 Hz 3.2 5.5 3.2 5.5 3.2 ÷Hz
nV/÷
en fO = 1 kHz 3.2 5.0 3.2 5.0 3.2 ÷Hz
nV/÷
(Note 2)
Input Noise fO = 10 Hz 1.1 1.1 1.1 ÷Hz
pA/÷
Current Density in fO = 100 Hz 0.7 0.7 0.7 ÷Hz
pA/÷
fO = 1 kHz 0.6 0.6 0.6 ÷Hz
pA/÷
Large-Signal VO = ± 10 V
Voltage Gain AVO RL = 10 kW 1500 2300 1000 1700 750 1500 V/mV
RL = 2 kW 750 1200 500 900 350 700 V/mV
Input Voltage Range IVR (Note3) ± 12 ± 12.5 ± 12 ± 12.5 ± 12 ± 12.5 V
Output Voltage Swing VO RL ≥ 2 kW ± 12 ± 13.5 ± 12 ± 13.5 ± 12 ± 13.5 V
Common-Mode
Rejection CMR VCM = ± 11 V 106 125 100 120 90 110 dB
Power Supply
Rejection Ratio PSRR VS = ± 4.5 V 0.56 3.2 1.0 5.6 1.5 6 mV/V
to ± 18 V
Slew Rate SR 1.7 2.4 1.7 2.4 1.7 2.4 V/ms
Supply Current ISY No Load 4 6.5 4 6.5 4 6.5 mA
(All Amplifiers)
Gain Bandwidth GBP 5 5 5 MHz
Product
Channel Separation CS VO = ± 20 V p-p
fO = 10 Hz 125 175 125 175 175 dB
(Note 1)
Input Capacitance CIN 3 3 3 pF
Input Resistance RIN 0.4 0.4 0.4 MW
Differential-Mode
Input Resistance RINCM 20 20 20 GW
Common-Mode
Settling Time tS AV = +1, 10 V 5 5 5 ms
Step to 0.01%
NOTES
1. Guaranteed but not 100% tested.
2. Sample tested.
3. Guaranteed by CMR test.
Specifications subject to change without notice.

–2– REV. C
 OP270
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (Vs = ⴞ15 V, –40∞C £ TA £ 85ⴗC, unless otherwise noted.)
OP270E OP270F OP270G
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT
Input Offset Voltage VOS 25 150 45 275 100 400 mV
Average Input
Offset Voltage Drift TCVOS 0.2 1 0.4 2 0.7 3 mV/∞C
Input Offset Current IOS VCM = 0 V 1.5 30 5 40 15 50 nA
Input Bias Voltage IB VCM = 0 V 6 60 15 70 19 80 nA
Large-Signal VO = ± 10 V
Voltage Gain AVO RL = 10 kW 1000 1800 600 1400 400 1250 V/mV
RL = 2 kW 500 900 300 700 225 670 V/mV
Input Voltage Range* IVR ± 12 ± 12.5 ± 12 ± 12.5 ± 12 ± 12.5 V
Output Voltage Swing VO RL ≥ 2 kW ± 12 ± 13.5 ± 12 ± 13.5 ± 12 ± 13.5 V
Common-Mode
Rejection CMR VCM = ± 11 V 100 120 94 115 90 100 dB
Power Supply
Rejection Ratio PSRR VS = ± 4.5 V 0.7 5.6 1.8 10 2.0 1.5 mV/V
to ± 18 V
Supply Current ISY No Load 4.4 7.2 4.4 7.2 4.4 7.2 mA
(All Amplifiers)
* Guaranteed by CMR test.
Specifications subject to change without notice.

REV. C –3–
OP270
ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature Range
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V OP270E, OP270F, OP270G . . . . . . . . . . . –40°C to +85°C
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ± 1.0 V NOTES
1
Differential Input Current2 . . . . . . . . . . . . . . . . . . . . ± 25 mA Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage device at these or any other conditions above those listed in the operational
Output Short-Circuit Duration . . . . . . . . . . . . . . . Continuous sections of this specification is not implied. Exposure to absolute maximum rating
Storage Temperature Range conditions for extended periods may affect device reliability.
2
P, S, Z Package . . . . . . . . . . . . . . . . . . . . –65°C to +150°C The OP270’s inputs are protected by back-to-back diodes. Current limiting
resistors are not used, in order to achieve low noise performance. If differential
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C voltage exceeds +10 V, the input current should be limited to ± 25 mA.
Junction Temperature (TJ) . . . . . . . . . . . . . –65°C to +150°C

ORDERING GUIDE
TA = +25°C
VOS Max θ JC θ JA* Temperature Package Package
Model (␮V) (°C/W) (°C/W) Range Description Option
OP270EZ 75 12 134 XIND 8-Lead CERDIP Q-8 (Z-Suffix)
OP270FZ 150 12 134 XIND 8-Lead CERDIP Q-8 (Z-Suffix)
OP270GP 250 37 96 XIND 8-Lead PDIP N-8 (P-Suffix)
OP270GS 250 27 92 XIND 16-Lead SOIC RW-16 (S-Suffix)
*θJA is specified for worst-case mounting conditions, i.e., θJA is specified for device
in socket for CERDIP and PDIP packages; θJA is specified for device soldered to
printed circuit board for SOIC package.

For military processed devices, please refer to the Standard

Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp.
SMD Part Number ADI Equivalent
5962-8872101PA OP270AZMDA

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the OP270 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

–4– REV. C
 Typical Performance Characteristics– OP270
10 5 0.1Hz TO 10Hz NOISE
9 TA = 25ⴗC TA = 25ⴗC
8 VS = ⴞ15V
7

NOISE VOLTAGE (100nV/DIV)

6

VOLTAGE NOISE (nV/ Hz)

VOLTAGE NOISE (nV/ Hz)

4
5
AT 10Hz
4

3 AT 1kHz
3

1/f CORNER = 5Hz

2
2

1 1
1 10 100 1k 0 ⴞ5 ⴞ10 ⴞ15 ⴞ20 TA = 25ⴗC TIME (1sec/DIV)
FREQUENCY (Hz) SUPPLY VOLTAGE (V) VS = ⴞ15V

TPC 1. Voltage Noise Density TPC 2. Voltage Noise Density TPC 3. 0.1 Hz to 10 Hz Input
vs. Frequency vs. Supply Voltage Voltage Noise

10 40 5
TA = 25ⴗC
VS = ⴞ15V TA = 25ⴗC
VS = ⴞ15V

CHANGE IN OFFSET VOLTAGE (␮A)

30 VS = ⴞ15V
4
CURRENT NOISE (pA/ Hz)

VOLTAGE NOISE (nV/ Hz)

20

3
10
1.0
0
2

1/f CORNER = 200Hz –10

1
–20

0.1 –30 0
10 100 1k 10k –75 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5
FREQUENCY (Hz) TEMPERATURE (ⴗC) TIME (Minutes)

TPC 4. Current Noise Density TPC 5. Input Offset Voltage vs. TPC 6. Warm-Up Offset Voltage
vs. Frequency Temperature Drift

7 5 7
VS = ⴞ15V VS = ⴞ15V TA = 25ⴗC
VCM = 0V VCM = 0V VS = ⴞ15V
INPUT OFFSET CURRENT (nA)

6 4 6
INPUT BIAS CURRENT (nA)

INPUT BIAS CURRENT (nA)

5 3 5

4 2 4

3 1 3

2 0 2
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 –10.0 –5.0 0.0 5.0 10.0
–12.5 –7.5 –2.5 2.5 7.5 12.5
TEMPERATURE (ⴗC) TEMPERATURE (ⴗC)
COMMON-MODE VOLTAGE (V)

TPC 7. Input Bias Current vs. TPC 8. Input Offset Current vs. TPC 9. Input Bias Current vs.
Temperature Temperature Common-Mode Voltage

REV. C –5–
OP270
130 6 8
TA = 25ⴗC
120 VS = ⴞ15V
VS = ⴞ15V 7

TOTAL SUPPLY CURRENT (mA)

TOTAL SUPPLY CURRENT (mA)
110
100 5 6
90
5
CMR (dB)

80
70 4 4
+125ⴗC
60
+25ⴗC 3
50
–55ⴗC
40 3 2
30
1
20
10 2 0
1 10 100 1k 10k 100k 1M 0 ⴞ5 ⴞ10 ⴞ15 ⴞ20 –75 –50 –25 0 25 50 75 100 125
FREQUENCY (Hz) SUPPLY VOLTAGE (V) TEMPERATURE (ⴗC)

TPC 10. CMR vs. Frequency TPC 11. Total Supply Current TPC 12. Total Supply Current
vs. Supply Voltage vs. Temperature

140 140 80
TA = 25ⴗC TA = 25ⴗC TA = 25ⴗC
120 120 VS = ⴞ15V VS = ⴞ15V
60

CLOSED-LOOP GAIN (dB)

100 100
VOLTAGE GAIN (dB)

40
PSR (dB)

80 80
–PSR

60 60
20
+PSR
40 40
0
20 20

0 0 –20
1 10 100 1k 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)

TPC 13. PSR vs. Frequency TPC 14. Open-Loop Gain vs. TPC 15. Closed-Loop Gain vs.
Frequency Frequency

25 80 5000 80
TA = 25ⴗC
VS = ⴞ15V
PHASE SHIFT (Degrees)

GAIN BANDWIDTH PRODUCT (MHz)

20 100
PHASE
4000
PHASE MARGIN (Degrees)
OPEN-LOOP GAIN (V/mV)

70
15 120 7
GAIN (dB)

10 140 3000
PHASE 60 ⌽
GAIN 6
5 MARGIN = 62ⴗ 160
2000

0 180 5
50 GBP
1000
–5
4

–10 0 40
1 2 3 4 5 6 7 8 9 10 0 ⴞ5 ⴞ10 ⴞ15 ⴞ20 ⴞ25 –75 –50 –25 0 25 50 75 100 125 150
FREQUENCY (Hz) SUPPLY VOLTAGE (V) TEMPERATURE (ⴗC)

TPC 16. Open-Loop Gain Phase TPC 17. Open-Loop Gain vs. TPC 18. Gain-Bandwidth Phase
Shift vs. Frequency Supply Voltage Margin vs. Temperature

–6– REV. C
 OP270
28 15 50
TA = 25ⴗC TA = 25ⴗC POSITIVE TA = 25ⴗC
VS = ⴞ15V 14 VS = ⴞ15V SWING VS = ⴞ15V
24 THD = 1% VIN = 100mV
PEAK-TO-PEAK AMPLITUDE (V)

13 40 AV = +1

MAXIMUM OUTPUT ( V)
20 12

OVERSHOOT (%)
11 NEGATIVE 30
16
SWING
10
12
9 20

8 8

7 10
4
6

0 5 0
1k 10k 100k 1M 10M 1k 10k 100k 0 200 400 600 800 1000
FREQUENCY (Hz) LOAD RESISTANCE (⍀) CAPACITIVE LOAD (pF)

TPC 19. Maximum Output TPC 20. Maximum Output TPC 21. Small-Signal Overshoot
Swing vs. Frequency Voltage vs. Load Resistance vs. Capacitive Load

100 2.8 190

TA = +25ⴗC VS = ⴞ15V
VS = ⴞ15V 180
2.7 170

CHANNEL SEPARATION (dB)

AV = 1
OUTPUT IMPEDANCE (⍀)

75 160
SLEW RATE (V/␮s)

2.6 150
140
50 2.5 130
AV = 10 –SR 120
AV = 100 2.4 110
25 +SR 100
2.3 90
TA = 25ⴗC
80 VS = ⴞ15V
VO = 20V p-p TO 10kHz
0 2.2 70
1k 10k 100k 1M 10M –75 –50 –25 0 25 50 75 100 125 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz) TEMPERATURE (ⴗC) FREQUENCY (Hz)

TPC 22. Output Impedance vs. TPC 23. Slew Rate vs. TPC 24. Channel Separation vs.
Frequency Temperature Frequency

0.1
TA = 25ⴗC
VS = ⴞ15V
VO = 20V p-p
RL =2k⍀

AV = 10
DISTORTION (%)

0.01

AV = 1

5V 20␮s 50mV 200nS

0.001 TA = 25ⴗC TA = 25ⴗC

10 100 1k 10k VS = ⴞ15V VS = ⴞ15V
FREQUENCY (Hz) AV = +1 AV = +1
RL = 2k⍀ RL = 2k⍀

TPC 25. Total Harmonic Distor- TPC 26. Large Signal Transcient TPC 27. Small-Signal
tion vs. Frequency Response Transient Response

REV. C –7–
OP270
5k⍀
TOTAL NOISE AND SOURCE RESISTANCE
The total noise of an op amp can be calculated by:
500⍀

(en ) + (in RS ) + (et )

1/2 V1 20Vp-p 2 2 2
OP270 En =

where:
5k⍀ En = total input referred noise
en = op amp voltage noise
50⍀
in = op amp current noise
1/2 V2
OP270
V et = source resistance thermal noise
CHANNEL SEPARATION = 20 log 1
V /1000 RS = source resistance
2

The total noise is referred to the input and at the output would
Figure 1. Channel Separation Test Circuit
be amplified by the circuit gain.
+18V
Figure 3 shows the relationship between total noise at 1 kHz
and source resistance. For RS < 1 kW the total noise is dominated
8 by the voltage noise of the OP270. As RS rises above 1 kW, total
100k⍀ noise increases and is dominated by resistor noise rather than by
2
the voltage or current noise of the OP270. When RS exceeds
1/2 1 20 kW, current noise of the OP270 becomes the major contributor
3
OP270 to total noise.
200k⍀
100

6
1/2 7
OP270
TOTAL NOISE (nV/ Hz)

100k⍀
OP200

10
4

–18V OP270

Figure 2. Burn-In Circuit RESISTOR

NOISE ONLY
1
APPLICATIONS INFORMATION 100 1k 10k 100k
VOLTAGE AND CURRENT NOISE RS – SOURCE RESISTANCE (⍀)
The OP270 is a very low noise dual op amp, exhibiting atypical
÷Hz @ 1 kHz. The exceptionally Figure 3. Total Noise vs. Source Resistance
voltage noise of only 3.2 nV/÷
(Including Resistor Noise) at 1 kHz
low noise characteristic of the OP270 is achieved in part by
operating the input transistors at high collector currents since
the voltage noise is inversely proportional to the square root of Figure 4 also shows the relationship between total noise and
the collector current. Current noise, however, is directly propor- source resistance, but at 10 Hz. Total noise increases more
tional to the square root of the collector current. As a result, the quickly than shown in Figure 3 because current noise is inversely
outstanding voltage noise performance of the OP270 is gained proportional to the square root of frequency. In Figure 4, current
at the expense of current noise performance, which is normal for noise of the OP270 dominates the total noise when RS > 5 kW.
low noise amplifiers.
Figures 3 and 4 show that to reduce total noise, source resistance
To obtain the best noise performance in a circuit, it is vital to must be kept to a minimum. In applications with a high source
understand the relationship between voltage noise (en), current resistance, the OP200, with lower current noise than the OP270,
noise (in), and resistor noise (et). will provide lower total noise.

–8– REV. C
 OP270
100 Figure 5 shows peak-to-peak noise versus source resistance over the
0.1 Hz to 10 Hz range. Once again, at low values of RS, the voltage
noise of the OP270 is the major contributor to peak-to-peak
noise, with current noise the major contributor as RS increases.
TOTAL NOISE (nV/ Hz)

The crossover point between the OP270 and the OP200 for
peak-to-peak noise is at RS = 17 kW.
10 OP200 The OP271 is a higher speed version of the OP270, with a slew
rate of 8 V/ms. Noise of the OP271 is slightly higher than that of
OP270 the OP270. Like the OP270, the OP271 is unity-gain stable.
For reference, typical source resistances of some signal sources
are listed in Table I.
RESISTOR
NOISE ONLY
1 Table I.
100 1k 10k 100k
RS – SOURCE RESISTANCE (⍀) Source
Figure 4. Total Noise vs. Source Resistance Device Impedance Comments
(Including Resistor Noise) at 10 Hz Strain gage <500 W Typically used in low
frequency applications.
1000 Magnetic <1500 W Low IB very important to reduce
tapehead, self-magnetization problems
OP200
microphone when direct coupling is used.
OP270 IB can be neglected.
PEAK-TO-PEAK NOISE (nV)

Magnetic <1500 W Similar need for low IB in

phonograph direct coupled applications.
100 cartridge OP270 will not introduce any
self-magnetization problem.
OP270 Linear variable <1500 W Used in rugged servo-feedback
RESISTOR differential applications. Bandwidth of
NOISE ONLY transformer interest is 400 Hz to 5 kHz.

10
100 1k 10k 100k
RS – SOURCE RESISTANCE (⍀)

Figure 5. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs.

Source Resistance (Includes Resistor Noise)

R3
1.24k⍀
R1
5⍀
–
OP270 C1
R2 + 2␮F
DUT C4
5⍀ OP27E
+ 0.22␮F
R6 D1, D2
– 600⍀ 1N4148
R5 + R10 R11
909⍀ 65.4k⍀ 65.4k⍀
OP27E + R14
R4 C3 4.99k⍀
OP42E eOUT
200⍀ – R9 0.22␮F
306k⍀ C5
– R13 1␮F
5.9k⍀
R8
10k⍀ R12
C2 10k⍀ GAIN = 50,000
0.032␮F VS = ⴞ15V

Figure 6. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)

REV. C –9–
OP270
NOISE MEASUREMENTS Noise Measurement — Noise Voltage Density
Peak-to-Peak Voltage Noise The circuit of Figure 8 shows a quick and reliable method of
The circuit of Figure 6 is a test setup for measuring peak-to-peak measuring the noise voltage density of dual op amps. The first
voltage noise. To measure the 200 nV peak-to-peak noise specifica- amplifier is in unity-gain, with the final amplifier in a noninverting
tion of the OP270 in the 0.1 Hz to 10 Hz range, the following gain of 101. As noise voltages of each amplifier are uncorrelated,
precautions must be observed: they add in rms fashion to yield:
1. The device has to be warmed up for at least five minutes. As Ê ˆ
(enA ) + (enB )
2 2
shown in the warm-up drift curve, the offset voltage typically eOUT = 101Á ˜
Ë ¯
changes 2 mV due to increasing chip temperature after power-up.
In the 10-second measurement interval, these temperature The OP270 is a monolithic device with two identical amplifi-
induced effects can exceed tens of nanovolts. ers. The noise voltage density of each individual amplifier will
2. For similar reasons, the device has to be well shielded from match, giving:
air currents. Shielding also minimizes thermocouple effects.
3. Sudden motion in the vicinity of the device can also “feed
through” to increase the observed noise.
Ê
Ë
2ˆ
eOUT = 101Á 2en ˜ = 101 2en
¯ ( )
4. The test time to measure noise of 0.1 Hz to 10 Hz should not R1 R2
exceed 10 seconds. As shown in the noise-tester frequency 100⍀ 10k⍀
response curve of Figure 7, the 0.1 Hz corner is defined by
only one pole. The test time of 10 seconds acts as an additional –
pole to eliminate noise contribution from the frequency band –
1/2 eOUT
OP270
below 0.1 Hz. 1/2 +
OP270 TO SPECTRUM ANALYZER
+ eOUT (nV/ Hz) =苲 101 ( 2en)
100
VS = 15V

80 Figure 8. Noise Voltage Density Test Circuit

R3
1.24k⍀
60
GAIN (dB)

R1 R2
5⍀ 100k⍀
–
OP270 –
40 DUT
+ OP27E enOUT
TO SPECTRUM ANALYZER
+
20
R5
R4 8.06k⍀ GAIN = 10,000
200⍀ VS = ⴞ15V
0
0.01 0.1 1.0 10 100
FREQUENCY (Hz)
Figure 9. Current Noise Density Test Circuit
Figure 7. 0.1 Hz to 10 Hz Peak-to-Peak Voltage
Noise Measurement — Current Noise Density
Noise Test Circuit Frequency Response
The test circuit shown in Figure 9 can be used to measure cur-
5. A noise-voltage-density test is recommended when measuring rent noise density. The formula relating the voltage output to
noise on a large number of units. A 10 Hz noise-voltage-density current noise density is:
measurement will correlate well with a 0.1 Hz to 10 Hz

( )
peak-to-peak noise reading, since both results are determined by 2
Ê enOUT ˆ 2
the white noise and the location of the 1/f corner frequency. Á G ˜ - 40 nV / Hz
Ë ¯
6. Power should be supplied to the test circuit by well bypassed in =
RS
low noise supplies, e.g., batteries. They will minimize output
noise introduced via the amplifier supply pins. where:

G = gain of 10,000
RS = 100 kW source resistance

–10– REV. C
 OP270
CAPACITIVE LOAD DRIVING AND POWER SUPPLY APPLICATIONS
CONSIDERATIONS Low Phase Error Amplifier
The OP270 is unity-gain stable and capable of driving large The simple amplifier depicted in Figure 12 utilizes a monolithic
capacitive loads without oscillating. Nonetheless, good supply dual operational amplifier and a few resistors to substantially
bypassing is highly recommended. Proper supply bypassing reduce phase error compared to conventional amplifier designs.
reduces problems caused by supply line noise and improves the At a given gain, the frequency range for a specified phase accuracy is
capacitive load driving capability of the OP270. over a decade greater than for a standard single op amp amplifier.
In the standard feedback amplifier, the op amp’s output resis- The low phase error amplifier performs second-order frequency
tance combines with the load capacitance to form a low-pass compensation through the response of op amp A2 in the feed-
filter that adds phase shift in the feedback network and reduces back loop of A1. Both op amps must be extremely well matched
stability. A simple circuit to eliminate this effect is shown in in frequency response. At low frequencies, the A1 feedback
Figure 10. The added components, C1 and R3, decouple the loop forces V2 /(K1 + 1) = VIN. The A2 feedback loop forces
amplifier from the load capacitance and provide additional Vo/(K1 + 1) = V2 /(K1 + 1), yielding an overall transfer function
stability. The values of C1 and R3 shown in Figure 10 are for a of VO /VIN = K1 + 1. The dc gain is determined by the resistor
load capacitance of up to 1,000 pF when used with the OP270. divider at the output, VO, and is not directly affected by the resis-
tor divider around A2. Note that like a conventional single op amp
V+
amplifier, the dc gain is set by resistor ratios only. Minimum
gain for the low phase error amplifier is 10.
C3 + C2
R2 R2 = R1
0.1␮F 10␮F
R2
R2 K1
–
C1
R1 200pF 1/2
VIN – R3 OP270E
50⍀ A2 V2
OP270 VOUT
+
+ C1
1000pF

C5 C4 –
0.1␮F R1
+ 10␮F 1/2 R2 K1
OP270E
PLACE SUPPLY DECOUPLING A1
V– CAPACITOR AT OP270 VIN +
VO
Figure 10. Driving Large Capacitive Loads
ASSUME A1 AND A1 ARE MATCHED. VO = (K1 + 1) V IN
␻
AO(s) = T
UNITY-GAIN BUFFER APPLICATIONS s
When Rf £ 100 W and the input is driven with a fast, large
Figure 12. Low Phase Error Amplifier
signal pulse (>1 V), the output waveform will look like the one
in Figure 11.
Figure 13 compares the phase error performance of the low
During the fast feedthrough-like portion of the output, the input phase error amplifier with a conventional single op amp ampli-
protection diodes effectively short the output to the input, and a fier and a cascaded two-stage amplifier. The low phase error
current, limited only by the output short-circuit protection, will be amplifier shows a much lower phase error, particularly for fre-
drawn by the signal generator. With Rf ≥ 500 W, the output is quencies where w/bwT < 0.1. For example, phase error of –0.1∞
capable of handling the current requirements (IL £ 20 mA at 10 V); occurs at 0.002 w/bwT for the single op amp amplifier, but at
the amplifier will stay in its active mode and a smooth transition 0.11 w/bwT for the low phase error amplifier.
will occur.
When Rf > 3 kW, a pole created by Rf and the amplifier’s input
capacitance (3 pF) creates additional phase shift and reduces
phase margin. A small capacitor (20 pF to 50 pF) in parallel
with Rf helps eliminate this problem.

Figure 11. Pulsed Operation

REV. C –11–
OP270
0 FIVE-BAND LOW NOISE STEREO GRAPHIC EQUALIZER
The graphic equalizer circuit shown in Figure 14 provides 15 dB of
–1
SINGLE OP AMP.
boost or cut over a 5-band range. Signal-to-noise ratio over a 20 kHz
CONVENTIONAL DESIGN bandwidth is better than 100 dB and referred to a 3 V rms input.
PHASE SHIFT (Degrees)

–2
Larger inductors can be replaced by active inductors, but this
–3
reduces the signal-to-noise ratio.
CASCADED
(TWO STAGES) DIGITAL PANNING CONTROL
–4 Figure 15 uses a DAC8221, a dual 12-bit CMOS DAC, to pan
a signal between two channels. One channel is formed by the
–5 current output of DAC A driving one-half of an OP270 in a
LOW PHASE ERROR
AMPLIFIER current-to-voltage converter configuration. The other channel is
–6
formed by the complementary output current of DAC A, which
normally flows to ground through the AGND pin. This comple-
–7
0.001
0.005
0.01
0.05
0.1
0.5
1.0 mentary current is converted to a voltage by the other half of the
FREQUENCY RATIO (1/␤␻)(␻/␻T) OP-270, which also holds AGND at virtual ground.

Figure 13. Phase Error Comparison Gain error due to mismatching between the internal DAC ladder
resistors and the current-to-voltage feedback resistors is elimi-
C1 nated by using feedback resistors internal to the DAC8221. Only
0.47␮F
VIN +
DAC A passes a signal; DAC B provides the second feedback
R2
R1
1/2 3.3k⍀ resistor. With VREFB unconnected, the current-to-voltage converter,
47k⍀ +
OP270E R14
100⍀
using RFBB, is accurate and not influenced by digital data reach-
1/2
– OP270E VOUT ing DAC B. Distortion of the digital panning control is less than
R4
1k⍀ –
0.002% over the 20 Hz to 20 kHz audio range. Figure 16 shows
R3 C2 R13 the complementary outputs for a 1 kHz input signal and a digital
680⍀ 6.8␮F L1 60Hz 3.3k⍀
+ ramp applied to the DAC data input.
TANTALUM 1H
R6 DUAL PROGRAMMABLE GAIN AMPLIFIER
1k⍀ The dual OP270 and the DAC8221, a dual 12-bit CMOS
R5 C3
680⍀ 1␮F L2 200Hz DAC, can be combined to form a space-saving dual program-
+
TANTALUM 600mH mable amplifier. The digital code present at the DAC, which is
R8 easily set by a microprocessor, determines the ratio between the
1k⍀
R7 C4 internal feedback resistor and the resistance the DAC ladder
680⍀ 0.22␮F L3 800Hz
presents to the op amp feedback loop. Gain of each amplifier is
180mH
VOUT 4096
=–
R10
1k⍀
R9 C5 VIN n
680⍀ 0.047␮F L4 3kHz

60mH where n equals the decimal equivalent of the 12-bit digital code
R12 present at the DAC. If the digital code present at the DAC
1k⍀
R11 C6 consists of all zeros, the feedback loop will open, causing the op
0.022␮F L5 10kHz
680⍀ amp output to saturate. A 20 MW resistor placed in parallel with
10mH the DAC feedback loop eliminates this problem with only a very
Figure 14. 5-Band Low Noise Graphic Equalizer small reduction in gain accuracy.

–12– REV. C
 OP270
+5V +15V
+15V +5V
21
DAC8221HP VDD 21 0.01␮F
DAC8221HP VDD
0.01␮F VREFA 4
RFBA 3 RFBA
VINA 3 +
20M⍀ 10␮F
+ –
10␮F IOUTA 2 2
– DAC A – 8
4 VREFA IOUTA 2 2
VIN DAC A – 8 1/2 1
OP270EZ
1/2 1 VOUTA
OP270GP OUT 3
+ 4
AGND 1 3
+ 4
DAC DATA BUS
PINS 6 (MSB) - 17 (LSB) AGND 1 –
RFBB 0.1␮F 10␮F
– 23 +
VINB
0.1␮F 10␮F
+
RFBB –15V –15V
23 IOUTB 24 6
DAC B –
1/2 7
22 VREFB IOUTB 24 6 OP270GP
NC DAC B –
VOUTB
1/2 20M⍀ 5
7 +
OP270GP OUT DAC DATA BUS
18 PINS 6 (MSB) - 17 (LSB)
DAC A/DAC B 5
+
18 VREFB 22
WRITE 19
19 CONTROL
WRITE CS 20
CONTROL 20 DGND
WR
DGND 5
5

Figure 17. Dual Programmable Gain Amplifier

Figure 15. Digital Panning Control

A OUT

A OUT

5V 5V 1ms

Figure 16. Digital Panning Control Output

REV. C –13–
OP270
OUTLINE DIMENSIONS

8-Lead Ceramic Dual In-Line Package [CERDIP] 8-Lead Plastic Dual In-Line Package [PDIP]
Z-Suffix P-Suffix
(Q-8) (N-8)
Dimensions shown in inches and (millimeters) Dimensions shown in inches and (millimeters)

0.005 (0.13) 0.055 (1.40) 0.375 (9.53)

MIN MAX 0.365 (9.27)
0.355 (9.02)
8 5

0.310 (7.87) 8 5 0.295 (7.49)

PIN 1 0.220 (5.59) 0.285 (7.24)
1 4 1 4 0.275 (6.98)
0.325 (8.26)
0.100 (2.54) BSC 0.310 (7.87)
0.320 (8.13) 0.100 (2.54) 0.150 (3.81)
0.405 (10.29) MAX 0.300 (7.62)
BSC
0.290 (7.37) 0.135 (3.43)
0.060 (1.52)
0.015 0.120 (3.05)
0.200 (5.08) 0.015 (0.38) 0.180
(4.57) (0.38)
MAX MIN
MAX
0.200 (5.08) 0.150 (3.81) 0.015 (0.38)
0.125 (3.18) MIN 0.150 (3.81) SEATING 0.010 (0.25)
0.015 (0.38) 0.130 (3.30) PLANE 0.008 (0.20)
0.023 (0.58) SEATING
0.070 (1.78) PLANE 15 0.110 (2.79) 0.060 (1.52)
0.014 (0.36) 0 0.008 (0.20)
0.030 (0.76) 0.022 (0.56) 0.050 (1.27)
0.018 (0.46) 0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR 0.014 (0.36)
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

16-Lead Standard Small Outline Package [SOIC]

Wide Body
S-Suffix
(RW-16)
Dimensions shown in millimeters and (inches)

10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
1 8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

2.65 (0.1043)
BSC ⴛ 45ⴗ
2.35 (0.0925) 0.25 (0.0098)
0.30 (0.0118)
0.10 (0.0039)
8ⴗ
0.51 (0.0201) SEATING 0ⴗ 1.27 (0.0500)
COPLANARITY 0.32 (0.0126)
0.33 (0.0130) PLANE 0.40 (0.0157)
0.10 0.23 (0.0091)
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

–14– REV. C
 OP270
Revision History
Location Page
4/03—Data Sheet changed from REV. B to REV. C.
Deletion of OP270A model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Deletion of WAFER LIMITS and DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to equations in Noise Measurements section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Change to Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
11/02—Data Sheet changed from REV. A to REV. B.
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9/02—Data Sheet changed from REV. 0 to REV. A.
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

REV. C –15–
–16–
C00325–0–4/03(C)