Curriculum Vitae of Prof.

Abhijit Biswas

1. Academic qualification:

Ph. D. (Semiconductor Physics, Devices and Circuits), Department of Radio

Physics and Electronics, University of Calcutta, INDIA (2005)
B. Tech. and M. Tech. in Radio Physics and Electronics, University of Calcutta,
INDIA

2. Research Interests:

Semiconductor Devices, Circuits, Optoelectronics and Photovoltaics

3. Teaching Experience: 25 years as a University Faculty Member

(i) Working as a Professor in University of Calcutta since 2012 –Till date

(ii) Worked as the Head of the Department in Radio Physics and Electronics, University of Calcutta
since December 2020 – December 2022.

4. Ph. D. Thesis supervised:

(i) Ms. Jayanti Paul (2022), “Ge and GeSn Channel MOSFETs and Their Performance Improvement
Through BOX Engineering”
(ii)Mr. Mainak Saha, (2022), “Performance Improvement of Nitride-Based Light-Emitting Diodes”
(iii) Mr. Arnab Laha (2021), “Application-Specific Optical Systems Hosting Exceptional
Singularities”
(iv) Ms. Suchismita De (2021), “Performance of Nanoscale MOSFETs Using High Mobility
Semiconductors”
(v) Mr. Himanshu Karan (2020), “Studies on nitride based light-emitting diodes for solid-state lighting”
(vi) Ms. Suchismita Tewari (2017), “Study of InGaAs n-channel MOSFETs for analog/mixed signal
application”
(vii) Ms. Chandrima Mondal (2016), “Studies on nanoscale Ge channel MOSFETs for analog and logic
applications”
(viii) Mr. Partha Sarathi Das (2014), “Studies on high-k gate dielectrics on GaAs substrates”
(ix) Ms. Swagata Bhattacherjee (2012), “Studies of device parameters of nanoscale double gate Si & Ge
MOSFETs”
(x) Mr. Pinaki Chakraborty (2010), “Modeling and characterization of non-volatile flash memory
devices”

5. Sponsored Research Projects:

(i) Title: Study of CMOS devices and circuits utilising “beyond silicon” channel materials for ULSI
applications

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Principal Investigator: Prof. A. Biswas, Co-Investigator: Prof. A. Mallik
Funded by CSIR (2012-2015)

(ii) Title: Studies on Nitride-based Light-emitting Diodes for Achieving Augmented Performance
Principal Investigator: Prof. A. Biswas
Funded by SERB (2013-2017)

(iii) Title: Special Manpower Development Program (SMDP) C2SD for 5 years with effect from 2015.
Chief Investigator: Dr. S. Pandit, Co-Investigator: Prof. A. Biswas
Funded by MeitY

(iv) Title: Investigations on high mobility III-V, Ge and GeSn nano CMOS devices including radiation
effects for analog/RF and logic applications
Funded by SERB (2018-2021)

6. Fellowships/Awards/Recognition/Honors:

(i). Recipient of University Grants Commission (UGC) Research Award (2012-2014)

(ii). Fellow in Institute of Engineers (FIE)
(iii). Life Member, Indian Physical Society
(iv). Life Member, The Institution of Electronics and Telecommunication Engineers (IETE), India
(v). Life Member, Forum of Scientists, Engineers & Technologists (FOSET), Kolkata
(vi). Member, IEEE Electron Device Society and Photonic Society
(vii). Post Doctoral Research Work at Interuniversity Microelectronic Center (IMEC), Belgium
(2007).
(viii) Received “Best Citizen of India Gold Medal Award” in August 2019 from Global Economic
Progress & Research Association.

7. Worked as Reviewer in the following Journals:

International:
(a) IEEE Electron. Device Lett.
(b) IEEE Trans. Electron Devices
(c) IEEE Journal of Quantum Electronics
(d) IEEE Trans. Nanotechnology
(e) Superlattices and Microstructures
(f) Optics & Laser Technology
(g) Microelectronics Reliability (Elsevier)
(h) Materials Science in Semiconductor Processing (Elsevier)
(i) Microsystem Technologies (Springer)
(j) IET Circuits, Devices and Systems
(k) Journal of Optical Communications
(i) Semiconductor Science and Technology

National:
(a) IETE Journal of Research
(b) Defense Science Journal

8. Working as a Guest Editor for the Journal Microsystem Technologies (Springer) in connection with
the International Conference Micro-2018.

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9. Working as a Guest Editor jointly with Dr. Prabir Saha for the Journal Microsystem Technologies
(Springer) in connection with the International Conference Micro-2017.

10. Working as a Guest Editor jointly with Prof. J. K. Mondal for the Journal Microsystem Technologies
(Springer) in connection with the International Conference Micro-2016.

11. My name was included in the Golden List of Reviewers of the IEEE Trans. Electron Devices for the
following calendar year: 2014 (Ref.: Vol.61, No. 12, p. 3922, Dec. 2014)

12. Worked as Ph.D. Thesis Examiner: Jadavpur University, Visva-Bharati University, Indian Institute
of Technology-BHU, NIT Rourkela, BIT Mesra and NIT Silchar.

13. Working as an External Member of the Ph. D. committee in the Department of Instrumentation and
Electronics, Jadavpur University.

14. Working as a Member of the Ph. D. committee in the Department of Radio Physics and Electronics,
University of Calcutta.

15. Conference/Workshop/Course Organized

(i) Worked as a General Chair in the 6th International Conference on Microelectronics, Circuits and Systems
during July 25-26, 2020, Kolkata.

(ii) Worked as a General Chair in the 6th International Conference on Microelectronics, Circuits and
Systems during July 6-7, 2019, Kolkata.

(iii) Worked as a General Chair in the 5th International Conference on Microelectronics, Circuits and
Systems during May 19-20, 2018, Bhubaneswar, Odisha.

(iv) Worked as a General Chair in the 4th International Conference on Microelectronics, Circuits and
Systems during June 3-4, 2017, Darjeeling, West Bengal.

(v) Worked as a Program Chair in the 3rd International Conference on Microelectronics, Circuits and
Systems during July 9-10, 2016, Kolkata.

(vi) Worked as a Course Co-ordinator for the Ph. D. course work in the Department of Radio Physics and
Electronics, University during June 16-30, 2016.

(vii) Worked as a Member in the 6th International Conference on Computers and Devices for
Communication (CODEC-15), December 16-18, 2015.

(viii) Worked as a course co-ordinator for the Summer School on “Frontiers of Nano Materials, Structures
and Devices (NanoMASTD), 2012” during June 20-July 10, 2012.

(ix) Worked as an associate course co-ordinator Techniques for Design, Fabrication and Computation of
Integrated Circuits (TECHNOMICS-12) during May 23-June 13, 2012.

(x) Worked as a course co-ordinator for the summer school on Physics and Simulation Techniques for
Nanoscale Electronic Devices NanoDev-2009 held during June 1-19, 2009.

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16. Invited Talks/ Plenary Talks:

(i) Keynote Talk, IEEE Silchar Subsection Conference (SILCON), 2022, NIT Silchar, Assam during
November 4-6, 2022.

(ii) Invited Talk, International Conference on Microelectronics, Computing & Communication Systems
(MCCS) at Ranchi during November 9-10, 2019.

(iii) Invited Talk, 5th International Conference on Microelectronics, Circuits and Systems, Bhubaneswar,
Odisha during May 19-20, 2018.

(iv) Invited Talk, AICTE Sponsored Short Term Training Course at IIT-BHU, Baranasi, July 17-22, 2017

(v) Invited Talk, 4th International Conference on Microelectronics, Circuits and Systems, Darjeeling during
June 3-4, 2017.

(vi) Invited Talk, 5-Day tutorial cum Workshop on Nano-materials and Devices for Biomedical
Applications, CRNN, Salt Lake, Kolkata, October 24-28, 2016.

(vii) Invited Talk, 3rd International Conference on Microelectronics, Circuits and Systems, Kolkata during
July 9-10, 2016.

(viii) Plenary Talk, International Conference on Recent Trends in Engineering and Material Sciences
(ICEMS-2016) at Jaipur National University, Jaipur, Rajathan during March 17-19, 2016.

(ix) Invited Talk, Organized by UGC-NRCPS at Tripura University, March 28, 2016.

(x) Invited Talk, International Conference on Microelectronics, Computing & Communication Systems
(MCCS) at Ranchi during November 14-15, 2015.

(xi) Invited Talk, Emerging Technology Trends in Electronics, Communication and Networking
(ET2ECN), SVNIT, Surat, December 26-27, 2014.

(xii) Invited Talk, Summer school on “Frontiers of Nano Materials, Structures and Devices
(NanoMASTD), 2012” organized by UGC-NRCPS during June 20-July 10, 2012.

(xiii) Invited Talk, Summer School on “Techniques for Design, Fabrication and Computation of Integrated
Circuits (TECHNOMICS-12).” organized by UGC-NRCPS during May 23-June 13, 2012.

(xiv) Invited Talk, Outreach program at Tezpur University organized by UGC-NRCPS during January
23-26, 2012.

(xv) Invited Talk, Outreach program at Mizoram University organized by UGC-NRCPS held during March
23-26, 2011.

(xvi) Invited Talk, Summer school on Photonics – Systems, Modeling Approach & Research Trends
PhotoSMART-2010 organized by UGC-NRCPS held during June 1-18, 2010.

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(xvii) Invited Talk, Summer school on Physics and Simulation Techniques for Nanoscale Electronic
Devices NanoDev-2009 organized by UGC-NRCPS held during June 1-19, 2009.

(xviii) Invited Talk, Summer school Physics of Semiconductor Nanosbtructures SemiNano-2008 organized
by UGC-NRCPS held during June 2-20, 2008.

17. List of Publications (Citations: 797; h-index: 16, i10-index: 29)

A. Research Papers Published/Accepted in Science Citation Index (SCI) Journals

1. K. Banerjee and A. Biswas, “Enhanced analog/RF performance of hybrid charge plasma based
junctionless C-FinFET amplifiers at 10 nm technology node,” Microelectronics Journal, 2022.
https:// DOI: 10.1016/j.mejo.2022.105662.

2. P. Chakraborti, A. Biswas and A. Mallik, “High Sensitivity Ge-source L-shaped Tunnel BioFETs
for Detection of High-K Biomolecules,” Microsystem Technologies, 2022.

3. A. Roy, S. Dey, A. Laha, A. Biswas and S. N. Ghosh, “Exceptional Point induced asymmetric mode
conversion in a dual-core optical fiber segment,” Optics Letts, Vol. 47, pp. 2546-2549, 2022

4. D. Roy, D. P. Samajdar and A. Biswas, “Design of hybrid solar cell with GaAs1−xBix (x = 0.01)
nanowire core and conformally coated P3HT/ITO shell,” Solar Energy, Vol. 238, pp.1-8, 2022.
https://doi.org/10.1016/j.solener.2022.04.019

5. H. Karan and A. Biswas, “Improving performance of light-emitting diodes using InGaN/GaN

MQWs with varying trapezoidal bottom well width”, Optik, Vol. 247, p. 167888, 2021.

6. D. Roy, D. P. Samajdar and A. Biswas, “Photovoltaic Performance Improvement of GaAs1-

xBixNanowire Solar Cells in Terms of Light Trapping Capability and Efficiency,” Solar Energy,
Vol. 221, pp. 468-475, 2021.

7. D. Roy and A. Biswas, “Design and Analysis of Ultra-Thin Dielectric Film Embedded Nanoscale
Double-Gate MOSFETs for Boosting Logic Performance,” AEUE - International Journal of
Electronics and Communications, Vol. 131, pp. 153614, 2021.

8. S. Ghosh, S. Tewari, A. Biswas, and A. Chakrabarti, “High performance pH sensors using ion
sensitive InGaAs-channel MOSFETs at sub-100 nm technology node,” J. of Electronic Materials,
Vol.50, pp.1292-1300, 2021.

9. K. Banerjee and A. Biswas, “Improved Digital Performance of Charge Plasma Based Junctionless
C-FinFETs at 10 nm Technology Node and Beyond,” AEUE - International Journal of Electronics
and Communications, Vol. 124, pp. 153350, Sept. 2020.

10. P. Nath, A. Biswas and V. Nath, “Performance optimization of solar cells using non-polar, semi-
polar and polar InGaN/GaN multiple quantum wells alongside AlGaN blocking layers,”
Microsystem Technologies, Vol. 27, pp. 301–306, 2021.

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11. A. Laha, S. Dey, D. Beniwal, A. Biswas and S. N. Ghosh, “Third-order exceptional point and
successive switching among three states in an optical microcavity,” Physical Review A, Vol. 101(6),
p-063829, 2020.

12. A. Laha, S. Dey, H. K. Gandhi, A. Biswas and S. N. Ghosh, “Exceptional Point and Toward Mode
Selective Optical Isolation,” ACS Photonics, Vol. 7, No. 4, pp. 967-974, 2020.

13. J. Paul, C. Mondal and A Biswas, “Suppression of buried oxide induced variability on digital
performance of GeOI pMOSFETs using substrate bias scheme,” Microsystem Technologies, 26,
pp.1605–1611, 2020.

14. S. Bhattacherjee and A. Biswas, “Investigation on noise performance of InAsxSb1-x MOSFETs with
compositional variations,” Microsystem Technologies, 26, pp.1133–1140, 2020.

15. S. Dasgupta, C. Mondal and A Biswas, “Effects of temperature and channel thickness on digital and
analog performance of InAs quantum well nMOSFETs,” Microsystem Technologies, 26, pp.1265–
1271, 2020.

16. S. De, S. Tewari, and A. Biswas, “Negative bias temperature instability (NBTI) effects on p-Si/n-
InGaAs hybrid CMOSFETs for digital applications,” Microsystem Technologies, Vol. 26, pp.1173–
1178, 2020.

17. S. Dasgupta, C. Mondal and A Biswas, “Role of grooving angle of 14-nm-InAs channel quantum
well MOSFETs for improvement of analog/RF and linearity performance,” IET Circuits, Devices
and Systems, Vol. 13, pp. 1292 – 1298, 2019.

18. S. De, S. Tewari, A. Biswas and A. Mallik, “Improved digital performance of hybrid CMOS inverter
with Si p-MOSFET and InGaAs n-MOSFET in the nanometer regime,” Microelectronic
Engineering, Vol. 211, pp. 18-25, 2019.

19. D. Roy and A. Biswas, “Effects of asymmetric underlap spacers on nanoscale JLTs and design of
optimized CMOS amplifiers,” IET Circuits, Devices and Systems, Vol. 13, pp. 510 – 518, 2019.

20. J. Paul, C. Mondal and A Biswas, “Subthreshold modeling of nanoscale germanium-tin (GeSn)-on-
insulator MOSFETs including quantum effects,” Materials Science in Semiconductor Processing,
Vol. 94, pp. 128-135, 2019.

21. A. Laha, A. Biswas and S. N. Ghosh, “Minimally asymmetric state conversion around exceptional
singularities in a specialty optical microcavity,” J. of Optics, Vol. 21, 025201, 2019.

22. H. Karan, M. Saha, A. Biswas and D. Biswas, “Analysis of luminescence spectra of rectangular and
trapezoidal InGaN/GaN multiple quantum wells under varying bias conditions,” Optical Materials,
Vol. 86, pp. 247-255, 2018.

23. N. Mondal, S. Tewari and A. Biswas, “Enhancement of pH-sensitivity using In0.53Ga0.47As channel
ion-sensitive-field-effect-transistors,” Microsystem Technologies, 2018.

24. A. Laha, A. Biswas and S. N. Ghosh, “Non-adiabatic Modal Dynamics around Exceptional Points
in an All-Lossy Dual-Mode Optical Waveguide: Towards Chirality Driven Asymmetric Mode-
Conversion,” Physical Review Applied, 2018.

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25. S. Bhattacherjee and A. Biswas, “Effects of sidewall spacer layers on thermal and low frequency
noise performance of SOI UTB MOSFETs,” Microsystem Technologies, 2018.
DOI:10.1007/s00542-018-4141-6

26. M. Saha and A. Biswas, “High Performance GaN/InGaN Multiple Quantum Well LEDs through
Electron Blocking Layer Engineering,” Microsystem Technologies, 2018. DOI:10.1007/s00542-
018-4091-z

27. J. Paul, C. Mondal and A Biswas, “Enhancing digital performance of nanoscale GeOI MOSFETs
through optimization of buried oxide properties and channel thickness,” Microsystem Technologies,
2018. DOI: 10.1007/s00542-018-4113-x

28. J. Paul, C. Mondal and A Biswas, “Studies of buried oxide properties on nanoscale GeOI
pMOSFETs for design of a high performance common source amplifier,” Materials Science in
Semiconductor Processing, Vol. 80, pp. 85-92, 2018.

29. M. Saha, A. Biswas and H. Karan, “Monolithic high performance InGaN/GaN white LEDs with a
tunnel junction cascaded yellow and blue light-emitting structures,” Optical Materials, Vol. 77, pp.
104-110, 2018.

30. D. Roy and A. Biswas, “Analytical model of nanoscale junctionless transistors towards controlling
of short channel effects through source/drain underlap and channel thickness engineering,”
Superlattices and Microstructures, Vol.113, pp. 71-81, 2018.

31. S. Bhattacherjee, A. Biswas and S. N. Ghosh, “Less-dispersive specialty optical fiber with an
enhanced operational bandgap for applications in the mid infrared region,” J. Opt. Soc. Am. B, Vol.
35, pp. 73-80, 2018.

32. S. Tewari, S. De, A. Biswas and A. Mallik, “Impact of sidewall spacer on n-InGaAs devices and
hybrid InGaAs/Si CMOS amplifiers in deca-nanometer regime,” Microsystem Technologies, 2017.

33. K. Banerjee, S.Tewari, and A. Biswas, “Impact of aspect ratio of nanoscale hybrid p-Ge/n-Si
complementary FinFETs on the logic performance,” Microsystem Technologies, 2017.

34. A. Roy, A. Biswas, R. K. Varshney and S. N. Ghosh, “Highly sensitive refractive index sensor based
on degeneracy in specialty optical fibers: a new approach,” Microsystem Technologies, 2017.
https://doi.org/10.1007/s00542-017-3622-3

35. H. Karan, M. Saha and A. Biswas, “Step multiple quantum well enabled performance enhancement
in InGaN/GaN based light-emitting diodes,” Microsystem Technologies, 2017. DOI:
10.1007/s00542-017-3567-6

36. D. Roy and A. Biswas, “Asymmetric underlap spacer layer enabled nanoscale double gate
MOSFETs for design of ultra-wideband cascode amplifiers,” Superlattices and Microstructures,
Vol. 110, pp. 114-125, 2017.

37. P. Biswas, B. Pal, A. Biswas and S. N. Ghosh, “Towards self-similar propagation of optical pulses
in a dispersion tailored, nonlinear and segmented Bragg fiber at 2.8 μm,” IEEE Photonics Journal,
Vol. 9, No. 4, 7104412-1-13, 2017.

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38. A. Laha, A. Biswas and S. N. Ghosh, “Next nearest neighbor resonance coupling and exceptional
singularities in degenerate optical microcavities,” Journal of the Optical Society of America B, vol.
34, No.10, pp. 2050-2058, August 2017.

39. H. Karan, A. Biswas and M. Saha, “Improved performance of InGaN/GaN MQW LEDs with
trapezoidal wells and gradually thinned barrier layers towards anode,” Optics Communications, Vol.
400, pp. 89-95, 2017.

40. S. De, S. Tewari, A. Biswas and A. Mallik, “Impact of channel thickness and spacer length on logic
performance of p-Ge/n-Si hybrid CMOSFETs for ULSI applications,” Superlattices and
Microstructures, Vol. 109, pp. 316-323, September 2017.

41. S. Bhattacherjee and A. Biswas, “Development of noise model for InAsSb MOSFETs and their
application in low noise amplifiers,” Microsystem Technologies, 2017.
https://doi.org/10.1007/s00542-017-3466-x

42. C. Mondal and A Biswas, “Performance analysis of nanoscale GeSn MOSFETs for mixed-mode
circuit applications,” Materials Science in Semiconductor Processing, Vol. 66, pp. 109-116, 2017.

43. D. Roy and A. Biswas, “Sidewall spacer layer engineering for improvement of analog/RF
performance of nanoscale double-gate junctionless transistors,” Microsystem Technologies, Vol. 23,
pp. 2847–2857, 2017.

44. P. S. Das and A. Biswas, “Effect of Ge interface control layer on the interfacial and electrical
properties of TaYOx thin films on GaAs substrates,” Microsystem Technologies, Vol. 23, pp. 2055-
2063, 2017.

45. D. Roy and A. Biswas, “Performance optimization of nanoscale junctionless transistors through
varying device design parameters for ultra-low power logic applications,” Superlattices and
Microstructures, Vol. 97, pp. 140-154, 2016.

46. P. Biswas, P. Adhikary, A. Biswas and S. N. Ghosh, “Formation and stability analysis of parabolic
pulses through specialty microstructured optical fibers at 2.1 µm,” Optics Communications, Vol.
377, pp. 120-127, 2016.

47. S. Tewari, A. Biswas and A. Mallik, “Impact of a Spacer Layer on the Analog Performance of
Asymmetric InP/InGaAs n-MOSFETs,” IEEE Trans. Electron Devices, Vol. 63, no. 6, pp. 2313 –
2320, 2016.

48. S. Bera, C. Mondal and A. Biswas, “Development of a Methodology for the Extraction of
BSIM3v3.2.2 Parameters of Ge-Channel MOSFETs and Estimation of Analog Circuit
Performance,” Microsystem Technologies, Vol. 23, Issue 9, pp. 4123-4131, 2016.

49. S. Tewari, A. Biswas and A. Mallik, “Performance of CMOS with Si p-MOS and asymmetric
InP/InGaAs n-MOS for analog circuit applications,” IEEE Trans. Electron Devices, Vol. 62, no. 5,
pp. 1655-1658, 2015.

50. S. Tewari, A. Biswas and A. Mallik, “Investigation on high performance CMOS with p-Ge and n-
InGaAs MOSFETs for logic applications,” IEEE Trans. on Nanotechnology, Vol. 14, pp. 274-281,
2015.

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51. P. S. Das and A. Biswas, Interface properties, physical and electrical characterization of sputtered
TaAlOx on silicon-passivated n-GaAs substrates,”
Appl. Phys. A, DOI 10.1007/s00339-014-8845-x, 2015.

52. C. Mondal and A. Biswas, “Binary Alloy Enabled Gate Work Function Engineering of Nanoscale
UTB-GeOI MOSFETs for Mixed-Signal System-on-Chip Applications,” Superlattices and
Microstructures, Vol. 75, pp. 118–126, 2014.

53. A. Biswas and S. Bhattacherjee, “Temperature dependent model for threshold voltage and
subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate,” Microelectronics
Reliability, Vol. 54, pp. 1527-1533, 2014.

54. C. Mondal and A. Biswas, “2-D compact model for drain current of fully depleted nanoscale GeOI
MOSFETs for improved analog circuit design,” IEEE Trans. Electron Devices, Vol. 60, No. 8, pp.
2525-2531, 2013.

55. C. Mondal and A. Biswas, “Performance analysis of nanoscale germanium on insulator MOSFETs
for mixed-signal system-on-chip applications,” Superlattices and Microstructures, Vol. 63, pp. 277-
288, 2013.

56. S. Tewari, A. Biswas and A. Mallik, “Impact of different barrier layers and indium content of the
channel on the analog performance of InGaAs MOSFETs,” IEEE Trans. Electron Devices, Vol. 60
, No. 5, pp. 1584-1589, May, 2013.

57. A. Biswas and S. Bhattacherjee, “Accurate modeling of the influence of back gate bias and interface
roughness on the threshold voltage of nanoscale DG MOSFETs,” Microelectronics Reliability, Vol.
53, Issue 3, pp. 363-370, 2013.

58. D. P. Bhattacharya, S. Midday, S. Nag and A. Biswas, "Lattice controlled transport in quantum
wires at low temperatures," Physica E: Low-dimensional Systems and Nanostructures, Vol. 47, pp.
264–269, January 2013.

59. C. Mondal and A. Biswas, “Studies on halo implants in controlling short-channel effects of
nanoscale Ge channel pMOSFETs,” IEEE Trans. Electron Devices, Vol. 59, No. 9, pp 2338-2344,
2012.

60. S. Tewari, A. Biswas and A. Mallik, “Study of InGaAs-channel MOSFETs for analog/mixed-signal
system-on-chip applications,” IEEE Electron Device Lett., Vol.33 , No.3, pp. 372-374, March, 2012.

61. S. Kabi, A. Biswas, D. Biswas and S. K. Biswas, “Investigations on optical transitions in InAs/InP
quantum dash structures,” Applied Nanoscience, Vol. 2, Issue 3, pp. 371-375, 2012.

62. P.S. Das and A. Biswas, “Investigations on electrical characteristics and reliability properties of
MOS capacitors using HfAlOx on n-GaAs substrates,” Microelectronics Reliability, Vol. 52, pp.
112-117, 2012.

63. P.S. Das and A. Biswas, “Investigation of charge trapping and breakdown characteristics of
sputtered-Y2O3 on n-GaAs substrates,” Thin Solid Films, Vol. 520, pp. 47-52, 2011.

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64. S. Bhattacherjee and A. Biswas, “Performance analysis of long Ge channel double gate (DG) p
MOSFETs with high-k gate dielectrics based on carrier concentration formulation,”
Microelectronics Reliability, Vol. 51, pp. 1105-1112, 2011.

65. P.S. Das and A. Biswas, “Influence of post deposition annealing on Y2O3-gated GaAs MOS
capacitors and their reliability issues,” Microelectronic Engineering, Vol. 88, pp. 282-286, 2011.

66. P.S. Das and A. Biswas, “Charge trapping and reliability characteristics of ultra-thin HfYOx films
on n-GaAs substrates,” Microelectronics Reliability, Vol. 50 , pp. 1924-1930, 2010.

67. P.S. Das and A. Biswas, “Improved electrical and interfacial properties of RF- sputtered HfAlOx on
n-GaAs with effective Si passivation,” Applied Surface Science, Vol. 256, pp. 6618-6625, 2010.

68. P. S. Das, G. K. Dalapati, D. Z. Chi, A. Biswas and C. K. Maiti, “Characterization

of Y2O3 gate dielectric on n-GaAs substrates,” Applied Surface Science, Vol. 256, pp. 2245-2251,
2010.

69. P. S. Das, A. Biswas and C. K. Maiti, “Effects of an ultrathin Si passivation layer on the interfacial
properties of RF-sputtered HfYOx on n-GaAs substrates,” Semiconductor Science and Technology
(U. K), Vol. 24, p. 085026 (6 pp.), 2009.

70. P. Chakraborty, S. S. Mahato, T. K. Maiti, M. K. Bera, C. Mahata, S. K. Samanta, A. Biswas and

C. K. Maiti, “Performance improvement of flash memory using AIN as charge-trapping layer,”
Microelectronics Engineering, Vol. 86, pp. 299- 302, 2009.

71. S. Bhattacherjee and A. Biswas, “Modeling of threshold voltage and subthreshold slope of
nanoscale DG MOSFETs,” Semiconductor Science and Technology (U. K), Vol. 23, p. 015010 (8
pp.), 2008.

72. B. Mukhopadhyay, A. Biswas, P. K. Basu, G. Eneman, P. Verheyen, E. Simoen and C. Claeys,

“Modeling of threshold voltage and subthreshold slope of strained–Si MOSFETs Including
quantum effects,” Semiconductor Science and Technology (U. K), Vol. 23, p. 095017 (8 pp.), 2008.

73. S. Bhattacherjee and A. Biswas, “Estimation of threshold voltage and subthreshold slope of
extremely scaled DG MOSFETs,” IETECH Journal of Information Systems, Vol. 2, no. 3, pp 127-
132, 2008.

74. M. Basak, A. Biswas and P. K. Basu, “Performance analysis of a -doped AllInAs- GaInAs HEMT
and design optimization of radio frequency MSM-HEMT transimpedance amplifier,” IETECH
Journal of Communication Techniques, Vol. 2, no. 2, p. 152-156, 2008.

75. A. Biswas and P. K. Basu, “Equivalent circuit models of quantum cascade lasers for SPICE
simulation of steady state and dynamic response,” Journal of Optics A : Pure and Applied Optics,
Vol. 9, pp. 26-32, 2007.

76. A. Biswas and P. K. Basu, “Modeling of Base Transit Time in Si/Si1-y-zGeyCz /Si HBTs and
Composition Profile Design Issue for Its Minimization,” Semiconductor Science and Technology,
U. K., Vol. 18, pp. 907 - 913, 2003.

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 77. A. Biswas and P. K. Basu, “An analytical approach to the modelling of intrinsic base sheet resistance
in a SiGe HBT and optimal profile design considerations for its minimization,” Semiconductor
Science and Technology, U. K., Vol. 17, p.1249 –1254, 2002.

78. A. Biswas and P. K. Basu, “Estimated effect of germanium and carbon on the Early voltage of a
Si1-x-yGexCy heterojunction bipolar transistor,”' Semiconductor Science and Technology, U. K., Vol.
16, pp. 947 - 953, 2001.

79. A. Biswas and P. K. Basu, “Calculation of figures of merit of Si/Si1-x-yGexCy/Si HBTs and their
optimization,” Solid State Electronics, U. K., Vol. 45, pp. 1885 –1889, 2001.

80. A. Biswas and P. K. Basu, ''Calculation of base transit time in Si HBTs with incorporation of C in
SiGe base,'' Indian Journal of Physics 75B, Vol. 3, pp. 223-225, 2001.

B. Books/ Book Chapter Published

1. A. Biswas, R. S. Saxena and D. De, “Microelectronics, Circuits and Systems Select Proceedings
of 7 th International Conference on Micro2020” in LNEE Springer, 2021. ISBN: 978-981-16-
1569-6

2. K. Banerjee, S.Tewari, and A. Biswas, “Effects of Fin Height on Digital Performance of Hybrid p-
Si/n-InGaAs C-FinFETs at 25 nm Gate Length,” in In LNEE Springer book series:
Nanoelectronics, Circuits and Communication Systems, Vol. 642, April 2020, DOI: 10.1007/978-
981-15-2854-5_7

3. A. Biswas and P. K. Basu, High Performance Ge MOSFETs for Future Nanoelectronics, Advances
in Microelectronics and Photonics, Nova Science Publishers, 2011, USA.

C. Research Papers Published in Refereed Conference Proceedings

1. P. Nath and A. Biswas, “Performance augmentation of radiation-resilient III-nitride based multi-

junction solar cells with varying composition and thickness of the cap layer,” IEEE Silchar Subsection
Conference (SILCON), 2022, November 4-6, 2022, NIT Silchar, Assam.

2. A. Roy, S. Dey, A. Laha, A. Biswas, and S. Ghosh, “Selective mode conversions in a dual core optical
fiber hosting multiple exceptional points,” Frontiers in Optics and Laser Sciences (FiO+LS-2022),
October 17-20, 2022, paper JW5B.40, Rochester, New York, (Hybrid meeting), USA.

3. A. Roy, S. Dey, A. Laha, A. Biswas, and S. Ghosh, “Hosting an exceptional point in a gain-loss assisted
dual-core optical fiber segment,” Frontiers in Optics and Laser Sciences (FiO+LS-2021), November
1-4, 2021, Technical Digest Series (Optica); paper JW7A.50, Washington DC (Hybrid meeting), USA.

4. P. Nath and A. Biswas, “Radiation-resilient GaN/InxGa1-xN multi-junction solar cells with varying In
contents,” in the 3th International Conference ICCDC 2021, organised by Haldia Institute of
Engineering, 16th -18th August, 2021.

5. M. Saha and A. Biswas, “Improvement of Efficiency and Uniformity of Dual Wavelength Emission
for GaN/InGaN Multiple Quantum Well LEDs Through Triangular Electron Blocking Layer,” 3rd

11
 International Conference on Communication, Devices and Computing (ICCDC 2021), August 16-18,
2021 at Haldia Institute of Technology, Haldia, West Bengal, India.

6. P. Chakraborti, A. Biswas and A. Mallik, “Detection of High-K Biomolecules Using Ge-source L-

shaped Tunnel BioFETs,” in Proc. 8th International Conference on Microelectronics, Circuits and
Systems, Micro2021, Kolkata, India, 8-9 May. 2021.

7. P. Chakraborti, A. Biswas and A. Mallik, “Sensing of High-K Biomolecules using L-Shaped Tunnel
FET,” in Proc. 7th International Conference on Microelectronics, Circuits and Systems, Micro2020,
Delhi, India, 25-26 Jul. 2020., pp. 25-33.

8. S. Sadhukhan, A. Laha, A. Biswas, and S. Ghosh, “Photonic crystal based ultra-sensitive

interferometric nanometer displacement sensor,” OSA Frontiers in Optics + Laser Science APS/DLS
(FIO + LS), September 14-17, 2020, OSA Technical Digest (online); paper JTu1A.3, Virtual Web
Conference, USA.

9. A. Laha, A. Biswas, and S. Ghosh, “Nonlinearity controlled asymmetric mode-conversion in an optical

waveguide hosting an exceptional point,” The JSAP-OSA Joint Symposia (80th Autumn Meeting of
the Japan Society of Applied Physics), September 18-21, 2019, OSA Technical Digest (online); paper
20p_E215_4, Hokkaido University (Sapporo Campus), Japan.

10. A. Laha, S. Dey, H. K. Gandhi, A. Biswas, and S. Ghosh, “Mode selective optical isolation in an
optical waveguide hosting an exceptional point,” International Conference on Optics and Electro-
optics (ICOL: XLIII Symposium of the Optical Society of India), October 19-22, 2019, Instruments
Research and Development Establishment (IRDE), Dehradun, India.

11. A. Laha, S. Dey, A. Biswas, and S. Ghosh, “Topological control of state-flipping in a specialty optical
microcavity,” Workshop on Optics & Photonics: Theory & Computational Techniques (OPTCT),
March 23-24, 2019, Indian Institute of Technology Delhi, India.

12. A. Laha, A. Biswas, S. Bhattacherjee and S. N. Ghosh, “Exceptional Points in a Specialty Microcavity:
Interplay between State-Conversion and Cavity Control Parameters,” in the 13th Pacific Rim
Conference on Lasers and Electro-Optics (CLEO Pacific Rim, CLEO-PR 2018), Hong Kong , Jul. 29-
Aug. 3, 2018.

13. A. Laha, A. Biswas, and S. N. Ghosh, “All-Lossy Quasi-Guided Dual-Mode Optical Waveguide
Exhibiting Exceptional Singularities,” in the Advanced Photonics Congress, Zurich, Switzerland, Jul
2-5, 2018.

14. S. Bhattacherjee and A. Biswas, “Impact of substrate bias and dielectric spacer layers on the noise
performance of UTB SOI MOSFETs,” 5th International Conference on Microelectronics, Circuits and
Systems (MICRO 2018), May 19-20, 2018.

15. J. Paul, C. Mondal and A. Biswas, “ Impact of buried oxide properties on improving digital
performance of ultra-thin body GeOI MOSFETs in deca-nanometer regime,” 5th International
Conference on Microelectronics, Circuits and Systems (MICRO 2018), May 19-20, 2018.

16. N. Mondal, S. Munshi, S. Tewari and A. Biswas, “Analysis of high sensitivity pH-Sensor using
In0.53Ga0.47As Channel Ion-Sensitive-Field-Effect-Transistors,” 5th International Conference on
Microelectronics, Circuits and Systems (MICRO 2018), May 19-20, 2018.

12
17. M. Saha and A. Biswas, “Enhancing the Quantum Efficiency of GaN/InGaN Multiple Quantum Well
LEDs by Electron Blocking Layer Engineering,” 5th International Conference on Microelectronics,
Circuits and Systems (MICRO 2018), May 19-20, 2018.

18. A. Laha, A. Biswas and S. N. Ghosh, “Adiabatic Optical State Conversion around Exceptional
Singularities in an Optical Microcavity of Varying Width,” in the International Conference on
Advanced Optics and Photonics: ICAOP-2017 (XLI Conference of Optical Society of India)Haryana,
India, November 23-26, 2017.

19. H. Karan and A. Biswas, “Performance improvement of light-emitting diodes with W-shape
InGaN/GaN multiple quantum wells,” International Conference on Communication, Devices and
Computing (ICCDC), Haldia, India, November 2-3, 2017.

20. M. Saha and A. Biswas, “Enhanced Performance of GaN/InGaN Multiple Quantum Well LEDs by
Shallow First Well and Stepped Electron Blocking Layer,” International Conference on
Communication, Devices and Computing (ICCDC), Haldia, India, November 2-3, 2017.

21. P. Biswas, S. N. Ghosh, R. K. Varshney, A. Biswas, and B. P. Pal, “Stable Propagation of Self Similar
Pulses Through A Chirped-clad All-solid Bragg Fiber in the Mid-IR,” 5th Workshop on Speciality
Optical Fibers and Their Applications (WSOF), Limassol, Cyprus, October 11-13, 2017.

22. P. Biswas, S. N. Ghosh, R. K. Varshney, A. Biswas, and B. P. Pal, “Parametric dependence of self-
similar propagation of parabolic pulses in a dispersion oscillating fiber,” 24th Congress of the
International Commission for Optics, August 21 – 25, 2017, Tokyo, Japan.

23. P. Biswas, S. N. Ghosh, R. K. Varshney, A. Biswas, and B. P. Pal, “Stable Propagation of Self Similar
Pulses Through A Chirped-clad All-solid Bragg Fiber in the Mid-IR,” 5th Workshop on Speciality
Optical Fibers and Their Applications (WSOF), Limassol, Cyprus, October 11-13, 2017.

24. P. Biswas, S. N. Ghosh, R. K. Varshney, A. Biswas, and B. P. Pal, “Parametric dependence of self-
similar propagation of parabolic pulses in a dispersion oscillating fiber,” in The 24th Congress of the
International Commission for Optics, August 21 – 25, 2017, Tokyo, Japan.

25. D. Roy and A. Biswas, “Improved Analog Performance with Asymmetric Underlap Spacers in Double
Gate MOSFETs,” 4th Int. Conf. on Microelectronics, Circuits & Systems (MICRO-2017), Darjeeling,
India, June 3-4, 2017.

26. A. Laha, A. Biswas and S. N. Ghosh, “Cascaded state-flipping around exceptional points in an
unconventional optical microcavity with balanced gain-loss,” 4th Int. Conf. on Microelectronics,
Circuits & Systems (MICRO-2017), Darjeeling, India, June 3-4, 2017.

27. H. Karan, M. Saha and A. Biswas, “Improved Performance of InGaN/GaN Based Light-Emitting
Diodes With Step Multiple Quantum Well Structures,” 4th Int. Conf. on Microelectronics, Circuits &
Systems (MICRO-2017), Darjeeling, India, June 3-4, 2017.

28. J. Pal, C. Mondal and A. Biswas, “Buried Oxide Design Considerations for Improving Analog
Performance of Ultra-Thin Body GeOI MOSFETs,” 4th Int. Conf. on Microelectronics, Circuits &
Systems (MICRO-2017), Darjeeling, India, June 3-4, 2017.

13
29. K. Banerjee, S. Tewari and A. Biswas, “Analysis of logic performance of nanoscale hybrid p-Ge/n-Si
complementary FinFETs,” 4th Int. Conf. on Microelectronics, Circuits & Systems (MICRO-2017),
Darjeeling, India, June 3-4, 2017.

30. S. Tewari, S. De, A. Biswas and A. Mallik , “Effect of sidewall spacers on the analog performance of
InGaAs nMOSFETs in deca-nanometer regime,” 4th Int. Conf. on Microelectronics, Circuits &
Systems (MICRO-2017), Darjeeling, India, June 3-4, 2017.

31. A. Roy, A. Biswas and S. N. Ghosh, “ Inter-modal interactions and towards sensing in speciality optical
fibers,” 4th Int. Conf. on Microelectronics, Circuits & Systems (MICRO-2017), Darjeeling, India, June
3-4, 2017.

32. S. Bhattacherjee, A. Biswas and S.N. Ghosh, “Towards Ultra-large bandwidth in band-gap engineered
specialty optical fibers: design and performance study,” Proc. in Optics & Photonics Theory &
Computational Techniques” (OPTCT), IIT Delhi, India, March 4-5, 2017.

33. A. Laha, A. Biswas and S. N. Ghosh, “Exceptional singularities in unconventional gain-loss optical
microcavities”, Workshop on Optics & Photonics: Theory & Computational Techniques (OPTCT-
2017), Indian Institute of Technology Delhi, India, March 4-5, 2017.

34. S. Tewari, S. De, A. Biswas and A. Mallik, “Investigations on Logic Performance of p-Ge/n-Si Hybrid
CMOSFETs for Digital Applications,” 2nd International Conference on Nano-electronics, Circuits &
Communication Systems (NCCS-2016) Ranchi, December 25-26, 2016.

35. P. Biswas, S. Ghosh, A. Biswas, and B. P. Pal, “Self-similar propagation in a dispersion managed and
highly nonlinear Segmented bandgap fiber in the mid-IR,” in Frontiers in Optics 2016, OSA Technical
Digest (online) (Optical Society of America, 2016), paper JTh2A.51, 17 – 21 October, 2016.

36. P. Biswas, A. Biswas, and S. Ghosh, “Stability analysis of self-similar pulse propagation through
dispersion oscillating specialty optical fibers,” in 13th International Conference on Fiber Optics and
Photonics, OSA Technical Digest (online) (Optical Society of America, 2016), paper W4C.2, 4 – 8
December, 2016.

37. S. Bhattacherjee and A. Biswas, “Noise analysis of III-V anion based MOSFETs,” Int. Conf. on
Microelectronics, Circuits and Systems (MICRO), Kolkata, July 9-10, pp. 159-164, 2016.

38. D. Roy and A. Biswas, “Subthreshold modeling of nanoscale double gate junctionless transistors with
laterally displaced source/ drain,” International Conference on Recent Trends in Engineering and
Material Sciences (ICEMS-2016), Jaipur National University, Jaipur, India, March 17-19, 2016.

39. S. De, S. Tewari, A. Biswas and A. Mallik, “Improved logic circuit performance of hybrid CMOS
inverter with Si p-MOSFET and InGaAs n-MOSFET,” International conference on recent trends in
engineering and material sciences (ICEMS-2016), Jaipur National University, Jaipur, India,17-19
March, 2016.

40. S. Tewari, P. K. Saha, A. Biswas and A. Mallik, “Investigations on the logic performance of hybrid
CMOSFETs comprising p-Ge/ n-InGaAs MOSFETs with barrier layers,” on International conference
on microelectronics computing and communication systems (MCCS-2015), Ranchi, India, November
14-15, 2015.

14
41. D. Roy and A. Biswas, “Impact of sidewall spacer layers on the analog/rf performance of nanoscale
double-gate junctionless transistors,” International Conference on Microelectronics, Computing and
Communication Systems (MCCS-2015), Ranchi, India, November 14-15, 2015.

42. S. Dasgupta, C. Mondal and A. Biswas, "Impact of channel thickness of nanoscale inas on insulator
mosfets for analog/rf circuit applications," 4th International Conference on Innovations in Electronics
and Communication Engineering (ICIECE), Aug 21-22, 2015, Hyderabad, pp. 383-387.

43. J. Pal, C. Mondal and A. Biswas, “Effects of back-gate bias and buried oxide properties in controlling
short channel effects of GeOI MOSFETs,” 4th International Conference on Innovations in Electronics
and Communication Engineering (ICIECE), Aug 21-22, -2015, Hyderabad, pp. 388-392.

44. S. Bera, C. Mondal and A. Biswas, “Extraction of BSIM3v3.2.2 parameters of Ge-channel MOSFETs
for circuit simulation” 2nd International Conference on Microelectronics, Circuits and Systems
(MICRO-2015), July 11-12, 2015, Kolkata, pp. 62-66.

45. S. Tewari, A. Biswas, and A. Mallik, “Effects of barrier layer on the analog performance of p-Ge/n-
InGaAs CMOS Devices,” 2nd International conference on Emerging Technology, Trends in
Electronics, Communication & Networking (ET2ECN), SVNIT, 26-27 December, 2014.

46. C. Mondal and A. Biswas, “Improvement of analog circuit performance of nanoscale p-MOSFETs
enabled by strained GeSn channel,” International Conference on Information and Communication
Engineering (ICICE-2014), pp. 6-12.

47. C. Mondal and A. Biswas, “Role of gate work function profiles on the analog performance pf nanoscale
UTB-GeOI MOSFETs,” International Conference on Information and Communication Engineering
(ICICE-2014), pp. 1-6.

48. **S. De, S. Tewari, A. Biswas and A. Mallik,” Studies on the Analog Performance of InGaAs Channel
Junctionless Transistors,” 2nd International Conference on Innovations in electronics and
Communication Engineering (ICIECE), pp. 676-680, Hyderabad, August 10-11, 2013.

49. **S. Tewari, A. Biswas and A. Mallik,” Studies on digital performance of CMOS comprising Ge p-
MOSFET and InGaAs n-MOSFET with different in contents,” 2nd International Conference on
Innovations in Electronics and Communication Engineering (ICIECE), pp. 667-671, Hyderabad,
August 10-11, 2013.

50. C. Mondal and A. Biswas,” Influence of work function engineering on the analog performance of
nanoscale UTB-GeOI MOSFETs,” 2nd International Conference on Innovations in Electronics and
Communication Engineering (ICIECE), pp. 662-666, Hyderabad, August 10-11, 2013.

51. S. Tewari, A. Biswas and A. Mallik, “Impact of indium contents on the analog circuit performance of
InGaAs channel MOSFETs”, Int. Conference on Electrical, Electronics and Computer Science
(ICEECS-2013), ISBN: 978-93-81693-88-16, pp. 178-182, Chandigarh, India, March 24, 2013.

52. C. Mondal and A. Biswas,” Influence of work function engineering on the short channel effects of
nanoscale GeOI MOSFFETs,” Int. Conference on Electrical, Electronics and Computer Science
(ICEECS-2013), ISBN: 978-93-81693-88-16, pp. 103-109, Chandigarh, India, March 24, 2013.

15
53. **C. Mondal and A. Biswas,” Analog performance of nanoscale germanium- on-Insulator
pMOSFETs,” Int. Conference on Electrical, Electronics and Computer Science (ICEECS-2013),
ISBN: 978-93-81693-88-16, pp. 98-102, Chandigarh, India, March 24, 2013.

54. S. Tewari, A. Biswas and A. Mallik, “Analog performance of dual-material gate InGaAs MOSFETs,”
Int. Conference on Emerging Electronics (ICEE 2012), ISBN: 978-1-4673-3136-4/12/$31.00 ©2012
IEEE, pp. 1- 4, IIT Bombay, India during December 15-17, 2012.

55. C. Mondal and A. Biswas, “Impact of metal source/drain contacts on Ge-on-Insulator (GeOI)
MOSFETs,” Proc. of Int. Conference on Electrical and Electronics Engineering (ICEEE), ISBN: 978-
93-82208-02-0, pp 82-85, Hyderabad, August 12, 2012.

56. **S. Tewari, A. Biswas, A. Mallik, “Influence of a barrier layer in enhancement mode n-MOSFETs
using InGaAs channel for analog/mixed signal system-on-chip applications,” Proc. of Int. Conference
on Electrical and Electronics Engineering (ICEEE), ISBN: 978-93-82208-02-0, pp 74-76, Hyderabad,
August 12, 2012.

57. P. S. Das and A. Biswas, “Interfacial characterization and reliability issues of high-k gate dielectrics
on GaAs substrate for MOSFET applications,” IEEE/OSA/IAPR International Conference on
Informatics, Electronics & Vision, pp. 1113-1117, Univ. of Dhaka, Bangladesh, May 18-19, 2012.

58. **C. Mondal and A. Biswas, “Modeling of high performance nanoscale GeOI pMOSFETs for analog
applications,” Int. Conf. Nanotechnology and Biosensors (ICNB2), Vishakhapatnam, INDIA, VL-04,
December 28-29, 2011.

59. P. S. Das, A. Biswas, S. Dutta Gupta, J. Mitard, G. Eneman, B. De Jaeger, M. Meuris and M. M.
Heyns, “Parameter extraction for long Ge Channel pMOSFETs with different channel-orientations,”
Int. Conf. Nanotechnology and Biosensors (ICNB2), Vishakhapatnam, INDIA, VL-05, December 28-
29, 2011.

60. S. Tewari, A. Biswas, A. Mallik, “Analog performance analysis of inversion type enhancement mode
n-MOSFETs using InGaAs channel,” Int. Conf. Nanotechnology and Biosensors (ICNB2),
Vishakhapatnam, INDIA, VL-06, December 28-29, 2011.

61. C. Mondal and A. Biswas, “Controlling of short channel effects in pocket implanted Ge channel
pMOSFETs with high-k gate stacks,” XVI Int. Workshop Physics Semd. Devices (IWPSD) -2011, IIT
Kanpur, INDIA, MS-P.19, December 19-22, 2011.

62. S. Dutta Gupta, A. Biswas, J. Mitard, G. Eneman, B. De Jaeger, M. Meuris and M. M. Heyns, “Device
characteristics and parameters of high performance long-channel Ge pMOSFETs with different
channel-orientations”, XVI Int. Workshop Physics Semd. Devices (IWPSD) -2011, IIT Kanpur,
INDIA, VT-P.06, December 19-22, 2011.

63. S. Bhattacherjee and A. Biswas “Evaluation of analog circuit performance of Ge-channel p-DG
MOSFETs with high-k dielectrics based on continuous drain current model,” Int. Conf. ICCCD-2010,
IIT, Kharagpur, INDIA, Paper Code 220, December 10-12, 2010.

64. C. Mondal and A. Biswas, “Influence of halo implants in controlling short channel effects (SCEs) of
Ge channel pMOSFETs,” Int. Conf. ICFANT 2010, Kolkata, INDIA, pp 105-111, December 9-11,
2010.

16
65. P. S. Das and A. Biswas, “Studies of charge trapping and breakdown characteristics of RF sputtered
HfAlOx gate dielectric on n-GaAs substrates with ultra-thin silicon inter-layer,” Int. Conf. ICFANT
2010, Kolkata, December 9-11, 2010.

66. **C. Mondal and A. Biswas, “Modeling and simulation studies of high performance Ge channel
pMOSFETs with high-k/metal gate stacks,” Int. Conf. ICETES 2010, Tamil Nadu, pp. 216-220,
March 25-26, 2010.

67. P. S. Das and A. Biswas, “Current conduction in HfYOx gated MOS capacitors on n-GaAs substrates
with the silicon interfacial layer,” Int. Conf. ICETES 2010, Tamil Nadu, pp. 532-536, March 25-26,
2010.

68. A. Biswas, “Determination of uniaxial stress of embedded Si1-yCy source/drain nMOSFETs using
numerical simulation techniques,” Int. Conf. ELECTRO-2009, BHU, Varanasi, INDIA, pp. 47-49,
December 22-24, 2009.

69. S. Bhattacherjee and A. Biswas, “Impact of high-k dielectrics and spacer layers on the elctrical
performance of symmetrical double gate MOSFETs,” Int. Conf. ELECTRO-2009, BHU, Varanasi,
INDIA, December 22-24, pp. 39-42, December 22-24, 2009.

70. A. Biswas and M. Basak Nath, “Influence of temperature on the threshold voltage and subthreshold
slope of strained-Si/SiGe MOSFETs with polysilicon gates,” Int. Conf. ELECTRO-2009, BHU,
Varanasi, INDIA, pp. 43-46, December 22-24, 2009.

71. S. Goswami and A. Biswas, “Modeling and numerical simulation of gate leakage current in strained-
Si channel nMOSFETs with high-k gate dielectrics,” Int. Conf. ELECTRO-2009, BHU, Varanasi,
INDIA, pp. 35-38, December 22-24, 2009.

72. A. Biswas and S. Bhattacherjee, “Effects of back gate bias and surface roughness on the threshold
voltage of nanoscale DG MOSFETs,” XV Int. Workshop Physics Semd. Devices (IWPSD) -2009,
Delhi, INDIA, pp.683-686, December 15-19, 2009.

73. S. Goswami and A. Biswas, “Impact of structural dimensions, channel doping concentration and bias
voltages on SCEs of nanoscale FD SOI-MOSFETs,” XV Int. Workshop Physics Semd. Devices
(IWPSD) -2009, New Delhi, INDIA, pp. 659-662, December 15-19, 2009.

74. S. Bhattacherjee, A. Biswas and P. K. Basu, “Influence of gate architectures on the performance of
SOI MOSFETs including the strained channel,” CODEC-2009, Kolkata, EDM, December 14-16,
2009.

75. S. Bhattacherjee and A. Biswas, “Estimation of threshold voltage and subthreshold slope of extremely
scaled DG MOSFETs,” IET-UK Int. Conf. Infor. and Comm. Tech. in Electrical Sciences ( ICTES
2007 ), Chennai, INDIA, Vol II, p. 873-878, December 20-22, 2007.

76. M. Basak, A. Biswas and P. K. Basu, “Analysis of a radio frequency transimpedance amplifier
based on a -doped AlInAs-GaInAs HEMT and its performance optimization,” IET-UK Int. Conf.
on Infor. and Comm. Tech. in Electrical Sciences ( ICTES 2007 ), Chennai, INDIA, Vol II, p. 879-
883, December 20-22, 2007.

17
77. S. Bhattacherjee and A. Biswas, “Effects of gate bias on the threshold voltage of nanoscale double-
gate (DG) MOSFETs,” XVI Int. Workshop Physics Semd. Devices (IWPSD) -2007 at IIT, Bombay,
India, December 16-20, 2007.

78. **A. Biswas and P. K. Basu, “Steady state and dynamic equivalent circuit models of a quantum
cascade laser and SPICE simulation of threshold current, intensity modulation response and optical
bandwidth,” Golden Jubilee Symposium on Radio Science, (INCURSI-2007), ODA-1, New Delhi,
February 21-24, 2007.

79. M. Basak, A. Biswas and P. K. Basu,“Design optimization of a transimpedance amplifier based on a

-doped AlInAs-GaInAs HEMT taking into account the radio frequency modeling of HEMTs in a
SPICE framework,” Golden Jubilee Symposium on Radio Science, (INCURSI-2007), ODA-24, New
Delhi, February 21-24, 2007.

80. S. Bhattacherjee and A. Biswas, “Modeling of the threshold voltage and subthreshold slope of
nanoscale double-gate MOSFETs,” Golden Jubilee Symposium on Radio Science, (INCURSI-2007),
ODA-31, New Delhi, February 21-24, 2007.

81. S. Bhattacherjee and A. Biswas, “Influence of structural dimensions, channel doping and gate
materials on the threshold voltage of Double Gate MOSFETs in the nanometer regime,” Int. Conf.
CODEC-06, Kolkata, December 18-20, p. 332-335, 2006.

82. M. Basak, A. Biswas and P. K. Basu, “Analysis and design optimization of a transimpedance
amplifier based on -doped AlInAs-GaInAs HEMTs in the microwave frequency,” Int. Conf.
CODEC-06, Kolkata, December 18-20, p. 332-335, 2006.

83. A. Biswas and P. K. Basu, “Development of equivalent circuits of a quantum cascade laser and SPICE
simulation of a steady state and dynamic response”, Int. Conf. CODEC-06, Kolkata, December 18-20,
p. 512-515, 2006.

84. A. Biswas and P. K. Basu, “Design issues of an optimal low noise amplifier based on SiGe HBTs, its
modeling and simulation using PSpice” published in the Int. Conf. on Electronic and Photonic
Materials, Devices and Systems, Kolkata, Jan 4-6, 2006.

85. P. K. Basu, A. Biswas and S. Ghosh, “Emerging electronic and optoelectronic devices based on silicon
and related materials” published in Int. Conf. on Communications, Devices and Intelligent systems,
Kolkata, held on January 9-10, p. 361- 364, 2004.

86. A. Biswas and P. K. Basu, “Modelling of SiGe-base HBTs and their simulation using PSpice” Abstract
in Conf. on Horizons on Telecommunications ( HOT-2003), Kolkata, p.11, 2003.

87. A. Biswas and P. K. Basu, “Calculation of figures of merit of Si/SiGeC/Si HBTs and their
optimization” Proceedings of the Int. Conf. on Communications, Computers and Devices, IIT,
Kharagpur, vol –1, p. 95-97, December 14-16, 2000.

88. A. Biswas and P. K. Basu, “Minimization of base transit time in Si HBTs by incorporation of C in
SiGe base” Abstracts in Symp. Advances in Microwave, Millimeterwave and Infrared Technology (
SAMMIT 99) December 21-24, 1999.

18
89. A. Biswas “SiGe Heterostructures: Physics, Devices and Consumer Applications,” Abstracts in the
UGC-sponsored 40th Orientation Program, Academic Staff College, C.U., December 21, 2000 -
January 19, 2001

** Received Best Paper Award

19