Q-1 (16 pts):

Design a combinational a) (4 pts.) Derive the truth table for the device.
circuit that takes the
absolute value of a 3-bit
(abc) number represented
with signed 2’s
complement. The computed
absolute value is a b c y z
represented with a 2-bit (yz) 0 0 0 0 0
unsigned binary number. “a” 0 0 1 0 1
and “y” are the most 0 1 0 1 0
significant bits of input and 0 1 1 1 1
output respectively. The 1 0 0 X X
input can be any 3-bit 2’s 1 0 1 1 1
complement number 1 1 0 1 0
except -4, since +4 cannot
1 1 1 0 1
be represented in 2 bits
unsigned binary number
system.

b) (8 pts.) Sketch the K-map(s), and derive the output Boolean function(s) in minimal SOP form.

y: bc z: bc
a 00 01 11 10 a 00 01 11 10
0 0 0 1 1 0 0 1 1 0
1 X 1 0 1 1 X 1 1 0

y = a’b + ab’ + bc’ Both z=c

solutions
ac’
ok.

c) (4 pts.) Sketch a schematic using NAND and NOT gates only

y = a’b + ab’ + bc’

y’= (a’b + ab’ + bc’)’ = (a’b)’ . (ab’)’ . (bc’)’
y = ( (a’b)’ . (ab’)’ . (bc’)’ )’

b y

c
z

1
Q-2 (15 pts):
a) Given the following circuit with inputs A,B,C,D and output F:
2x1 MUX

B 0 i. (4 pts.) Find the SOP expression for F in terms of the

Out 2x1 MUX inputs A,B,C,D. Do not use truth table or K-Map.
0 1
S 0
Out F
A
1
F = (A’B).D’ + (A’+AC).D
S S
1 0 = A’BD’ + A’D + CD
Out D
1
= A’B + A’D + CD (if you did not simplify, it is ok since the
C
question does not ask to simplify/minimize)
2x1 MUX

ii. (5 pts.) Implement F using a single multiplexer having minimum number of inputs. Do not
use any other gates. You may use logic levels 0 and 1 but complements of variables are not
provided.

4x1 MUX
B 0
1 1
Out F
0 2
C 3
S1 S0
A D

b) (6 pts) Using only a minimum number of 4-bit A3 A2 A1 A0 B3 B2 B1 B0

binary parallel adders given right, design a circuit
which multiplies a given unsigned 4-bit binary 4 Bits Parallel Adder
number(abcd) by constant (6)10 and outputs the
result Y[6:0] in binary form. Cout S3 S2 S1 S0

Y1 Y0
a b c d 0 a b c

A3 A2 A1 A0 B3 B2 B1 B0
4 Bits Parallel Adder

Cout S3 S2 S1 S0

Y6 Y5 Y4 Y3 Y2

2
Q-3 (19 pts.): Design a synchronous Mealy-type sequential circuit with a single 1 bit input(X) and a
single 1 bit output(Z). The circuit must track the last 3 inputs, and produces a 1 output iff the number
of 1s in the last 3 inputs is more than the number of 0s.

a) (5 pts.) Draw the state diagram using at most 4 states.

1/0 01 1/1
0/0 0/0
00 11 1/1
1/1
10 0/1
0/0

b) (5 pts.) Obtain the state/transition table depicting the state and next state values after state
assignment, as well as any output. Assume the design will use minimum number of state
elements.

Current Next State Output

State X=0 X=1 X=0 X=1
00 00 01 0 0
01 10 11 0 1
10 00 01 0 1
11 10 11 1 1

c) (6 pts.) Obtain the simplified T-type flip-flop input equations and output equation Z by using
K-Map(s).

Current Next State A+B+ TA TB

State
AB X=0 X=1 X=0 X=1 X=0 X=1
00 00 01 0 0 0 1
01 10 11 1 1 1 0
10 00 01 1 1 0 1
11 10 11 0 0 1 0

TA: AB TB: AB Z: AB
X 00 01 11 10 X 00 01 11 10 X 00 01 11 10
0 0 1 0 1 0 0 1 1 0 0 0 0 1 0
1 0 1 0 1 1 1 0 0 1 1 0 1 1 1

TA = A’B + AB’ TB = XB’ + X’B Z = XA + XB + AB

3
d) (3 pts.) Sketch a schematic of your design using T-type flip-flops, AND, OR and NOT gates.

Schematic includes two T-type flip-flops with;

Input equations:
TA = A’B + AB’

TB = XB’ + X’B

Output equation:
Z = XA + XB + AB

4
Q-4 (20 pts.): The provided synchronous INA[7:0] INB[7:0]
datapath is to be used to do the following
calculation using two 8-bit signed 2’s 0 1 0 1
SA SB
complement integers W and Z:
F = 4 x (2W – Z) ENA load D[7:0] D[7:0] load ENB
Each data bus is 8 bits wide. The provided RA (8 bit) RB (8 bit) CLK
control signals are driven by the control unit (not
shown here). RA and RB are registers with x y
AS Adder/
synchronous parallel load capability. RC is a Subtractor
synchronous shift/load register that shifts logical
left by 1 if SH=1, and loads a new value if SH=0.
Other blocks are combinational. The 8 bit D[7:0] shift/
SH
adder/subtractor performs 2’s complement RC (8 bit)
load

arithmetic with AS=1 for addition and AS=0 for

subtraction. F[7:0]

a) (10 pts) If W = 0A and Z = FB (numbers provided in hexadecimal notation), complete the below
simulation waveforms in minimum number of clock cycles, indicating the values required from
the control signals and data signals at each clock cycle in order to calculate F correctly. Enter the
values of the multi-bit signals (INA, INB, RA, RB, F) in hexadecimal. Assume the propagation
delays are all 0 (zero). Stop simulation waveforms when the 8-bit result is obtained for F
computation. Calculate and show all arithmetic values (in hexadecimal format).
CLK

INA[7:0] 0 0A

INB[7:0] 0 FB
1
SA
0

1
SB
0
1
AS
0
1
ENA
0
1
ENB
0

1
SH
0

1
RA[7:0] 0 0A 14
0
1
RB[7:0] 0 0A FB
0

1
F[7:0] 0 14 19 32 64
0

b) (2 pts.) Show how you could possibly add an 8-bit 2-to-1 Multiplexer and one more control
signal, named KEEP, to the datapath in order to be able to retain the stored value of F
over many clock cycles after it is computed (you do not need to redraw the full datapath, but
show only the modified portion.)
Soln:
Previous Input to RC

1 0
KEEP

D[7:0] shift/
SH
load
RC (8 bit) CLK

F[7:0]

5
Q-4 continued:
c) (8 pts.) Assume a Control Unit is to be designed for the provided datapath in (a) with one
command input, CMD. The result obtained by each instruction is depicted in the table on the
right.
CMD F
0 2 x (W + Z)
1 4 x (2W – Z)

Given operands W and Z are available at INA and INB when needed for the operation, show a
Moore State Diagram with minimum number of states to implement the Control Unit. Assume
CMD input to the control unit is stable (unchanged) during the execution of each instruction until
the result is obtained. The initial state is S0, and the machine goes to S0 state after completion
of each instruction. Clearly annotate input/output values on the diagram for full credit.

Soln: Input: CMD Outputs: SA, SB, AS, ENA, ENB, SH

S0
0 1
0,0,0,0,0,0

S1 S2
1,1,0,1,1,0 1,0,0,1,1,0

S3 1 S5
0,1,1,1,1,0 0,
0,0,1,0,0,0
0

S4 S6
0,0,0,0,0,1 0,0,0,0,0,1

6
Q-5 (10 pts.): The component AC specifications on the right apply to the datapath on the left. Assume
routing delays are negligible, and the paths that include the interface data and control signals have
no timing marginality. Show all details of your analysis in answering the below questions for
full credit.
START
DataIn[1:0]
Component AC Timing Specifications
2 (all values in ps)
SELECT 1 0
2
Synchronous tp-min tp-max tsu tho
0 SI SO SI Register A
LOAD EN 2-Bit Loadable =Q[0] 2-Bit Shift Register B 70 120 60 30
SHF
Shift Register A SHF Parallel Load
SHIFT
2 2 Register A
Control 50 100 20 10
Unit and B Shift
STOP CO
Adder Combinational tp-min tp-max
2 2
Adder 220 340
3
2-to-1 MUX 20 30
DataOut[2:0]

a) (5 pts.) What is the maximum possible clock frequency, fmax, that ensures correct data transfer
among the datapath registers in this circuit?

Soln:
Inspecting all paths, worst case path starts with Register A and ends at Register A:
fmax = 1 / Tmin = 1 / [ tp-max,RA + tp-max,Adder + tp-max,MUX + tsu,RA ]
= 1 / [ 120ps + 340ps + 30ps + 60ps ] = 1.82 GHz

b) (5 pts.) What is the worst case hold-timing slack in the circuit?

Soln:
Inspecting all paths, worst case is the shift path from Register A to Register B:
thold-slack = tp-min,RA-shift + tho,RB-shift
= 50 ps – 10 ps = 40 ps

7
Q-6 (20 pts. + 6 BONUS pts.): A given automation monitor tracks every second revolution of a slow
motor. It receives a digital signal, RC, from the motor. Whenever a revolution is completed,
input RC pulses ON (1) for a few seconds and then turns OFF (0) for minutes, until another
rotation is complete. Since the rotational speed varies a lot with load, there could be different
amounts of time between input pulses. The monitor output M turns ON (1) when 2 such
consecutive RC pulses are observed, and turns OFF (0) when the 2nd pulse turns OFF (0). The
next input pulse is the first pulse of the next 2 revolutions. The machine does not use clocks.
a) (6 pts.) Provide a primitive flow table for this machine, and reduce the flow table to
minimum number of states, if your table is not reduced already.

Soln:
Reduced Flow Table (same as Primitive Flow Table):
S+ Output M
Meaning: S RC=0 RC=1 RC=0 RC=1
(0) 1 1 2 0 -
(0,1) 2 3 2 - 0
(0,1,0) 3 3 4 0 -
(0,1,0,1) 4 1 4 - 1

b) (6 pts.) Identify state assignments without critical races, and draw the transition table
together with an output table that avoids false outputs.

Soln:
State assignments without critical races: 1: 00 , 2: 01 , 3: 11 , 4: 10

Transition and output tables, avoiding false outputs:

A+ B+ Output M

AB RC=0 RC=1 RC=0 RC=1

00 00 01 0 0

01 11 01 0 0

11 11 10 0 -

10 00 10 - 1

8
Q-6 continued:
c) (6 pts.) Derive a logic schematic without hazards for the automation monitor using primitive
(AND, OR, inverter) gates.
(2 pts.) Explain how you avoided hazards in your next state equations.

Soln:
Next state and output logic equations (avoiding hazards):
A+ = B.RC’ + A.RC + AB ; B+ = B.RC’ + A’.RC + A’B ; M = A.B’
(schematic skipped here…)
The underlined redundant products have been added to the next state equations to avoid static-
1 hazard when RC changes from 1 to 0 (while A=B=1 for A+ and while B=1 and A=0 for B+)

d) (6 BONUS pts.) Design the automation monitor using one or more SR latches.
Show the details of your work for full credit.

Soln:
(Schematic skipped here…)

SR Excitation
Table: Input Maps:
SB:
Q Q+ SR SA: AB 00 01 11 10
00 0X AB 00 01 11 10 RC
01 10 RC 0 0 X X 0
0 0 1 X 0
10 01 1 1 X 0 0
11 X0 1 0 0 X X RB:
RA: AB
AB 00 01 11 10
In/Out Equations:
00 01 11 10 RC
SA= B.RC’ RC 0 X 0 0 X
RA= B’.RC’ 0 X 0 0 1
SB= A’.RC 1 0 0 1 X
RB= A.RC 1 X X 0 0
M = A.B’