Reg. No.

B.Tech. DEGREE EXAMINATION, NOVEMBER 2017

Third/Fourth/Fifth S emester

158C3258_ DIGITAL LOGIC DESIGN WITH PLDS AND VHDL

(For the candidates admitted during the acadentic year 2015
Note:
- 2a16 onwards)

(i) Part' A should be answered in OMR sheet within first 45 minutes and OMR sheet should be handed
over to hall invigilator at the end of 45n minute.
(ir) Part - B and Part - C should be answered in answer booklet.

Time: Three Hours Max. Marks: 100

PART-A(20x1=20Marks)
Answer ALL Questions
1. The logical expression abcd + abc7 is equivalent to
(A) abd (B) ab
(c) abi (D) oi
2. How many select lines are required to make a 64x1 multiplexer?
(A) 2 (B) 4
(c) 6 (D) None
3- Identify the output state of the tri-state inverter shown below. When A=0, E =0, Z
=?
E
t'

A _j rL
>__z
(A) 0 (B) Hi-Z
(c) 1 (D) ..x))

4. The output of the circuit is always

1 *----A
)-'---
AlLr 1 I Lr
r
(A) A (B) V
(c) 1 (D) 0

5. If the JK flipflop can be operated as a toggle flipflop. Apply a 10 kIIz clock signal and
determine the frequency of Q output.
(A) 5 kHz square wave (B) 10 kllz square wave
(C) 2lkllz square wave (D) None

6. The characteristic equation for SR flip flop is

(A) Qn+t = sg + a (B) en+t = sg + ng
(c) en+l= s + eR (D) Qn+r = se+ R

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 7 . The content of a 4-brtregister is initially101. The register is shifted 6 time to the right with
1

serial input being 101101. What is the content of the register after each shift?
iol 1rior;r 11i0011;1010;0101;1111) (B) (t t to;ot 11;1011;1101;0110;1011)
(C) (t t t t;t 101;1001;1110;l 11 1;1010) (D) (ooot;Ooto;0011;0100;0101;01 10)

8. For Mealy circuit

(A) The output dePends on both the (B) The output depends on either present state
present state and Present inPuts or present inPuts
(C) The butput dePends on both the (D) The output depends only on present state
present state and clock inPuts

9. CPLD is an acroym for

(A) Computer Programmable Logic (B) Complement Programmable Logic Device
Device
(C) Complex Programmable Logic (D) CMOS Programmable Logic Device
Device
10. The content of a simple PLD's consists of
(A) Fuse link arrays (B) Thousand of basic logic gates
iCi Advanced sequential logic function (D) Thousand of basic iogic gates and
advanced sequential logic function

11. The storage element for a static RAM is

(A) Diode (B) Resistor
(C) Capacitor (D) Flipflop

12. The number of cLB's available in xilinx xc303A, 3030L, 31304

(A) t44 (B) t20
(c) e6 (D) 100

t3. In VHDL, which object are used to connect entities together for the model formation?
(A) Constant (B) Variable
ici Signal (D) All of the above

14. The default range of integer data types supported in VHDL

(A) - 2, 647,483,147 1s +2,647,483,t47 (B) -2'147'483'647 to +2'147'483'647
- 2,483,147,647 1s *2,483,147,647 (D) - 2.147,647,483 to
(c) *2'147,647,483

15. An anti fuse prograrnming technolory is predominantly associated with

(A) CPLDs (B) SPLDs
(C) FPGAs (D) Al1of the above

16. Find x, y when a: 0001, b : 1001, c: 1100. fnote: x is the inout bit vector]
Architecture ar of oa is
Begin
xe a and b;y:x or c;
end ar;
(A) 1101, 1100 (B) 1100, 1101
(c) 1101, 0001 (D) 0001,1101

22NF3/4/515EC3258
Page 2 of5
 17. Identify the following program
entity find is port (a, b, c, d: in bit; x,!, w, z: ofibrt);
end find;
architecture ar of find is begin
xe a; y€ a xor b; w€ b xor c; ze c xor d;
end ar;
(A) Binary to gray code converter
(B) Gray to binary code converter
(C) Binary to excess-3 converter (D) Excess-3 to binary converter
18. Determine the number of flip flop that would be required to build the following counters:
mod-6, mod-l1, mod-15, mod-19, mod-31.
(A) 2,4,4,5,5 (B) 3,5,5,4,4
(c) 3,4,4,5,5 (D) 5,5,3,4,4
19. Find the value of y, when a : 1111, b : 1111 architecture mul of twoip is
Begin
]€axb;
end mul;
(A) 11100001 (B) 11000011
(c) 10000010 (D) 11i11100

20. Find the value of SO? When DI:01010101. [Note: S is the inout unsigned vector]
architecture ar of shifting is
begin S e DI rol 1; SO eS ror 3;
end ar;
(A) 010101xx (B) )k101010
(c) 01010101 (D) 10101010

PART-B(5x4=20Marks)
Answer AI\IY FM Questions

21. Define:Hazard. Eliminate the static 'ol" hazardfor the given circuit.
A
C

nF

C
22. With the state diagram as example, list the difference between Mealy and Moore circuit.

23.i. Write a short notes on PROM.

ii. Implement the Boolean function using PAL F =lm(2,12,13).

24. Listthe types of operator available in VHDL and explain any two.

25. Explainthe package in VHDL.

26. Write a VHDL code for D-flip flop.

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 27. Desigoa single bit comparator and write the VHDL code for the same.

PART - C (5 x 12 =60 Marks)

Answer ALL Questions

28. a.i. Explain Reed Muller expansion theorem with an example. (4 Marks)

ii. By applying the Shannon's expansion theorem implement the following function using one
2xl multiplexer and logic gates. F - X'Y'Z'+ X'Y'Z'+ X'YZ + XY'Z'+ XY'2. (8 Marks)
(oR)
b.i. Simpliff the following Boolean equation and eliminate the consensus terms.
4 = A'C'+ ABD + BC'D + AB'D'+ ABCD'
Fz=A'B+ABD+AB'CD'+BC

ii. With the design example, explain how multiplexer is working as logic function generator.

29. a. A sequential circuit has one input (X) and one output (Z). The circuit produces an output
Z:! ior the input sequence 101. Find the Mealy state graph and design the circuit using D-
flip flop.
X = 001 101 1001010100
Z =00AA010000010100

(oR)
b. Design a synchronous 3-bit gray code up-counter using JK flip flops.

30. a. With a neat sketch explain the Xilinx 4000 architecture.

(oR)
b. Design the synchronous sequential circuit for the given state diagram with D-flip flop and
implement using PALI 6R6.

31. a.i. What is an entity in VHDL? (3 Marks)

ii. What is the significance of architecture declaration in VHDL? (3 Marks)

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 iii. Define process statement and list its types and explain any two. (6 Marks)

(oR)
b.i. Explain the different types of data objects present in VHDL.

ii. Distinguish between concurrent and sequential signal assignment with e6ample.

32. a. Develop a VHDL program for BCD adder using full adders and logic gates as a cgmponent.

(oR)
b.i. Write a VHDL program for 3x8 decoder with enable input in dataflow modeling.

ii. Write a VHDL program for 4-bit up/down counter in behavioral modeling.

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