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INTERPOSE_UK
Advanced Integrated Circuit Interposers for Semiconductor
Packaging in the UK

An Introduction to Heterogeneous Integration

Ian Sturland

Image: Southampton University

© 2024. All Rights Reserved.
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IMAPS Interposer Workshop

Scope
• Introduction to Heterogeneous Integration
• State of the Art
• Semiconductor Roadmaps
• Introduction to Interposers
• UK Semiconductor Strategy
• State of the art vs what’s required to support UK Electronics Scene

UK Interpose Consortium
• Who, what, when and why

Finally the ask

• What can you offer in terms of help and guidance?

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eps.ieee.org/hir

https://doi.org/10.1007/978-3-319-51482-6_16

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Why have Chips stopped getting bigger?
Chip approach limits:
• Yield
• Complexity
• Cost

From: www.keysight.com

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 Roadmaps

CHAPTER 1: HETEROGENEOUS INTEGRATION ROADMAP – OVERVIEW CHAPTER 13: CO DESIGN FOR HETEROGENEOUS INTEGRATION

CHAPTER 2: HIGH PERFORMANCE COMPUTING AND DATA CENTERS CHAPTER 14: MODELING AND SIMULATION

CHAPTER 3: THE INTERNET OF THINGS (IOT) CHAPTER 15: MATERIALS AND EMERGING RESEARCH MATERIALS

CHAPTER 4: MEDICAL, HEALTH & WEARABLES CHAPTER 16: EMERGING RESEARCH DEVICES

CHAPTER 5: AUTOMOTIVE CHAPTER 17: TEST TECHNOLOGY

CHAPTER 6: AEROSPACE AND DEFENSE CHAPTER 18: SUPPLY CHAIN

CHAPTER 7: MOBILE CHAPTER 19: SECURITY

CHAPTER 8: SINGLE CHIP AND MULTI CHIP INTEGRATION CHAPTER 20: THERMAL

CHAPTER 9: INTEGRATED PHOTONICS CHAPTER 21: SIP AND MODULE SYSTEM INTEGRATION

CHAPTER 10: INTEGRATED POWER ELECTRONICS CHAPTER 22: INTERCONNECTS FOR 2D AND 3D ARCHITECTURES

CHAPTER 11: MEMS AND SENSOR INTEGRATION CHAPTER 23: WAFER‐LEVEL PACKAGING (WLP)

CHAPTER 12: 5G COMMUNICATIONS

From eps.ieee.org/hir

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 Heterogeneous Integration
• Being pursued aggressively by Tier 1 Semiconductor Vendors TSMC, INTEL etc

• R&D spending in this area 100’s million dollars

• Closed Shop – developing proprietary process for their next generation AI, Graphic and advanced Processor Chips

Intel Samsung
AMD

What does that mean for the rest of the semiconductor /packaging industry?

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 UK Market Potential – Long Tail Approach
• UK electronics market characterized by broad array of companies that target a wide range of
opportunities.
• Consortia considering a 'long tail' approach to the market.
• Providing low volumes to many customer segments, instead of providing large volumes in single popular
segments.

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 UK Semiconductor Strategy

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Chiplets are Becoming a Reality…

Exploitation
• Separate out functional blocks into simpler cheaper modular
die. Cadence Intel
• Standardise the physical, electrical and software interface
between them.
• Because they are new- developed largely on modern processes
increasingly likely to come with fine pitch interconnect and
micropillar terminations.
• If chiplets become “the norm” they become the driver for widespread
use of Interposers.

DARPA

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 What is an Interposer?

Stacked Bare Die/Chiplet

Bare Die/Chiplet
Stacked Bare Die/Chiplet

Interposer
Bare Die/Chiplet

Substrate (e.g. BGA)

Interposer

PCB PCB

Bonded to PCB via BGA Substrate Directly bonded to PCB

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 Interposers
Tend to be silicon, glass or polymer potentially other materials (sapphire/alumina, silicon carbide)

Enables
• Finer geometry interconnect.
• More complex interconnect routing (Redistribution layers –RDL’s).
• Access to most modern chips and chiplets.
• Greater levels of integration (Silicon digital and or analogue, MEMS, photonics, RF, power).
• Improved Size weight and Power (SWaP).
• Improved heat sinking (application specific).

Just think of it as an advanced substrate.

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 Substrates and Interconnect: Tracking 12

PCB

Hybrid

FR4, Polyimides, Advanced

substrates: LCP etc Wafer

Ceramic, Alumina,
Aluminium Nitride
Polymer
Silicon, Glass, GaAs/GaN/InP…SiC,
Sapphire, Diamond

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Substrates and Interconnect: Vertical connections

Lau et al Microelec Electronic

epec Inseto DS-HiMetal Packaging (2014) 11, 16-24

Results in Smaller packages, higher speed, more complex interconnect

Plated Through Hole Wire Bond Solder Ball Copper Bumps/Pillars Micro-Pumps Through Silicon or Glass Vias RDL’s
Typ >200um diam Typ. 25um wire 800 to ca 60um 100um down to 10um diam 50um down to ca 1um can be <1um
typ 400um pitch Typ 100um pitch Down to 100um Typ 200 pitch down to ca 20um typ 2x diam can be <1um

Also note:
• Cu resistivity and thermal conductivity
• Superior to solder

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Cross-section Through Packaged Demonstrator

Lau et al Microelec Electronic Packaging (2014) 11, 16-24

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 INTERPOSE – UK

Partners
• BAE Systems: Project lead, silicon interposer fabrication, and overall project management.
• University of Southampton: Interposer technology development, electroplating, and planarisation processes.
• Oxford Lasers Ltd: Laser processing development for glass interposers.
• PRP Optoelectronics Ltd: Application of interposer technology to micro-LED displays and other demonstrators.

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 Short high impact project to improve UK supply Chain

Oxford Lasers
Demonstrate Silicon Interposer
• Through silicon vias
• Copper filled vias
• Single level RDL each side target >10:1 aspect ratio ca <20um dia via
Plated copper fully filled
Demonstrate Glass Interposer RDL modest >5um features
• Through Glass vias
• Copper filled vias

Southampton Uni
• Single level RDL each side

Demonstrate integration of compound semi device and Si ASIC using interposer

• High reliability
• Cost effective – allows reuse of ASIC over many applications PRP presentation
Later!
Reach out to Supply Chain
• Understand/identify candidate applications

Southampton Uni
• Understand/identify future requirements Workshop discussions
Later!

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 Niche Packaging Exemplars

MEMS RF

Combined cap
and interposer

From 3DGSinc.com

Adapted from Microsystems & Nanoengineering (2015) 1, 15005

• Capping layer provides both interposer and cavity. • Inductors, compact filters, heat-spreader
• Eliminating wire bonds between MEMS and ASIC
results in lower and more stable parasitic capacitance
and sensitivity to wire bond movement under
vibration.
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What is the Desired Supply Chain?

Bump bare die

PDK Interposer Fab & Chiplets etc to
Interposer

Other wafer level

process steps?

Packaging House

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What can you Offer in Terms of Help and Direction?

From your perspective? What does this mean for Interposer technology?
• End User • Material, size, shape, thickness
• System Integrator /Design House • Interconnect complexity
• PCB Manufacture • Spatial resolution
• Packaging House • Number of RDL layers
• Metal connection
• Via size
What are your future pinch points? • Security of supply
• SWaP (AC) • Environmental
• Access to advanced devices or substrates
• Interconnect complexity
• Thermal Management
• Security of supply
• Environmental

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