AEC LAB Manual For Students Experiment 1,2,3
AEC LAB Manual For Students Experiment 1,2,3
Analog Circuits
Lab Manual
(Course Code: 22EC2403)
Prepared By
Dr. Gayathri K M
Associate Professor
Vision
To create innovative Engineers and Entrepreneurs with technological excellence,
professional commitment and social responsibility for serving national and global needs.
Mission
Inculcate Academic Excellence through innovative teaching and learning processes and
espousing appropriate pedagogical parameters.
Reinforce the Students with desired technical aptitude, entrepreneurial and leadership skill
sets enabling them to face the challenges of globalization and technological sophistication.
NEGATIVE CLIPPING
Parallel Clipping
DESIGN:
Assume Forward Resistance of Diode, Rf =100 Ω;
Reverse Resistance of Diode, Rr =1MΩ
The series resistance is calculated such that 𝑅𝑅 = �𝑅𝑅𝑓𝑓 . 𝑅𝑅𝑟𝑟 = 10𝐾𝐾𝐾𝐾
Note: If you are using 1N4001 Rf and Rr may be assumed to be 30 Ω and 300K Ω respectively
and R=3.3 K Ω The series resistor is used to limit the current through the diode.
PROCEDURE:
1. Connections are made as per the above explained circuit diagrams – 12 circuits.
2. Apply a 10V peak to peak sinusoidal wave input with a suitable frequency of 1KHz
3. Adjust the reference DC voltage VR to some convenient values. Note the changes in the
Output due to variations in the reference voltage VR = 0V, 2V, etc.
4. Observe the output waveform in the CRO and Obtain the transfer characteristics of Clipper
circuit, by keeping CRO in X-Y mode.
5. Repeat the same procedure for other circuits and note down the waveforms against
the circuits.
RESULT:
Different combinations of clipping circuits are implemented and waveforms observed.
EXPERIMENT 2.
DIODE CLAMPING CIRCUITS
Aim: To construct and test different clamping circuits
Apparatus:
Bread board
Regulated dual power
supply Function generator
Resistors Connecting wires CRO
Diodes
Theory:
A clamping circuit adds a d.c component to the signal in such a way that it pushes the signal either on the positive
side or on the negative side. When the circuit pushes the signal on the positive side then the negative peak of the
signal falls on the zero level, this circuit is called a positive clamper. When the circuit pushes the signal on the
negative side, this is called a negative clamper circuit.
Circuit Diagram:
Negative Clamping
Positive Clamping
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Note down the output on CRO.
3. Use the dc/ac switch of CRO to calculate the added dc level to the wave.
Observation Table:
Clamper
Positive
Negative
Waveform:
RESULT:
Different combinations of clamping circuits are implemented and waveforms observed.
INFERENCE:
EXPERIMENT 3:
Aim: To design and measure the gain-frequency response, input impedance and output impedance of
CE R-C coupled Amplifier for the following specifications:
Given IC=1.5mA, VCC=15V, β = 100
Apparatus:
BC 107
Function generator
(1MHz) AC
millivoltmeter
Regulated power supply (0-30) V
Resistors- based on design
Capacitors
Bread board
Cathode Ray Oscilloscope Connecting wires
THEORY:
The CE configuration is widely used as a basic amplifier as it has both voltages and current
amplification. The resistors R1 and R2 provide required biasing conditions. The circuit is designed
such that the transistor operates in a linear active region and Vmax peak to peak output signals are
possible. Resistors R1 and R2 form a voltage divider network across the base of the transistor. The
function of this network is to provide necessary biasing in order to operate the transistor as an
amplifier, thus keeping the operating point in the active region.
For an amplifier the Q point is to be placed such that the load line is bisected; therefore the
Vce is set to Vcc/2. The emitter resistor Re is required to obtain the DC quiescent stability. However
the inclusion of Re in the circuit causes a decrease in amplification at higher frequency in order to
avoid such a condition it is bypassed by a capacitor so that it acts as short circuit for ac and
contributes stability for DC quiescent conditions. Hence a capacitor is connected in parallel with
emitter resistance.
The bypass capacitor (Emitter bypass capacitor) is used to short circuit the emitter resistance
and thus increase the gain at higher frequency. The coupling capacitors cause the fall off in the low
frequency response of the amplifier
The input impedance = VS-VI/R
The output impedance = Resistance at which voltage equal to Vo/2
Amplifier Operation
Once the Q-point is fixed through DC bias, an AC signal is applied at the input using coupling capacitor
C1. During the positive half cycle of the signal VBE increases leading to increased IB. Therefore IC
increases by times leading to decrease in the output voltage, VCE. Thus the CE amplifier produces an
amplified output with a phase reversal. The voltage Gain of the common emitter amplifier is equal to the
ratio of the change in the output voltage to the change in the input voltage. Thus, Av= Vout/Vin
The input (Zi) and output (Zo) impedances of the circuit can be computed for the case when the emitter
resistor RE is completely bypassed by the capacitor, CE:
Zi = R1 ||R2||βre and Zo = RC||r0
where re (26mV/IE) and ro are the emitter diode resistance and output dynamic resistance (can be
determined from output characteristics of the transistor). Usually ro_10 RC, thus the gain can be
approximated as Av = Vout/Vin = -βIB(Rc||r0) /βIBre = -Rc/re
The negative sign accounts for the phase reversal at the output.
The performance of an amplifier is characterized by its frequency response curve that shows output
amplitude (or, more often, voltage gain) plotted versus frequency (often in log scale). Typical plot of the
voltage gain of an amplifier versus frequency is shown in the figure below. The frequency response of an
amplifier can be divided into three frequency ranges. The frequency response begins with the lower
frequency range designated between 0 Hz and lower cutoff frequency. At lower cutoff frequency, fL , the
gain is equal to 0.707 Amid. Amid is a constant mid-band gain obtained from the mid-frequency range. Third,
the higher frequency range covers frequency between upper cutoff frequency and above. Similarly, at
higher cutoff frequency, fH, the gain is equal to 0.707 Amid. Beyond this the gain decreases with frequency
increases and dies off eventually.
Design:Can be done as per the steps shown below OR using the Thevenin's equivalent circuit and
the expression for stability factor.
𝑉𝑉𝑐𝑐𝑐𝑐 15
Let 𝑉𝑉𝐸𝐸 = = = 1.5 𝑉𝑉
10 10
To find R1 and R2
𝑉𝑉𝐵𝐵 = 𝑉𝑉𝐸𝐸 + 𝑉𝑉𝐵𝐵𝐵𝐵 = 2.2𝑉𝑉
𝑉𝑉𝐵𝐵 2.2
𝑅𝑅2 = = = 16.29𝐾𝐾𝐾𝐾
9 ∗ 𝐼𝐼𝐵𝐵 9 ∗ 15𝜇𝜇
Use R2 = 10Kohm
To find RC:
𝑉𝑉𝐶𝐶𝐶𝐶 = 𝑉𝑉𝐶𝐶𝐶𝐶 − 𝐼𝐼𝐶𝐶 𝑅𝑅𝐶𝐶 − 𝑉𝑉𝑅𝑅𝑅𝑅
= 4Kohm
Use RC = 4.7Kohm
1
𝑋𝑋𝑐𝑐1 = ≤ 0.11𝐾𝐾𝐾𝐾
2𝜋𝜋 ∗ 200 ∗ C1
To find C2:
𝑍𝑍𝑜𝑜
𝑋𝑋𝑐𝑐2 ≤
10
Zo = RC = 4.7KΩ
1 𝑍𝑍𝑜𝑜 4.7 𝐾𝐾𝐾𝐾
𝑋𝑋𝑐𝑐2 = ≤ =
2𝜋𝜋𝜋𝜋𝐶𝐶2 10 10
C2 ≥ 112.87μF- Select C2 = 100μF
𝑅𝑅𝐸𝐸
To find CE : 𝑋𝑋𝐶𝐶𝐶𝐶 ≤
10
1 𝑅𝑅𝐸𝐸
≤ ⇒
2𝜋𝜋𝜋𝜋𝐶𝐶𝐸𝐸 10
10
𝐶𝐶𝐸𝐸 ≥
2𝜋𝜋𝜋𝜋 𝑅𝑅𝐸𝐸
10
𝐶𝐶𝐸𝐸 =
2𝜋𝜋 ∗ 100 ∗ 1𝐾𝐾
PROCEDURE: -
Method 1 to find input and output impedance
1. The amplifier circuit is rigged up.
2. The input frequency is kept constant at 1 KHz, the voltage Vin less than Vinmax is applied.
For Input Impedance:
3. The DRB in zero ohms position is connected in series with the input as shown in the figure.
4. The DRB is increased until the output becomes half of the previous value with the same input
voltage as in step 2.
5. The DRB resistance will give the input impedance of the amplifier.
For Output Impedance:
6..The DRB in maximum position (say 100KΩ) is connected across the output terminals as shown in
the figure.
7. The DRB is reduced until the output becomes half of the previous value with the same input
voltage as in step 2.
8. The DRB resistance will give the output impedance of the amplifier.
Procedure to plot the frequency response
1. Measure and record all the values of resistance and capacitance of the transistor using a
multimeter. Configure the circuit as per the diagram.
2. Apply supply voltage to the circuit. Measure and record all the dc parameters listed inTable 1 in
absence of the ac signal.
3. Next, set the function generator in 20 Hz “Frequency” range. Also, set the “Attenuation”button at
40dB. Connect the output to the oscilloscope and adjust the “Amplitude” knob till you get a
sinusoidal input signal, Vi _ 100-200 mV peak-to-peak value. DO NOT CHANGE THIS
SETTING THROUGHOUT THE EXPERIMENT.
4. Now apply this input signal to the circuit you have made keeping the connection to the
oscilloscope intact. Feed the output of the circuit to the other channel of the oscilloscope.
***Take care to make all the ground pins common***
5. With input signal amplitude always constant, increase signal frequency slowly. Observe,measure
and record the output voltage, Vo. Scan the entire frequency in the range 20 Hz –2 MHz. You may
have to measure Vi and take the ratio Vo/Vi each time in case input fluctuation is too large to hold
constant.
6. Calculate the voltage gain for each frequency. Observe the inverted output.
7. Plot the frequency response curve, i.e. voltage gain in dB versus frequency on a semi-log graph-
sheet.
8. Estimate the mid-frequency gain and also the lower and higher cut off frequencies and hence the
bandwidth.
Frequency Response : Vin = 20mV
RESULT: Designed CE self-bias amplifier by calculating the required values of R1, R2, RE,
Rc and measured input & output impedance and the frequency response
INFERENCE: