EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS

UNIT-II
AMPLIFIERS
Load line, operating point, biasing methods for BJT and MOSFET, BJT small signal model – Analysis
of CE, CB, CC amplifiers- Gain and frequency response –MOSFET small signal model– Analysis of
CS, CG and Source follower – Gain and frequency response- High frequency analysis.
Biasing:
1. Biasing means the proper selection of the operating point or maintenance of proper level of DC voltage
and currents in the transistor.
2. In order to operate transistor in the desired region we have to apply external dc voltages of correct
polarity and magnitude to the two junctions of the transistor.
3. Because DC voltages are used to bias the transistor , biasing is known as dc biasing of the transistor.
Need for Biasing BJT:
1. When an input AC signal is only supplied to the circuit (without any DC) as shown in fig 1.1(a),
during positive half cycle of input (𝑉𝑖𝑛 > 𝑉𝐵 ) then input junction becomes forward biased results in
current flows from emitter to base , then base to collector circuit.
2. During negative half cycle of input,the junction becomes reverse biased, so no current flows in the
circuit results in negative cycle is not amplified as shown in fig 1.1(b).
3. The resultant output is theunfaithful or distorted (i.e input and output shape are not same).

Fig 1.1(a) Fig 1.1(b)

4. Thus, to obtain faithful amplification the following three conditions needs to be satisfied.
i) The base–emitter junction mustbe forward-biased (p-region voltage more positive), with a
resulting forward-bias voltage of about 0.6 to 0.7 V.
ii) The base–collector junction mustbe reverse-biased (n-region more positive), with the
reverse-bias voltage being any value within the maximum limits of the device.
iii) There should be proper zero signal (i.e., ac input is present or not) collector current.
5. Transistor can be operated in 3 regions as shown in Table 1.1.
Region of operation Emitter- Base Junction Collector- Base Junction
Cut-off region Reverse biased Reverse biased
Active region Forward biased Reverse biased
Saturation region Forward biased Forward biased
Table 1.1
DC operating point or Quiescent point or Q-Point:
1. The intersection of the load- line with the transistor
output characteristic for a particular 𝐼𝐵 gives the operating point
𝑄(𝑉𝐶𝐸 , 𝐼𝐶𝐸 ) as shown in fig 1.1 (c).
2. Q-Point may shift : Temperatue change,
Transistor leakage current 𝐼𝐶𝑂 ,
Current gain 𝛽 and
Base-Emitter voltage 𝑉𝐵𝐸

Fig 1.1 (c)

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Selection of Operating Point:
 Let us consider three operating points of transistor operating in common emitter amplifier.
1. Near cut-off region
2. Near saturation region
3. In middle of active region.
Case 1:If the operating point (R) is selected near the cutoff region, then the output is clipped in negative half
cycle as shown in fig1.2 (a)
Case 2:If the operating point (P) is selected near saturation region, then the output is clipped in positive cycle
as shown infig1.2 (b)
Case 3:If the operating point (Q) is selected in the middle of active region, then there is no clipping and the
output follows input faithfully as shown in fig1.2 (C).
If input is large then clipping at both sides will take place.

Fig 1.2(a) Fig1.2 (b)

Fig 1.2 (c)

Variation of Quiescent point(or)Factors Affecting Stability of Q-point:
1. Designing the biasing circuit to stabilize the Q point is known as bias stability.
2. Two important factors are to be considered while designinga circuit which are responsible for shifting
the operating point.
 Temperature
 Transistor Current gain ℎ𝐹𝐸 ⁄𝛽
i) Temperature
1) 𝑰𝑪𝑶 :The flow of current in the circuit produces heat at the junctions.
1. We know that the minority carriers are temperature dependent and they increase, increases the leakage
current 𝐼𝐶𝐸𝑂 ,
∴ 𝑰𝑪𝑬𝑶 = (𝟏 + 𝜷)𝑰𝑪𝑩𝑶 → (𝟏)

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
2. Specifically, 𝐼𝐶𝐵𝑂 doubles for every 10℃ rise in temperature.
3. Increase in 𝐼𝐶𝐸𝑂 in turn increases the collector current,
∴ 𝑰𝑪 = 𝜷𝑰𝑩 + 𝑰𝑪𝑬𝑶 → (𝟐)
4. The increase in the collector current increases the power dissipated
𝑷𝑫 at the collector junction.
5. This, in turn further increase the temperature of the junction and
increases the collector current.
6. The process is cumulative as shown in fig 1.2 (d).
7. The excess heat produced at the collector- base junction may even
burn and destroy the transistor.
8. This situation is called ‘thermal runaway’ of the transistor.
Fig 1.2 (d)
9. For any transistor , maximum power dissipation
is always a fixed value.
10. That is known as maximum power dissipation
rating of a transistor.
11. This value is specified by the manufacturer in
data sheets.
12. The hyperbola gives the maximum power
dissipation transistor as shown in fig 1.2 (e).
13. If this limit is crossed ,the device will fail.

Fig 1.2 (e) Output characteristics of a transistor in common –emitter configuration . Maximum
current , voltage and power ratings are indicated
2) 𝑽𝑩𝑬 :Base to emitter voltage 𝑉𝐵𝐸 changes with temperature at
the rate of 2.5mV/℃.
1. 𝐼𝐵 and𝐼𝐶 depends upon 𝑉𝐵𝐸 as ahown in fig 1.2 (f).
2. Therefore collector current 𝐼𝐶 changes with
temperature due to change in 𝑉𝐵𝐸 .
3. The change in collector current change the operating
point.
3)𝜷𝒅𝒄 : 𝛽𝑑𝑐 of the transistor is also temperature dependent.
1. As 𝛽𝑑𝑐 varies, 𝐼𝐶 also varies, since 𝐼𝐶 = 𝛽𝐼𝐵 as shown
in fig 1.2 (g).
Fig 1.2 (f)
2. The change in collector current change the operating point.
3. Therefore, to avoid thermal instability , the biasing circuit should
be designed to provide a degree of temperature stability i.e. even
though there are temperature changes ,the changes in the transistor
parameters (𝑉𝐶𝐸𝑄 , 𝐼𝐶𝑄 , 𝑃𝐷𝑚𝑎𝑥 ) should be very less so that the
operating point shifting is minimum in the middle of the active
region.

Fig 1.2 (g)

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝒉
ii) Transistor current gain 𝑭𝑬⁄𝜷:
 Even though there is tremendous advancement in
semiconductor technology, there are changes in the
transistor parameters among different units of the same
type ,same number.
 This means if we take two transistor units of same
type and use them in the circuit ,there is change in the 𝛽
value in the actual practice.
 The biasing circuit is designed according to the
required 𝛽 value.
Fig 1.2(h) Graphs showing the collector characteristics for two transistors of the same type
 But due to change in 𝛽from unit to unit , the operating point may shift .
 The common emitter output characteristics for two transistors of the same type.
 The dashed characteristics are for a transistor whose 𝛽 is much larger than that of the transistor
represented by the solid curves.
Stability factor:
 The operating point can be made stable by keeping 𝐼𝐶 and 𝑉𝐶𝐸 constant.
 There are two techniques to make Q-point stable.
 Stabilization techniques
 Compensation techniques
Stabilization techniques:
1. It refer to the use of resistive biasing circuits which allow 𝐼𝐵 to vary so as to keep 𝐼𝐶 relatively
constant, with variations in 𝛽, 𝐼𝐶𝑂 𝑎𝑛𝑑 𝑉𝐵𝐸 .
2. Stability factor is defined asthe rate of change of collector current with respect to the reverse saturation
current, keeping 𝛽 𝑎𝑛𝑑 𝑉𝐵𝐸 constant .
𝝏𝑰 ∆𝑰
i.e.Stability factor𝑺 = 𝝏𝑰 𝑪 ≈ ∆𝑰 𝑪 |𝜷,𝑽𝑩𝑬 = 𝑪𝒐𝒏𝒔𝒕𝒂𝒏𝒕
𝑪𝑶 𝑪𝑶
where𝐼𝐶 = collector current and 𝐼𝐶𝑂 = reverse saturation current
3. Rate of change of collector current𝐼𝐶 with 𝑉𝐵𝐸 , keeping 𝐼𝐶𝑂 𝑎𝑛𝑑 𝛽 constant.
𝝏𝑰 ∆𝑰
i.e,𝑺′ = 𝝏𝑽 𝑪 ≈ ∆𝑽 𝑪 |𝑰𝑪𝑶 ,𝜷= 𝑪𝒐𝒏𝒔𝒕𝒂𝒏𝒕
𝑩𝑬 𝑩𝑬
4. Rate of change of collector current 𝐼𝐶 with 𝛽, keeping 𝐼𝐶𝑂 𝑎𝑛𝑑 𝑉𝐵𝐸 constant.
𝝏𝑰𝑪 ∆𝑰𝑪
i.e,𝑺′′ = ≈ |
𝝏𝜷 ∆𝜷 𝑰𝑪𝑶 ,𝑽𝑩𝑬 = 𝑪𝒐𝒏𝒔𝒕𝒂𝒏𝒕
Smaller is the value of S , higher is the stability.
Expression for stability factor (S):
 When a transistor is biased in the active region of its characteristics , the collector current is related to
the base current by the following expression.
𝐼𝐶 = 𝛽𝐼𝐵 + (1 + 𝛽)𝐼𝐶𝑂 …….(1)
Where 𝐼𝐶 = collector current and 𝐼𝐵 =base current
Differentiating the above equ(1) w.r.t 𝐼𝐶 considering 𝛽 to be constant, we get
𝑑𝐼𝐵 𝑑𝐼𝐶𝑂
1=𝛽 + (1 + 𝛽)
𝑑𝐼𝐶 𝑑𝐼𝐶
𝑑𝐼 1 𝑑𝐼
1 = 𝛽 𝑑𝐼𝐵 + (1 + 𝛽) 𝑆 (𝑠𝑖𝑛𝑐𝑒 𝑆 = 𝑑𝐼 𝐶 )
𝐶 𝐶𝑂

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝑑𝐼𝐵 1
1−𝛽 = (1 + 𝛽)
𝑑𝐼𝐶 𝑆
(𝟏+𝜷)
𝑺= 𝒅𝑰 …..(2)…..(Standard equation)
(𝟏−𝜷 𝑩 )
𝒅𝑰𝑪

Types of BJT biasing:

 Base Resistor method or Fixed- bias or Base -Bias
 Fixed -Bias with Emitter Resistor or Emitter stabilized bias
 Collector to Base bias
 Voltage -divider bias or Self bias or Potential -divider bias
BASE RESISTOR METHOD (OR)FIXED - BIAS (OR) BASE BIAS CIRCUIT:

 In biasing circuit shown in

fig 1.3(a), two different power
supplies are required.
 To avoid the use of two
supplies the base resistance RBis
connected to VCC as shown in fig
1.3(b).
 The voltage 𝑉𝐵𝐸 across the
forward- biased emitter-base
junction is approximately 0.7V for
a Si transistor & 0.3V for a Ge
transistor in the active region.
Fig 1.3
Circuit analysis:
Base circuit of the fixed -bias circuit
Applying KVL to the base circuit as shown in fig 1.3(c), we get,
+VCC − IB R B − VBE = 0
Solving for the current IB ,
𝐕𝐂𝐂 − 𝐕𝐁𝐄
𝐈𝐁 = … … . (1)
𝐑𝐁
Since the supply voltage VCC is usually much larger than VBE we have,
VCC
IB ≈ Fig 1.3 (c)Base circuit
RB
The current IB is constant and the network is called the ‘Fixed -Bias Circuit’.
Collector circuit of the fixed - bias circuit
Applying KVL to the collector circuit as shown in fig 1.3(d), we get,
VCC − IC R C − VCE = 0
∴ VCE = VCC − IC R C ….(2)
The magnitude of collector current is given by ,
𝐼𝐶 = 𝛽𝐼𝐵 ….(3)
From equ (2), we have
𝐕𝐂𝐂 −𝐕𝐂𝐄
𝐈𝐂 = … … (4) Fig 1.3 (d)Collector circuit
𝐑𝐂
By the relation of 𝐼𝐶 = 𝛽𝐼𝐵 ,the magnitude of 𝐼𝐶 is not a function of the resistance R C .

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Changing R C to any level will not affect the level of 𝐼𝐵 or 𝐼𝐶 . However, the level of R C will determine the
magnitude of VCE .
VCE = VC − VE …..(4a)
Where VC =collector voltage ; VE =Emitter voltage
Similarly, VBE = VB − VE …..(4b)
Where VB =Base voltage
In this circuit ,substitutingVE = 0V in (4a) and (4b) , we get
VCE = VC
VBE = VB
Stability factor S:
𝑑𝐼𝐶 (1 + 𝛽)
𝑆= =
𝑑𝐼𝐶𝑂 (1 − 𝛽 𝑑𝐼𝐵 )
𝑑𝐼𝐶
To obtain ‘S’ differentiate the above equ(1)with respect to𝐼𝐶 ,
𝑑𝐼𝐵
= 0becauseVCC,𝑉𝐵𝐸 and R B are constants
𝑑𝐼𝐶
𝑺 = (𝟏 + 𝜷) …….(5)
Stability factor S’ :
𝜕𝐼
𝑆′ = 𝜕𝑉 𝐶 when 𝛽 𝑎𝑛𝑑 𝐼𝐶𝑂 are constant
𝐵𝐸
We know, 𝐼𝐶 = 𝛽𝐼𝐵 + (1 + 𝛽)𝐼𝐶𝑂
𝐼𝐶 −(1+𝛽)𝐼𝐶𝑂
𝐼𝐵 = …….(6)
𝛽
From the base circuit we get ,
VCC = VBE + 𝐼𝐵 R B ….(7)
Substitute the 𝐼𝐵 value in above equ (6),
𝐼𝐶 −(1+𝛽)𝐼𝐶𝑂
VCC = VBE + R B [ ]….(8)
𝛽
Differentiating the above equation w. r.t 𝐼𝐶 we get,
∂VBE 1
0= + R B [𝛽 ]
∂ 𝐼𝐶
1 RB
0= ’+[ ]
𝑆 𝛽
𝜷
𝐒’ = − ….(9)
𝐑𝐁
Stability factor 𝑺′′ :
𝜕𝐼𝐶
𝑆′′ = whenVBE and 𝐼𝐶𝑂 are constant.
𝜕𝛽
Differentiating the above equ(8) w. r.t 𝐼𝐶 we get,
𝜕𝛽
𝛽 − 𝐼𝐶 (𝜕 𝐼 )
𝐶
0 = 0 + RB [ ]
𝛽2
RB 𝐼𝐶
0= 2
[𝛽 − ]
𝛽 𝑆′′
𝑰𝑪
𝑺′′ = Fig 1.3 (e)Common Emitter Output Characteristics with dc load line
𝜷
Load Line And Quiescent Point:
1. The d.c load line is a plot of 𝐼𝐶 versus 𝑉𝐶𝐸 as shown in fig 1.3(e).
2. For different values of 𝐼𝐵 ,we have different intersection points such as P,Q and R.
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
For fixed bias circuit, we have
𝑉𝐶𝐶 − 𝑉𝐶𝐸 𝑉𝐶𝐶 1
𝐼𝐶 = = − [ ] 𝑉𝐶𝐸
𝑅𝐶 𝑅𝐶 𝑅𝐶
1 𝑉𝐶𝐶
𝐼𝐶 = − [ ] 𝑉𝐶𝐸 +
𝑅𝐶 𝑅𝐶
By comparing this equation with equation of straight line y=mx+c, where m is the slope of the line and c is
the intercept on y-axis, then we can draw a straight line on the graph of 𝐼𝐶 versus 𝑉𝐶𝐸 which is having slope
−1⁄ and intercept 𝑉𝐶𝐶⁄ .
𝑅𝐶 𝑅𝐶
 To determine the two points on the line we assume 𝑉𝐶𝐸 = 𝑉𝐶𝐶 and 𝑉𝐶𝐸 = 0 .
 When 𝑉𝐶𝐸 = 𝑉𝐶𝐶 ; 𝐼𝐶 = 0 and we get a point A and
𝑉𝐶𝐶
 When 𝑉𝐶𝐸 = 0 ; 𝐼𝐶 = ⁄𝑅 and we get a point B
𝐶
Advantages:
 Simple circuit
 Maximum flexibility
Disadvantages:
 Operating point is not maintained
 Stabilization is very poor
EMITTER STABILIZED BIAS CIRCUIT (OR) EMITTER BIAS (OR) FIXED-BIAS WITH
EMITTER RESISTOR:
 To improve the stability of biasing circuit over the
fixed bias circuit,the emitter resistance is connected
in the biasing circuit as shown in fig 1.4.
 Such biasing circuit is known as emitter bias circuit.
Circuit Analysis:
Base Circuit:
Applying KVL to the base circuit we get as shown
in fig 1.4 (a),
𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 − 𝐼𝐸 𝑅𝐸 = 0……(1)
We have ,𝐼𝐸 = (1 + 𝛽)𝐼𝐵 Substitute 𝐼𝐸 in equ(1) we get,
𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 − (1 + 𝛽)𝐼𝐵 𝑅𝐸 = 0
∴ 𝑉𝐶𝐶 − 𝑉𝐵𝐸 = 𝐼𝐵 𝑅𝐵 + (1 + 𝛽)𝐼𝐵 𝑅𝐸
𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵 + (1 + 𝛽)𝑅𝐸
𝑽𝑪𝑪 −𝑽𝑩𝑬
𝑰𝑩 = Since𝛽>>1 Fig 1.4Emitter-bias circuit
𝑹𝑩 +𝜷𝑹𝑬
Note that the only difference between the equation for 𝐼𝐵 and that obtained for the fixed-
bias configuration is the term 𝛽𝑅𝐸
𝑉𝐵 = 𝑉𝐵𝐸 + 𝑉𝐸 or𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐵
Since 𝑉𝐸 = 𝐼𝐸 𝑅𝐸
𝑉𝐵 = 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸

Fig 1.4 (a) Base Circuit

Collector Circuit:
Applying KVL to the collector circuit as shown in fig 1.4 (b),
𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐸 − 𝐼𝐸 𝑅𝐸 = 0 Fig 1.4 (b)Collector Circuit

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝐼𝐸 𝑅𝐸
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 )
𝑉𝐸 = 𝐼𝐸 𝑅𝐸
𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸
𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶

Stability improvement:
The addition of emitter resistance 𝑅𝐸 in the emitter bias circuit provides improved stability , i.e, the dc bias
currents and voltages remain closer to where they were set by the circuit when outside conditions , such as
temperature and transistor β , change.

COLLECTOR TO BASE BIAS:

 It is an improvement over the fixed-bias method.
 In this the biasing resistor is connected between the collector
and the base of the transistor to provide a feedback path as
shown in fig 1.5.
 Thus IB flows through R B and (IC + IB ) flows through the
RC.
Circuit Analysis:
Base Circuit:
Applying KVL to the base circuit as shown in fig 1.5,
𝑉𝐶𝐶 − (𝐼𝐶 + 𝐼𝐵 )𝑅𝐶 − 𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 = 0…..(1)
∴ 𝑉𝐶𝐶 = (𝑅𝐵 + 𝑅𝐶 )𝐼𝐵 + 𝐼𝐶 𝑅𝐶 + 𝑉𝐵𝐸 ……..(2)Fig 1.5 DC bias with voltage feedback
𝑽𝑪𝑪 −𝑽𝑩𝑬 −𝑰𝑪 𝑹𝑪
𝑰𝑩 = …….(3)
𝑹𝑪 +𝑹𝑩
Substitute 𝐼𝐶 = 𝛽𝐼𝐵 in equ(2)
𝑉𝐶𝐶 = (𝑅𝐵 + 𝑅𝐶 )𝐼𝐵 + 𝛽𝐼𝐵 𝑅𝐶 + 𝑉𝐵𝐸
𝑉𝐶𝐶 −𝑉𝐵𝐸
𝐼𝐵 = 𝑅 ….(4)
𝐵 +(1+𝛽)𝑅𝐶
𝑽𝑪𝑪 −𝑽𝑩𝑬
𝑰𝑩 = since𝛽 ≫ 1
𝑹𝑩 +𝜷𝑹𝑪
Collector Circuit:
Applying KVL to the collector circuit as shown in fig 1.5,
𝑉𝐶𝐶 − (𝐼𝐶 + 𝐼𝐵 )𝑅𝐶 − 𝑉𝐶𝐸 = 0
∴ 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − (𝐼𝐶 + 𝐼𝐵 )𝑅𝐶
Modified Collector to Base bias:
To further improve the level of stability, the emitter resistance is
connected in this circuit as shown in fig 1.5 (a).
Base Circuit:
Applying KVL to the base circuit as shown in fig 1.5(a),
𝑉𝐶𝐶 − (𝐼𝐶 + 𝐼𝐵 )𝑅𝐶 − 𝐼𝐵 𝑅𝐵 − 𝑉𝐵𝐸 − 𝐼𝐸 𝑅𝐸 = 0
∴ 𝑉𝐶𝐶 − 𝑉𝐵𝐸 = (1 + 𝛽)𝐼𝐵 𝑅𝐶 + 𝐼𝐵 𝑅𝐵 + (1 + 𝛽)𝐼𝐵 𝑅𝐸 (since 𝐼𝐸 = (1 + 𝛽)𝐼𝐵 )
Fig 1.5 (a) Modified D.C bias with voltage feedback
𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵 + (1 + 𝛽)(𝑅𝐶 + 𝑅𝐸 )
𝑽𝑪𝑪 −𝑽𝑩𝑬
𝑰𝑩 = since𝜷 ≫ 𝟏
𝑹𝑩 +𝜷(𝑹𝑪 +𝑹𝑬 )

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
In general we can say that,
𝑽′
𝑰𝑩 =
𝑹𝑩 + 𝜷𝑹′
Where 𝑉 ′ = 𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝑅 ′ = 0 for fixed bias
𝑅 ′ = 𝑅𝐸 for emitter bias
𝑅 ′ = 𝑅𝐶 for collector to base bias
𝑅 ′ = 𝑅𝐶 +𝑅𝐸 for collector to base bias with 𝑅𝐸
Collector Circuit:
Applying KVL to the collector circuitas shown in fig 1.5(a),
𝑉𝐶𝐶 − (𝐼𝐶 + 𝐼𝐵 )𝑅𝐶 − 𝑉𝐶𝐸 − 𝐼𝐸 𝑅𝐸 = 0
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐸 (𝑅𝐶 + 𝑅𝐸 ) (since 𝐼𝐸 = 𝐼𝐶 + 𝐼𝐵 )
From equ (3) Since 𝑉𝐵𝐸 is almost independent of collector current , hence it is neglected from the above
equation
𝑉𝐶𝐶 −𝐼𝐶 𝑅𝐶
Thus,𝐼𝐵 =
𝑅𝐶 +𝑅𝐵
Differentiate the above equation w.r.t. 𝐼𝐶 we get
𝑑𝐼𝐵 𝑅𝐶
=0− → (5)
𝑑𝐼𝐶 𝑅𝐶 + 𝑅𝐵
Stability factor S:
1+𝛽
We know 𝑆 = 𝑑𝐼
1−𝛽 𝐵
𝑑𝐼𝐶
𝑑𝐼𝐵
Substituting the value of in the above equation, we get
𝑑𝐼𝐶
𝟏+𝜷
𝑺= 𝑹𝑪
→ (6)
𝟏 + 𝜷 (𝑹 )
𝑪 +𝑹𝑩
Collector to base bias circuit provides better stability than fixed bias circuit.
Stabilization with changes in 𝜷:
The equ (6) shows that the stability factor S for this circuit also depends on 𝛽.
But if we design the circuit with condition 𝛽𝑅𝐶 ≫ 𝑅𝐵 then we can make stability factor independent of 𝛽.
We know ,𝐼𝐶 = 𝛽𝐼𝐵 + (1 + 𝛽)𝐼𝐶𝑂
𝐼𝐶 − (1 + 𝛽)𝐼𝐶𝑂
𝐼𝐵 =
𝛽
From equ (2)we can write,
−𝑉𝐶𝐶 + 𝐼𝐵 (𝑅𝐶 + 𝑅𝐵 ) + 𝐼𝐶 𝑅𝐶 + 𝑉𝐵𝐸 = 0
Substituting the value of 𝐼𝐵 in above equation
𝐼𝐶 − (1 + 𝛽)𝐼𝐶𝑂
−𝑉𝐶𝐶 + [ ] (𝑅𝐶 + 𝑅𝐵 ) + 𝐼𝐶 𝑅𝐶 + 𝑉𝐵𝐸 = 0
𝛽
Multiplying by 𝛽 on both sides we get,
−𝛽𝑉𝐶𝐶 + 𝐼𝐶 (𝑅𝐶 + 𝑅𝐵 ) − (1 + 𝛽)𝐼𝐶𝑂 (𝑅𝐶 + 𝑅𝐵 ) + 𝛽𝐼𝐶 𝑅𝐶 + 𝛽𝑉𝐵𝐸 = 0
𝐼𝐶 (𝑅𝐶 + 𝑅𝐵 + 𝛽𝑅𝐶 ) = [𝛽𝑉𝐶𝐶 + (1 + 𝛽)𝐼𝐶𝑂 (𝑅𝐶 + 𝑅𝐵 ) − 𝛽𝑉𝐵𝐸 ]
As 𝛽 ≫ 1, 1 + 𝛽 ≈ 𝛽
𝐼𝐶 (𝑅𝐵 + 𝛽𝑅𝐶 ) ≈ 𝛽[𝑉𝐶𝐶 − 𝑉𝐵𝐸 + 𝐼𝐶𝑂 (𝑅𝐶 + 𝑅𝐵 )]
𝛽[𝑉𝐶𝐶 − 𝑉𝐵𝐸 + 𝐼𝐶𝑂 (𝑅𝐶 + 𝑅𝐵 )]
𝐼𝐶 ≈
(𝑅𝐵 + 𝛽𝑅𝐶 )
Assume 𝛽𝑅𝐶 ≫ 𝑅𝐵 , then the above equation becomes,

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝑉𝐶𝐶 − 𝑉𝐵𝐸 + 𝐼𝐶𝑂 (𝑅𝐶 + 𝑅𝐵 )
𝐼𝐶 ≈
𝑅𝐶
STABILITY FACTOR𝑺′:
𝜕𝐼
We know𝑆′ = 𝜕𝑉 𝐶 | when 𝐼𝐶𝑂 𝑎𝑛𝑑 𝛽 constant.
𝐵𝐸
𝑉𝐶𝐶 −𝐼𝐶 𝑅𝐶 −𝑉𝐵𝐸
From equ (3) , 𝐼𝐵 = or
𝑅𝐶 +𝑅𝐵
𝐼𝐶 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝑉𝐵𝐸
=
𝛽 𝑅𝐶 + 𝑅𝐵
𝐼𝐶 𝐼𝐶 𝑅𝐶 𝑉𝐶𝐶 − 𝑉𝐵𝐸
+ =
𝛽 𝑅𝐶 + 𝑅𝐵 𝑅𝐶 + 𝑅𝐵
𝐼𝐶 𝐶 + 𝑅𝐵 + 𝛽𝑅𝐶 ] = (𝑉𝐶𝐶 − 𝑉𝐵𝐸 )𝛽
[𝑅
𝛽(𝑉𝐶𝐶 − 𝑉𝐵𝐸 )
𝐼𝐶 =
𝑅𝐶 (1 + 𝛽) + 𝑅𝐵
Differentiate the above equation w.r.t. 𝑉𝐵𝐸 we get
𝜕𝐼𝐶 −𝛽
𝑆′ = =
𝜕𝑉𝐵𝐸 𝑅𝐵 + (1 + 𝛽)𝑅𝐶
−𝜷
𝑺′ =
𝑹𝑩 + (𝟏 + 𝜷)𝑹𝑪
STABILITY FACTOR S’’:
𝜕𝐼𝐶
We knowS’’= when 𝐼𝐶𝑂 and 𝑉𝐵𝐸 constant , from equ (4) we get
𝜕𝛽
𝑉𝐶𝐶 −𝑉𝐵𝐸 𝛽(𝑉𝐶𝐶 −𝑉𝐵𝐸 )
𝐼𝐵 = (𝛽+1)𝑅 or𝐼𝐶 =
(𝛽+1)𝑅𝐶 +𝑅𝐵
𝐶 +𝑅𝐵
Differentiate the above equation w.r.t𝛽thus we get,
𝜕𝐼𝐶 (𝑉𝐶𝐶 − 𝑉𝐵𝐸 )(𝑅𝐵 + 𝑅𝐶 ) (𝑉𝐶𝐶 − 𝑉𝐵𝐸 )(𝑅𝐵 + 𝑅𝐶 )
S’’ = = ⟹
𝜕𝛽 [(𝛽 + 1)𝑅𝐶 + 𝑅𝐵 ]2 [(𝛽 + 1)𝑅𝐶 + 𝑅𝐵 ][(𝛽 + 1)𝑅𝐶 + 𝑅𝐵 ]
𝑰 (𝑹 +𝑹𝑩 )
𝑩 𝑪 𝑰𝑪 (𝑹𝑪 +𝑹𝑩 )
𝐒’’ = (𝜷+𝟏)𝑹 or𝐒’’ =
𝑪 +𝑹𝑩 𝜷[(𝜷+𝟏)𝑹𝑪 +𝑹𝑩 ]

VOLTAGE -DIVIDER BIAS OR SELF BIAS OR POTENTIAL - DIVIDER BIAS :

 The biasing is provided by three resistors :𝑅1 ,𝑅2 and 𝑅𝐸
.
 The resistors 𝑅1 and 𝑅2 act as a potential divider giving
a fixed volatge to point B which is base as shown in fig 1.6.
 If collector current𝐼𝐶 increases due to change in
temperature or change in 𝛽 , the emitter current 𝐼𝐸 also
increases and the voltage drop across 𝑅𝐸 increases, reducing
the voltage difference between base and emitter (𝑉𝐵𝐸 ).
 Due to reduction in 𝑉𝐵𝐸 ,base current 𝐼𝐵 and hence
collector current 𝐼𝐶 also reduces.
 Therefore , we can say that negative feedback exits in
the emitter bias circuit.
 This reduction in 𝐼𝐶 compensates for the original change
in 𝐼𝐶 .
Fig 1.6 Voltage -Divider Bias

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Circuit Analysis:
Base Circuit:
Voltage across 𝑅2 is the base voltage 𝑉𝐵𝐸 as shown in fig 1.6 (b),
𝑅2 (𝐼)
𝑉𝐵 = × 𝑉𝐶𝐶 ……..(1)
𝑅1 (𝐼+𝐼𝐵 )+𝑅2 (𝐼)
𝑅2
𝑉𝐵 = × 𝑉𝐶𝐶 𝑠𝑖𝑛𝑐𝑒 𝐼 ≫ 𝐼𝐵 …..(2)
𝑅 +𝑅
1 2
Collector Circuit: Fig 1.6 (b)Base Circuit
Voltage across 𝑅𝐸 , (𝑉𝐸 ) can be obtained as,
𝑉𝐸 = 𝐼𝐸 𝑅𝐸
𝑉𝐸 = 𝑉𝐵 − 𝑉𝐵𝐸
𝑉𝐵 −𝑉𝐵𝐸
∴ 𝐼𝐸 = ……..(3)
𝑅𝐸
Applying KVL to the collector circuit as shown in fig 1.6 (c),
𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐸 − 𝐼𝐸 𝑅𝐸 = 0
∴ 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝐼𝐸 𝑅𝐸 ……..(4)

Fig 1.6 (c) Divider Biased

Simplified circuit of Voltage Divider Bias:
Here 𝑅1 𝑎𝑛𝑑 𝑅2 are replaced by 𝑅𝐵 𝑎𝑛𝑑 𝑉𝑇 , where 𝑅𝐵 is the parallel combination
of 𝑅1 𝑎𝑛𝑑 𝑅2 𝑎𝑛𝑑 𝑉𝑇 is the thevenin’s voltage as shown in fig 1.6 (b).
𝑅𝐵 can be calculated as
𝑅1 𝑅2
𝑅𝐵 = …….(5) Fig 1.6 (d)Thevenin’s equivalent circuit forVoltage -Divider Bias
𝑅1 + 𝑅2
Applying KVL to the base circuit as shown in fig 1.6 (d) ,
𝑉𝑇 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸 …….(5a)
∴ 𝑉𝑇 = 𝑉𝐵𝐸 + (𝑅𝐵 + 𝑅𝐸 )𝐼𝐵 + 𝐼𝐶 𝑅𝐸 (𝑠𝑖𝑛𝑐𝑒 𝐼𝐸 = 𝐼𝐵 + 𝐼𝐶 )
∴ 𝑉𝐵𝐸 = 𝑉𝑇 − (𝑅𝐵 + 𝑅𝐸 )𝐼𝐵 − 𝐼𝐶 𝑅𝐸
We can use simplified /approximate analysis when, 𝛽𝑅𝐸 ≥ 10𝑅2 condition is satisfied.
Stability factor S :
Here the thevenin’s equivalent voltage 𝑉𝑇 is given by ,
𝑅2 𝑉𝐶𝐶
𝑉𝑇 = 𝑎𝑛𝑑
𝑅1 + 𝑅2
𝑅1 𝑅2
From equ(5) we have, 𝑅𝐵 =
𝑅1 +𝑅2
Applying KVL to the base circuit as shown in fig 1.6 (e),
𝑉𝑇 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + (𝐼𝐵 +𝐼𝐶 )𝑅𝐸
𝑉𝑇 = 𝐼𝐵 (𝑅𝐵 + 𝑅𝐸 )+𝐼𝐶 𝑅𝐸 + 𝑉𝐵𝐸
Differentiating the above equation w.r.t 𝐼𝐶 𝑎𝑛𝑑 assuming 𝑉𝐵𝐸 to be constant we get,Fig 1.6 (e)Thevenin’s
equivalent circuit forVoltage- Divider Bias
𝑑𝐼𝐵
0= (𝑅 + 𝑅𝐸 ) + 𝑅𝐸
𝑑𝐼𝐶 𝐵
𝑑𝐼𝐵 −𝑅𝐸
=
𝑑𝐼𝐶 𝑅𝐵 + 𝑅𝐸
(1+𝛽)
We know that,𝑆 = 𝑑𝐼
(1−𝛽 𝐵 )
𝑑𝐼𝐶

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝑑𝐼𝐵
Substituting the value of 𝑑𝐼 , we get
𝐶
(𝟏 + 𝜷)
𝑺= 𝑹𝑬
𝟏 + 𝜷 (𝑹 )
𝑩 +𝑹𝑬
Advantage:
 Stability factor is less as compare to other biasing circuits.
 More stable
 Most commonly used.
Stability Factor: 𝑺′
From equ (5a) , we have 𝑉𝑇 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸
𝑉𝐵𝐸 = 𝑉𝑇 − 𝐼𝐵 𝑅𝐵 − 𝐼𝐸 𝑅𝐸
𝑉𝐵𝐸 = 𝑉𝑇 − 𝐼𝐵 𝑅𝐵 − (𝐼𝐵 +𝐼𝐶 )𝑅𝐸 (since 𝐼𝐸 = 𝐼𝐵 +𝐼𝐶 )
𝑉𝐵𝐸 = 𝑉𝑇 − 𝐼𝐵 𝑅𝐵 − (1 + 𝛽)𝐼𝐵 𝑅𝐸 (since 𝐼𝐸 = (1 + 𝛽)𝐼𝐵 )
𝑉𝐵𝐸 = 𝑉𝑇 − 𝐼𝐵 [𝑅𝐵 + (1 + 𝛽)𝑅𝐸 ]
We know , 𝐼𝐶 = 𝛽𝐼𝐵 + (1 + 𝛽)𝐼𝐶𝑂
𝐼𝐶 − (1 + 𝛽)𝐼𝐶𝑂
𝐼𝐵 = [ ]
𝛽
𝐼𝐶 − (1 + 𝛽)𝐼𝐶𝑂
𝑉𝐵𝐸 = 𝑉𝑇 − [ ] [𝑅𝐵 + (1 + 𝛽)𝑅𝐸 ]
𝛽
Differentiate the above equation w.r.t 𝐼𝐶 assume 𝐼𝐶𝑂 𝑎𝑛𝑑 𝛽 as constant.
𝜕𝑉𝐵𝐸 𝑅𝐵 + (1 + 𝛽)𝑅𝐸
= 0−[ ]
𝜕𝐼𝐶 𝛽
1 𝑅𝐵 + (1 + 𝛽)𝑅𝐸
= − [ ]
𝑆′ 𝛽
−𝜷
𝑺′ = [ ]
𝑹𝑩 + (𝟏 + 𝜷)𝑹𝑬
Stability Factor: 𝑺′′
𝐼𝐶𝑂 𝐼𝐶
𝑉𝐵𝐸 = 𝑉𝑇 + (1 + 𝛽)[(1 + 𝛽)𝑅𝐸 + 𝑅𝐵 ] − [𝑅𝐵 + (1 + 𝛽)𝑅𝐸 ]
𝛽 𝛽
𝐼𝐶 𝐼𝐶𝑂
𝑉𝐵𝐸 = 𝑉𝑇 + 𝑉 ′ − [𝑅𝐵 + (1 + 𝛽)𝑅𝐸 ]Where 𝑉 ′ = (1 + 𝛽)[(1 + 𝛽)𝑅𝐸 + 𝑅𝐵 ]
𝛽 𝛽
𝐼𝐶
𝑉𝑇 + 𝑉 ′ − 𝑉𝐵𝐸 = [𝑅 + (1 + 𝛽)𝑅𝐸 ]
𝛽 𝐵
(𝑉𝑇 + 𝑉 ′ − 𝑉𝐵𝐸 )
𝐼𝐶 = 𝛽
𝑅𝐵 + (1 + 𝛽)𝑅𝐸
Differentiating the above equation w.r.t 𝛽, we get
𝜕𝐼𝐶
[𝑅 + (1 + 𝛽)𝑅𝐸 ] + 𝐼𝐶 𝑅𝐸 = (𝑉𝑇 + 𝑉 ′ − 𝑉𝐵𝐸 )
𝜕𝛽 𝐵
𝜕𝐼𝐶 𝐼𝐶
[𝑅𝐵 + (1 + 𝛽)𝑅𝐸 ] = [𝑅𝐵 + (1 + 𝛽)𝑅𝐸 ] − 𝐼𝐶 𝑅𝐸
𝜕𝛽 𝛽
𝜕𝐼𝐶 𝐼𝐶
[𝑅 + (1 + 𝛽)𝑅𝐸 ] = [𝑅𝐵 + 𝑅𝐸 + 𝛽𝑅𝐸 − 𝛽𝑅𝐸 ]
𝜕𝛽 𝐵 𝛽
𝐼𝐶
𝑆 ′′ [𝑅𝐵 + (1 + 𝛽)𝑅𝐸 ] = [𝑅𝐵 + 𝑅𝐸 ]
𝛽
𝑰𝑪 (𝑹𝑩 + 𝑹𝑬 )
𝑺′′ =
𝜷 𝑹𝑩 + (𝟏 + 𝜷)𝑹𝑬
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
BIASING OF MOSFET:
Biasing Circuits for D-MOSFET:
 Biasing circuits for depletion type MOSFET are quite similar to the circuits used for JFET biasing.
 The primary difference between the two is the fact that depletion type MOSFETs also permits the operating
points with positive value of VGS for n-channel and negative value ofVGS for p-channel MOSFET.
 To have positive value of VGSfor n-channel and negative value of VGSfor p-channel self bias
circuit is unsuitable.
Biasing Circuits for E-MOSFET:
In the DC analysis of MOSFETcircuits , we can use ideal current-voltage equations listed in table 1.2.

S.No nMOS pMOS

1 Non saturation region(𝑉𝐷𝑆 < 𝑉𝐷𝑆(𝑠𝑎𝑡) ) Non saturation region(𝑉𝑆𝐷 < 𝑉𝑆𝐷(𝑠𝑎𝑡) )
2 ] 2 ]
𝐼𝐷 = 𝐾[2(𝑉𝐺𝑆 − 𝑉𝑇 )𝑉𝐷𝑆 − 𝑉𝐷𝑆 𝐼𝐷 = 𝐾[2(𝑉𝑆𝐺 + 𝑉𝑇 )𝑉𝑆𝐷 − 𝑉𝑆𝐷
2 Saturation region(𝑉𝐷𝑆 > 𝑉𝐷𝑆(𝑠𝑎𝑡) ) Saturation region(𝑉𝑆𝐷 < 𝑉𝑆𝐷(𝑠𝑎𝑡) )
𝐼𝐷 = 𝐾(𝑉𝐺𝑆 − 𝑉𝑇 )2 𝐼𝐷 = 𝐾(𝑉𝑆𝐺 + 𝑉𝑇 )2
3 Transistion point 𝑉𝐷𝑆(𝑠𝑎𝑡) = 𝑉𝐺𝑆 − 𝑉𝑇 Transistion point 𝑉𝑆𝐷(𝑠𝑎𝑡) = 𝑉𝑆𝐷 + 𝑉𝑇
4 Enhancement mode 𝑉𝑇 > 0 Enhancement mode 𝑉𝑇 < 0
5 Depletion mode 𝑉𝑇 < 0 Depletion mode 𝑉𝑇 > 0
Table 1.2
Common-Source Biasing Circuit for EMOSFET:
 Common-Source Circuit is one of the basic MOSFET circuit
configurations.
 The fig 1.15 shows the n-channel enhancement-mode MOSFET
circuit with the source terminal is at ground potential and is common
to both the input and output sides of the circuit.
 It is important to note that the coupling capacitor 𝐶𝐶 acts at an
open circuit to d.c.
 But it allows the signal voltage to be coupled to the gate of the
MOSFET.
 The equivalent circuit is shown in fig
1.15.1
Fig 1.15 An nMOS common-source circuit
 Since the gate current into the MOSFET is zero,the voltage at the gate is
given by a voltage-divider , which can be written as,
𝑅2
𝑉𝐺 = 𝑉𝐺𝑆 = (𝑅 ) 𝑉𝐷𝐷 ….(1)
1 +𝑅2

 Assuming that the gate-source is given by equ(1) is greater than 𝑉𝑇 and

MOSFET is biased in the saturation region, the drain current is
𝐼𝐷 = 𝐾(𝑉𝐺𝑆 − 𝑉𝑇 )2 ….(2)
 Applying KVL to drain circuit we have,
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 ….(3) Fig 1.15.1 d.c. equivalent circuit
 If 𝑉𝐷𝑆 > 𝑉𝐷𝑆(𝑠𝑎𝑡) = 𝑉𝐺𝑆 − 𝑉𝑇 , then the MOSFET is biased in the saturation region , as we initially
assumed, and our analysis is correct.
 If 𝑉𝐷𝑆 < 𝑉𝐷𝑆(𝑠𝑎𝑡) , then the MOSFET is biased in the non-saturation region ,and the drain current is
given by,

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝑰𝑫 = 𝑲[𝟐(𝑽𝑮𝑺 − 𝑽𝑻 )𝑽𝑫𝑺 − 𝑽𝟐𝑫𝑺 ]
 Fig 1.15.2 shows a common-source circuitwith p-channel enhancement-
mode MOSFET.
 Here the source is tied to +𝑉𝐷𝐷 , which become signal ground in the ac
equivalent circuit.Thus it is also a common-source circuit.
 The dc analysis for this cirucit is essentially the same as for the n-channel
MOSFET circuit.
 The gate voltage is given by,
𝑅2
𝑉𝐺 = (𝑅 ) 𝑉𝐷𝐷 Fig 1.15.2 A pMOS common-source circuit
1 +𝑅2

 Assuming that 𝑉𝐺𝑆 < 𝑉𝑇 , or 𝑉𝐺𝑆 > |𝑉𝑇 | and that the device is biased in the saturation region, the drain
current is given by,
𝐼𝐷 = 𝐾(𝑉𝑆𝐺 + 𝑉𝑇 )2 ….(2)
 If 𝑉𝑆𝐷 > 𝑉𝑆𝐷(𝑠𝑎𝑡) = 𝑉𝑆𝐺 + 𝑉𝑇 , then the MOSFET is indeed biased in the saturation region , as we have
assumed.
 However, if 𝑉𝑆𝐷 < 𝑉𝑆𝐷(𝑠𝑎𝑡) , then the MOSFET is biased in the non-saturation region ,and the drain
current is given by,
𝑰𝑫 = 𝑲[𝟐(𝑽𝑺𝑮 + 𝑽𝑻 )𝑽𝑺𝑫 − 𝑽𝟐𝑺𝑫 ]
Load Line and Modes of Operation:
Consider the common-source circuit shown in fig 1.16(a).

Fig 1.16 (a) Common source circuit Fig 1.16 (b) Transistor characteristics, 𝑽𝑫𝑺 (𝒔𝒂𝒕) curve,
loadline and Q-point for the nMOS common-source circuit shown in Fig 1.16 (a)
 Writing KVL around the drain-source loop results 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 , which is the load line equation.
 It shows a linear relationship between the 𝐼𝐷 and 𝑉𝐷𝑆 .
 The load line is given by,
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 10 − 𝐼𝐷 (40) (Asssume 𝑉𝐷𝐷 = 10𝑉 𝑎𝑛𝑑 𝑅𝐷 = 40 𝑘Ω )
10 𝑉𝐷𝑆
or 𝐼𝐷 = 40 − (𝑚𝐴)
40
10
 If the 𝐼𝐷 = 0, then 𝑉𝐷𝑆 = 10𝑉; If 𝑉𝐷𝑆 = 0 then 𝐼𝐷 = 40 = 0.25𝑚𝐴
 The Q-point of the MOSFET is given by the d.c. 𝐼𝐷 and 𝑉𝐷𝑆 and it is always on the load line,as shown
in fig 1.16(b)
 If the 𝑉𝐺𝑆 < 𝑉𝑇 , the𝐼𝐷 = 0 and the MOSFET is cutoff.
 If the 𝑉𝐺𝑆 > 𝑉𝑇 , the MOSFET is turns ON and is biased in the saturation region.
 As 𝑉𝐺𝑆 increases, the Q-point moves up the load line.
 The transition point is the boundary between the saturation and non saturation regions.
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
 It is the point where , 𝑉𝐷𝑆 = 𝑉𝐷𝑆(𝑠𝑎𝑡) = 𝑉𝐺𝑆 − 𝑉𝑇
 As 𝑉𝐺𝑆 increases further, the MOSFET operates in non saturation region.
Steps in the DC anlaysis of MOSFET circuits:
1. Assume that, the MOSFET is biased in the saturation region, in which case 𝑉𝐺𝑆 > 𝑉𝑇 , 𝐼𝐷 > 0 and
𝑉𝐷𝑆 ≥ 𝑉𝐷𝑠(𝑠𝑎𝑡) .
2. Analyse the circuit using the saturation current-voltage relations.
3. Evaluate the resulting bias condition of the MOSFET, if the assumed parameter values in step-1 are
valid, then the initial assumption is correct.If 𝑉𝐺𝑆 < 𝑉𝑇 ,then the MOSFET is probably cut-off, and if
𝑉𝐷𝑆 < 𝑉𝐷𝑠(𝑠𝑎𝑡) ,the MOSFET is likely biased in the non-saturation region.
4. If the initial assumption is proved incorrect,then a new assumption must be made and the circuit must
be reanalysed.
Voltage-Divider Bias:
 It is similar to voltage-divider bias provided for JFETand depletion type
MOSFET.
 The only difference is biasing resistors 𝑅1 𝑎𝑛𝑑 𝑅2 are designed to
provide positive gate to source voltage as shown in fig 1.17.
For DC analysis:
As 𝐼𝐺 = 0𝐴
𝑅2
𝑉𝐺 = (𝑅 ) 𝑉𝐷𝐷 …….(1)
1 + 𝑅2
Applying KVL to the input circuit as shown in fig 1.17.1 ,we get, Fig 1.17
𝑉𝐺 − 𝑉𝐺𝑆 − 𝑉𝑆 = 0
∴ 𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝑆 𝑅𝑆
𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷 𝑅𝑆 (since𝐼𝐷 = 𝐼𝑆 ) ….(2)
Applying KVL to the output circuit as shown in fig 1.15,we get
𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝑆 − 𝐼𝑆 𝑅𝑆 = 0 ∴ 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝐼𝑆 𝑅𝑆
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝐼𝐷 𝑅𝑆 (since 𝐼𝐷 = 𝐼𝑆 )
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 )……..(3)

Fig 1.17.1
Feedback bias Circuit:

Fig 1.18 Feedback bias Circuit Fig 1.18(a) Simplified Feedback bias Circuit for DC analysis
 For dc analysis we can replace coupling capacitors by open circuits and we also replace the resistor by
a short circuit equivalent, since IG=0 A as shown in fig 1.18(a).
 As drain and gate terminals are shorted , 𝑉𝐷 = 𝑉𝐺
𝑎𝑛𝑑 𝑉𝐷𝑆 = 𝑉𝐺𝑆 (Since 𝑉𝑆 = 0) …….(1)
Applying KVL to the output circuit we get,

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝑆 = 0
∴ 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 …… (14)
OR 𝑉𝐺𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 (𝑆𝑖𝑛𝑐𝑒 𝑉𝐷𝑆 = 𝑉𝐺𝑆 ) …..(2)
COMPARISON OF BIASING CIRCUITS:
Type Circuit Diagram Equations
𝑉𝐶𝐶 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵
Base Resistor Method 𝑉𝐶𝐶 − 𝑉𝐶𝐸
𝐼𝐶 =
(or)Fixed - Bias Circuit 𝑅𝐶
𝑆 = (1 + 𝛽)
𝛽
𝑆’ = −
𝑅𝐵
𝐼𝐶
𝑆” =
𝛽
𝑉𝐶𝐶 − 𝑉𝐵𝐸 − 𝐼𝐶 𝑅𝐶
𝐼𝐵 =
𝑅𝐶 + 𝑅𝐵
Collector to Base bias 𝛽(𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 −𝑉𝐵𝐸 )
𝐼𝐶 =
𝑅𝐶 + 𝑅𝐵
1+𝛽
𝑆= 𝑅𝐶
1 + 𝛽 (𝑅 +𝑅 )
𝐶 𝐵
−𝛽
𝑆′ =
𝑅𝐵 + (1 + 𝛽)𝑅𝐶
𝐼𝐶 (𝑅𝐶 + 𝑅𝐵 )
𝑆" =
𝛽[(𝛽 + 1)𝑅𝐶 + 𝑅𝐵 ]
Voltage - Divider Bias (or) 𝑅2
𝑉𝐵 = × 𝑉𝐶𝐶
Self Bias (or) Potential - 𝑅1 + 𝑅2
divider bias 𝑠𝑖𝑛𝑐𝑒 𝐼 ≫ 𝐼𝐵
𝑉𝐵 − 𝑉𝐵𝐸
𝐼𝐸 =
𝑅𝐸
(1 + 𝛽)
𝑆= 𝑅
1+𝛽( 𝐸 )
𝑅𝐵 +𝑅𝐸
−𝛽
𝑆′ = [ ]
𝑅𝐵 + (1 + 𝛽)𝑅𝐸
𝐼𝐶 (𝑅𝐵 + 𝑅𝐸 )
𝑆" =
𝛽 𝑅𝐵 + (1 + 𝛽)𝑅𝐸
𝑉𝐷𝑆 = 𝑉𝐺𝑆
𝑉𝐺𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷
Feedback bias Circuit for (𝑆𝑖𝑛𝑐𝑒 𝑉𝐷𝑆 = 𝑉𝐺𝑆 )
E-MOSFET

𝑅2
𝑉𝐺 = ( )𝑉
𝑅1 + 𝑅2 𝐷𝐷
𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷 𝑅𝑆
Voltage Divider Bias for
E-MOSFET

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Introduction:
1. The term small signal amplifier refers to the use of signal that takes up a relatively small percentage of
an amplifier’s operational range.
2. With small input signals the transistors can be replaced with small signal linear model – Small signal
equivalent circuit.
3. An amplifier is used to increase the signal level; i.e. the amplifier is used
to get a larger (sinusoidal) signal output from a small (sinusoidal) signal
input, with frequency same as that of the input.
4. To make the transistor work as an amplifier, it is to be biased to operate
in the active region,i.e. base-emitter junction is to be forward biased, while
base-collector junction to be reverse- biased.
5. Let us consider the common emitter amplifier circuit using self bias or
voltage divider bias as shown in fig 2.1.
Fig 2.1 Common Emitter Amplifier
6. The dc collector-emitter voltage VCE , the dc collector current IC and dc base current IB is the quiescent
operating point for the amplifier.

Fig 2.1.1 𝑰𝑩𝑸 is quiescent DC base current

7.The output current i.e. the collector current is 𝛽 times larger than the input basecurrent in common emitter
configuration.
8.Hence the collector current will also vary
sinusoidally about its quiescent value, ICQ
9.The output voltage will also vary sinusoidally as
shown in the Fig 2.1.1 (a) and (b).
10. Then variations in the collector current and the
voltage between collector and emitter due to change
in the base current are shown graphically with the
help of load line in fig 2.1.2.
11. The frequency of output sinusoidal is the same as
the frequency of input sinusoidal, only the magnitude
of the output signal can change. Fig 2.1.2 Graphical representation of 𝑰𝑩 , 𝑰𝑪 and 𝑽𝑪𝑬 voltage swings
COMMON- EMITTER AMPLIFIER CIRCUIT:
1. Biasing circuit:
 R1, R2and RE - Voltage divider biasing circuit as shown in fig 2.2.
 Sets the proper operating point for the CE amplifier
2. Input Capacitor C1 :
 Couples the signal to the base of the transistor.
 Blocks d.c and allows a.c for amplification.
 Because of this biasing conditions are maintained constant.
3. Emitter Bypass Capacitor CE:
 CE is connected in parallel with emitter resistance RE, to provide
a low reactance path to the amplified ac signal. Fig 2.2 Practical Common Emitter Amplifier
Circuit

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
 If it is not inserted, the amplified ac signal passing through 𝑅𝐸 will cause a voltage drop across it.
 This will reduce the output voltage, reducing the gain of the amplifier.
4. Output Coupling capacitor C2 :
 Couples the output of the amplifier to the load or to the next stage of the amplifier.
 It blocks dc and passes only ac part of the amplified signal.
Need for 𝑪𝟏 , 𝑪𝟐 𝒂𝒏𝒅 𝑪𝑬 :
Consider that the signal source is connected directly to the base of the transistor
as shown in fig 2.2.1.
 Source resistance 𝑅𝑆 is in parallel with𝑅2 and it will reduce the bias voltage.
 Connecting 𝑅𝐿 directly, the dc levels of 𝑉𝐶 and 𝑉𝐶𝐸 will change, So to avoid
this coupling capacitors are connected.
 Coupling capacitors act as open circuits to d.c, maintain stable biasing
conditions. Fig 2.2.1
 The emitter resistance RE which provides bias stabilization and also reduces the voltage swing at the
output.
 The emitter bypass capacitor CE provides a low reactance path to the amplified ac. signal increasing the
output voltage swing.
Phase Reversal:
 An amplifier produces 1800 phase shift.
 A is positive w.r.t B, 𝐼𝐵 increases,𝐼𝐶 increases to get negative half cycle.
 A is negative w.r.t B,𝐼𝐵 decreases,𝐼𝐶 decreases to get positive half cycle.
 By the relation 𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶
CE (Common Emitter) configuration is widely used in amplifier circuits:
1. It provides both voltage gain as well as current gain greater than unity.
2. Power gain (product of voltage gain and current gain) of CE is much greater.
3. The ratio of output resistance to input resistance is small ,may range from 10Ω to 100Ω.So that it is
efficient for coupling between various transistor stages.
AC LOAD LINES:
AC Equivalent Circuits
 For AC analysis, substituting short-circuits for the power supply and all capacitors in the circuit in Fig
2.2.2(a) gives the ac equivalent circuit in Fig 2.2.2(b).
 If 𝑅𝐿 is present, as shown, it appears in parallel with 𝑅𝐶 in the ac equivalent circuit.
 Once the ac equivalent circuit is drawn, the circuit ac performance can be investigated by drawing an
ac load line and by substituting a transistor model for the device.
AC Load Lines
 The emitter resistor is bypassed by the capacitor in Fig 2.2.2 (a), resistor𝑅𝐸 is not part of the circuit ac
load.
 An ac loadline may now be drawn to represent the ac performance of the circuit.
 When there is no input signal, the transistor voltage and current conditions are exactly as indicated by
the Q-point on the dc load line.
 An ac signal causes the transistor voltage and current levels to vary above and below the Q-point.
 Therefore, the Q-point is common to both the ac and dc load lines.
 Starting from the Q-point, another point is found on the ac load line by taking a convenient collector
current change (usually ∆𝐼𝐶 = 𝐼𝐶𝑄 )and calculating the corresponding collector-emitter voltage
change(∆𝑉𝐶𝐸 ).
 Point C is plotted by measuring ∆𝐼𝐶 and ∆𝑉𝐶𝐸 from theQ-point.
 The ac load line is then drawn through points C and Q, as illustrated in fig 2.2.3.
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Draw the dc and ac load lines for the transistor circuit in Fig2.2.3. using the transistor common-emitter
characteristics in Fig2.2.4

Fig 2.2.4 The ac load line for a transistor circuit is drawn through the Q-point.
Fig 2.2.3 Voltage-divider bias circuit with a bypassed emitter resistor.The dc load is (𝑹𝑪 + 𝑹𝑬 ),and the
acload is 𝑹𝑪 when there is no capacitor- coupled load.
Solution:
Drawing the dc load line:
𝑅𝐿(𝑑𝑐) = 𝑅𝐶 + 𝑅𝐸 = 2.2𝑘Ω + 2.7𝑘Ω = 4.9 𝑘Ω
The equation for 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 )
When 𝐼𝐶 = 0, 𝑉𝐶𝐸 = 𝑉𝐶𝐶 = 20𝑉
Plot point A at𝐼𝐶 = 0 and 𝑉𝐶𝐸 = 20 𝑉
𝑉 20𝑉
When 𝑉𝐶𝐸 = 0, 𝐼𝐶 = 𝑅 +𝐶𝐶𝑅 = 4.9×103 = 4.08 𝑚𝐴
𝐶 𝐸
Plot point B at𝐼𝐶 = 4.08 𝑚𝐴 and 𝑉𝐶𝐸 = 0
Draw the dc load line through points A and B as shown in fig 2.2.4
𝑉𝐶𝐶 × 𝑅2 20 × 8.2 × 103
𝑉𝐵 = = = 6.3 𝑉
𝑅1 + 𝑅2 18 × 103 + 8.2 × 103
𝑉𝐸 = 𝑉𝐵 − 𝑉𝐵𝐸 = 6.3𝑉 − 0.7𝑉 = 5.6 𝑉
𝑉𝐸 5.6
𝐼𝐶 ≈ 𝐼𝐸 = = = 2.07𝑚𝐴
𝑅𝐸 2.7 × 103
Mark the Q-point on the dc load line at𝐼𝐶 = 2.07𝑚𝐴
Drawing the ac load line:
When there is no external𝑅𝐿 ,
𝑅𝐿(𝑎𝑐) = 𝑅𝐶 = 2.2𝑘Ω
When 𝐼𝐶 changes by ∆𝐼𝐶 = 2.07𝑚𝐴
∆𝑉𝐶𝐸 = ∆𝐼𝐶 × 𝑅𝐶 = 2.07𝑚𝐴 × 2.2𝑘Ω = 4.55𝑉
Plot point C at ∆𝐼𝐶 = 2.07𝑚𝐴 and ∆𝑉𝐶𝐸 = 4.55𝑉 from the Q-point.
Draw the ac load line through points C and Q as shown in fig 2.2.4.
The Output Voltage Swing (or) Maximum Symmetrical swing:
1. When symmetrical sinusoidal signals are applied to the input of an amplifier, symmetrical sinusoidal
signals are generated at the output, as long as the amplifier operation remains linear.
2. We can use the ac load line to determine the maximum output symmetrical swing.
3. If the output exceeds this limit, a portion of the output signal will be clipped and signal distortion will
occur.
COMMON - COLLECTOR AMPLIFIER CIRCUIT:
1. Also known as Emitter follower circuit , because the emitter terminal follows the signal voltage
applied to the base.
2. The dc biasing is provided by R1,R2 and RE as shown in fig 2.3

19
EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
3. The load resistance is capacitor coupled to the emitter
terminal of the transistor.
4. When a signal is applied via to the base of the transistor, VB
is increased and decreased as the signal goes positive and
negative, respectively
5. By the relation VE = VB –VBE ,VBE = Constant
6. As VB changes, VE also changes, so that the output voltage is
same as that of input voltage. Fig 2.3 Common-Collector Circuit
COMMON- BASE AMPLIFIER CIRCUIT:
1. The signal source is coupled to the emitter of the transistor
via C1 as shown in fig 2.4.
2. The load resistance RL is coupled to the collector of the
transistor via C2.
3. The positive going signal increases the emitter voltage.
4. As VB constant, so VBE reduces, IB reduces and IC also
reduces.
5. By the relation 𝑉0 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 ,the reduction in IC results
in an increase in 𝑉0.
6. So the positive going input produces positive going output and Fig 2.4 Common- Base Circuit
similarly negative going input produces negative going output and there is no phase shift between input and
output in a common base amplifier.
SMALL SIGNAL-LOW FREQUENCY H-PARAMETER MODEL:
This parameter is easier for applying in amplifier circuits for analyzing and designing a circuit.
HereI𝑖 = is the input current to the amplifier ,
𝑉𝑖 = is the input voltage to the amplifier ,
I0 =is the output current of the amplifier,
𝑉0 =is the output voltageof the amplifier
Input voltage 𝑉𝑖 and output current I0 are dependent variables, whereas
input currentI𝑖 and output voltage 𝑉0 are independent variables.
𝑉𝑖 = 𝑓1 (𝐼𝑖 , 𝑉0 ) …. (1) Fig 2.5 Transistor Amplifier
𝐼0 = 𝑓2 (𝐼𝑖 , 𝑉0 ) …. (2)
These can be written in the equation form as follows,
𝑉𝑖 = ℎ11 𝐼𝑖 + ℎ12 𝑉0 …. (3)
𝐼0 = ℎ21 𝐼𝑖 + ℎ22 𝑉0 …. (4)
The above equations can also be written using alphabetic notations,
𝑉𝑖 = ℎ𝑖 𝐼𝑖 + ℎ𝑟 𝑉0 …. (5)
𝐼0 = ℎ𝑓 𝐼𝑖 + ℎ𝑂 𝑉0 …. (6)
Definitions of h-parameter
The parameters in the above equation are defined as follows:
𝑉𝑖
ℎ11 = |𝑉0=0=Input resistance with output short-circuited, in ohms.
𝐼𝑖
𝑉𝑖
ℎ12 = 𝑉 |𝐼𝑖=0 =Fraction of output voltage at input with input open circuited.
0
This parameter isa ratio of similar quantities, hence unitless.
𝐼0
ℎ21 = |𝑉0=0 = Forward current transfer ratio or current gain with output short circuited.
𝐼𝑖
This parameter is a ratio of similar quantities, hence unitless.
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝐼0
ℎ22 = 𝑉 |𝐼𝑖=0 = Output admittance with input open-circuited, in mhos.
0
The above parameters have a mixture of different units and hence referred to as hybrid parameters or h-
parameters.
𝑖 = 11 = Input o = 22 = 𝑂𝑢𝑡𝑝𝑢𝑡
𝑓 = 21 = 𝐹𝑜𝑟𝑤𝑎𝑟𝑑 𝑡𝑟𝑎𝑛𝑠𝑓𝑒𝑟 𝑟 = 12 = 𝑅𝑒𝑣𝑒𝑟𝑠𝑒 𝑡𝑟𝑎𝑛𝑠𝑓𝑒𝑟
a)With output short circuited:
ℎ11 = ℎ𝑖 : Input resistance
ℎ21 = ℎ𝑓 : Short circuit current gain
b)With input open circuited:
ℎ12 = ℎ𝑟 : 𝑅𝑒𝑣𝑒𝑟𝑠𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑡𝑟𝑎𝑛𝑠𝑓𝑒𝑟 𝑟𝑎𝑡𝑖𝑜
ℎ22 = ℎ0 : 𝑂𝑢𝑡𝑝𝑢𝑡 𝑎𝑑𝑚𝑖𝑡𝑡𝑎𝑛𝑐𝑒
Transistor Hybrid Model: Fig 2.6 h-parameter equivalent circuit for transistor
 In order to analyze transistorized amplifier circuit and calculate its input impedance, output impedance,
current gain and voltage gain.
 It is necessary to replace transistor circuit with its equivalent circuit of two equations as shown in fig
2.6.
𝑉𝑖 = ℎ𝑖 𝐼𝑖 + ℎ𝑟 𝑉0 𝐼0 = ℎ𝑓 𝐼𝑖 + ℎ0 𝑉0
Benefits of h-parameters:
1. Real numbers at audio frequencies.
2. Easy to measure.
3. Can be obtained from the transistor static characteristic curves.
4. Convenient to use in circuit analysis and design.
5. Most of the transistor manufacturers specify the h-parameters.
h-parameter equivalent circuit for CE configuration
 Let us consider the common emitter configuration as shown in fig
2.7
The variables 𝐼𝑏 , 𝐼𝑐 . 𝑉𝑏 𝑎𝑛𝑑 𝑉𝑐 represent total instantaneous currents and
voltages. Fig 2.7 Simple common emitter configuration
𝐼𝑏 = 𝐼𝑛𝑝𝑢𝑡 𝐶𝑢𝑟𝑟𝑒𝑛𝑡, 𝐼𝑐 = 𝑂𝑢𝑡𝑝𝑢𝑡 𝐶𝑢𝑟𝑟𝑒𝑛𝑡,
𝑉𝑏𝑒 = Input Voltage and 𝑉𝑐𝑒 = 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒

Fig 2.7.1 h-parameter equivalent circuit for the common emitter configuration
From the h-parameter equivalent circuit of the common emitter configuration we can write,
𝑉𝑏𝑒 = ℎ𝑖𝑒 𝐼𝑏 + ℎ𝑟𝑒 𝑉𝑐𝑒 ……….(7)
𝐼𝑐 = ℎ𝑓𝑒 𝐼𝑏 + ℎ𝑜𝑒 𝑉𝑐𝑒 ……….(8)
∆𝑉𝐵𝐸
Whereℎ𝑖𝑒 = |𝑉𝐶𝐸 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 ……….(9)
∆𝐼𝐵
∆𝑉𝐵𝐸
ℎ𝑟𝑒 = |𝐼𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 ……….(10)
∆𝑉𝐶𝐸
∆𝐼𝐶
ℎ𝑓𝑒 = ∆𝐼 |𝑉𝐶𝐸 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 ……….(11)
𝐵
∆𝐼
ℎ𝑜𝑒 = ∆𝑉 𝐶 |𝐼𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 ……….(12)
𝐶𝐸

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
The quantities ∆𝑉𝐵𝐸 (𝑉𝑏𝑒 ), ∆𝑉𝐶𝐸 (𝑉𝑐𝑒 ), ∆𝐼𝐵 (𝐼𝑏 )𝑎𝑛𝑑∆𝐼𝐶 (𝐼𝑐 ) represent the small change in base in base and
collector voltages and currents.
h-parameters for all three configurations
ℎ𝑖𝑒 = ℎ11𝑒 = 𝐼𝑛𝑝𝑢𝑡 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑖𝑛 𝑐𝑜𝑚𝑚𝑜𝑛 − 𝑒𝑚𝑖𝑡𝑡𝑒𝑟 𝑐𝑜𝑛𝑓𝑖𝑔𝑢𝑟𝑎𝑡𝑖𝑜𝑛
ℎ𝑓𝑏 = ℎ21𝑏 = 𝑆ℎ𝑜𝑟𝑡 − 𝑐𝑖𝑟𝑐𝑢𝑖𝑡 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑔𝑎𝑖𝑛 𝑖𝑛 𝑐𝑜𝑚𝑚𝑜𝑛 − 𝑏𝑎𝑠𝑒 𝑐𝑜𝑛𝑓𝑖𝑔𝑢𝑟𝑎𝑡𝑖𝑜𝑛
The basic circuit of hybrid model is same for all the three configurations, only parameters are different as
shown in table 2.1.
Parameter CB CE CC
Input resistance ℎ𝑖𝑏 ℎ𝑖𝑒 ℎ𝑖𝑐
Reverse voltage gain ℎ𝑟𝑏 ℎ𝑟𝑒 ℎ𝑟𝑐
Forward transfer current gain ℎ𝑓𝑏 ℎ𝑓𝑒 ℎ𝑓𝑐
Output admittance ℎ𝑜𝑏 ℎ𝑜𝑒 ℎ𝑜𝑐
Table 2.1
The circuits and equations are valid for either an n-p-n or p-n-p transistor and are independent of the type of
load or method of biasing as shown in fig 2.7.2.

Fig 2.7.2 Transistor configurations and their hybrid models

Determination of h-parameters from characteristics:
Let us consider CE configuration. Its functional relationship can be
defined as,
𝑉𝑏𝑒 = 𝑓1 (𝐼𝑏 , 𝑉𝑐𝑒 ) ….. (1)
𝐼𝑐 = 𝑓2 (𝐼𝑏 , 𝑉𝑐𝑒 ) ….. (2)
The input characteristic curves give the relationship between input voltage
𝑉𝐵𝐸 and input current 𝐼𝐵 for different values of output voltage 𝑉𝐶𝐸 as
shown in fig 2.7.3.
Determination of 𝒉𝒊𝒆 𝒂𝒏𝒅 𝒉𝒓𝒆 from input characteristic curves:
Fig 2.7.3 Typical Input Characteristic Curves for CE Configuration
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Parameter 𝒉𝒊𝒆 :
∆𝑉𝐵𝐸 𝑉𝐵𝐸2 −𝑉𝐵𝐸1
ℎ𝑖𝑒 = |𝑉𝐶𝐸 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 = ……(3)
∆𝐼𝐵 𝐼𝐵2 −𝐼𝐵1
The slope of the line EF, drawn tangent to the input characteristic curve at the point Q gives ℎ𝑖𝑒 .
Parameter 𝒉𝒓𝒆 :
∆𝑉𝐵𝐸 𝑉𝐵𝐸2 − 𝑉𝐵𝐸1
ℎ𝑟𝑒 = |𝐼𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 =
∆𝑉𝐶𝐸 𝑉𝐶𝐸2 − 𝑉𝐶𝐸1
A horizontal line on the input characteristic curve represents constant
base current as shown in fig 2.7.3.
The output characteristic curves give the relationship between output
current𝐼𝐶 and output voltage𝑉𝐶𝐸 for different values of input current𝐼𝐵 as
shown in fig 2.7.4 Fig 2.7.4 Typical output Characteristic Curves for CE Configuration
Determination of 𝒉𝒇𝒆 𝒂𝒏𝒅 𝒉𝒐𝒆 from output characteristic curves:
Parameter 𝒉𝒇𝒆 :
∆𝐼𝐶 𝐼𝐶2 − 𝐼𝐶1
ℎ𝑓𝑒 = |𝑉𝐶𝐸 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 =
∆𝐼𝐵 𝐼𝐵2 − 𝐼𝐵1
Parameter 𝒉𝒐𝒆 :
∆𝐼𝐶 𝐼𝐶2 − 𝐼𝐶1
ℎ𝑜𝑒 = |𝐼𝐵 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 =
∆𝑉𝐶𝐸 𝑉𝐶𝐸2 − 𝑉𝐶𝐸1
The slope of the line AB, drawn tangent to the input characteristic curve at the point Q gives ℎ𝑜𝑒 .
So the h-parameters are always calculated at quiescent operating point of the amplifier.
Mid-band Analysis of BJT single stage Amplifiers:
To form a transistor amplifier only it is necessary to connect an external load and signal source, along with
proper biasing.

Fig 2.8 Basic transistor amplifier

Replace the above transistor circuit with its small signal hybrid model as shown below

Fig 2.8.1 Transistor amplifier in its h-parameter model

Let us analyze hybrid model to find the current gain, the input resistance, the voltage gain, and the output
resistance.
Current Gain (𝑨𝒊 ):
For transistor amplifier 𝐴𝑖 is defined as the ratio of output to input currents. It is given by,
𝐼𝐿 𝐼
𝐴𝑖 = = − 2 ..........(1)
𝐼1 𝐼1
Hence 𝐼𝐿 and 𝐼2 are equal in magnitude but opposite in sign,i.e.𝐼𝐿 = −𝐼2
From the circuit of fig 2.8.1we have,
𝐼2 = ℎ𝑓 𝐼1 + ℎ0 𝑉2 .......... (2)
Substituting 𝑉2 = −𝐼2 𝑅𝐿 in the equation we get,

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝐼2 = ℎ𝑓 𝐼1 + ℎ0 (−𝐼2 𝑅𝐿 )
∴ 𝐼2 + ℎ0 𝐼2 𝑅𝐿 = ℎ𝑓 𝐼1
∴ (1 + ℎ0 𝑅𝐿 )𝐼2 = ℎ𝑓 𝐼1
𝐼2 ℎ𝑓
∴ =
𝐼𝑖 1 + ℎ0 𝑅𝐿
𝑰 −𝒉
∴ 𝑨𝒊 = − 𝑰𝟐 = 𝟏+𝒉 𝒇𝑹 .......... (3)
𝟏 𝟎 𝑳
Current Gain (𝑨𝒊𝒔 ):
It is the current gain taking into account the source
resistance,𝑅𝑆 if the model is driven by the current
source instead of voltage source. It is given by
𝐼2 𝐼2 𝐼1
𝐴𝑖𝑠 = − = . .......... (4)
𝐼𝑠 𝐼1 𝐼𝑠
𝐼
𝐴𝑖𝑠 = 𝐴𝑖 . 𝐼1 Fig 2.8.2
𝑠
Looking at fig 2.8.2 and using current divider equation we get,
𝐼𝑠 𝑅𝑠
𝐼1 =
𝑍𝑖 + 𝑅𝑠
𝐼1 𝑅𝑠
∴ =
𝐼𝑠 𝑍𝑖 + 𝑅𝑠
𝑨𝒊 𝑹𝒔
and hence 𝑨𝒊𝒔 = 𝒁 +𝑹 .......... (5)
𝒊 𝒔
Input Impendence (𝒁𝒊 ):
As shown in fig 2.8 ,𝑅𝑖 is the input resistance looking into the amplifier input terminals(1,1’). It is given by,
𝑉1
𝑅𝑖 = .......... (6)
𝐼1
From the input circuit we have, 𝑉1 = ℎ𝑖 𝐼1 + ℎ𝑟 𝑉2 .......... (7)
𝑉1 ℎ𝑖 𝐼1 +ℎ𝑟 𝑉2
Hence𝑍𝑖 = =
𝐼1 𝐼1
𝑉2
∴ 𝑍𝑖 = ℎ𝑖 + ℎ𝑟 𝐼 .......... (8)
1
Substituting 𝑉2 = −𝐼2 𝑅𝐿 = 𝐴𝑖 𝐼1 𝑅𝐿 .......... (9)
In the above equation we get,
ℎ𝑟 𝐴𝑖 𝐼1 𝑅𝐿
𝑍𝑖 = ℎ𝑖 + = ℎ𝑖 + ℎ𝑟 𝐴𝑖 𝑅𝐿 .......... (10)
𝐼1
ℎ
Substituting 𝐴𝑖 = − 1+ℎ𝑓 𝑅
0 𝐿
ℎ𝑟 ℎ𝑓 𝑅𝐿
We get,𝑍𝑖 = ℎ𝑖 − 1+ℎ .......... (11)
0 𝑅𝐿
Dividing numerator and denominator by 𝑅𝐿 we get
ℎ𝑟 ℎ𝑓
𝑍𝑖 = ℎ𝑖 −
1⁄𝑅𝐿 + ℎ0
𝒉𝒓 𝒉𝒇 1
𝒁𝒊 = 𝒉𝒊 − 𝒀 Where 𝑌𝐿 = 𝑅 . . . . . . . . . . (12)
𝑳 +𝒉𝟎 𝐿
From this equation we can note that input impedance is a function of the load and impedance
Voltage Gain(𝑨𝑽 ):
It is the ratio of output voltage 𝑉2 to the input voltage 𝑉1.It is given by
𝑉
𝐴𝑉 = 𝑉2 .......... (13)
1
From equ(9) we have,
𝐴𝑖 𝐼1 𝑅𝐿 𝐴𝑖 𝑅𝐿
𝐴𝑉 = = .......... (14)
𝑉1 𝑍𝑖
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝐼1 1
Since,𝑉 = 𝑍
1 𝑖
Voltage Gain (𝑨𝑽𝑺 ):
It is voltage gain including the source. It is given by,
𝑉 𝑉 𝑉
𝐴𝑉𝑆 = 𝑉2 = 𝑉2 × 𝑉1 .......... (15)
𝑆 1 𝑆
𝑉
∴ 𝐴𝑉𝑆 = 𝐴𝑉 × 𝑉1 .......... (16) Fig 2.8.3
𝑆
Looking at fig 2.8.3and applying potential divider theorem we can write,
𝑍𝑖
𝑉1 = 𝑉
R S + 𝑍𝑖 𝑆
𝑉1 𝑍𝑖
∴ =
𝑉𝑆 R S + 𝑍𝑖
𝑉1
Substituting value of 𝑉 in equ (16)
𝑆
𝑍𝑖
We get,𝐴𝑉𝑆 = 𝐴𝑉 × R .......... (17)
S +𝑍𝑖
𝑨𝑹 𝐴𝑖 𝑅𝐿
𝑨𝑽𝑺 = 𝐑 𝒊+𝐑𝑳 since𝐴𝑉 = .......... (18)
𝐒 𝐢 𝑍𝑖
Output Admittance 𝒀𝑶 :
It is the ratio of output current 𝐼2 to the output voltage 𝑉2 . It is given by,
𝐼2
𝑌𝑂 = with𝑉𝑆 = 0 .......... (19)
𝑉2
From equ(2) we have,𝐼2 = ℎ𝑓 𝐼1 + ℎ0 𝑉2
Dividing above equation by 𝑉2 we get,
𝐼2 ℎ𝑓 𝐼1
= + ℎ0
𝑉2 𝑉2
𝐼
∴ 𝑌𝑂 = ℎ𝑓 𝑉1 + ℎ0 .......... (20)
2
From fig 2.8.1with 𝑉𝑆 = 0 we can write,
R S 𝐼1 + ℎ𝑖 𝐼1 + ℎ𝑟 𝑉2 = 0 .......... (21)
∴ (R S + ℎ𝑖 )𝐼1 = −ℎ𝑟 𝑉2
𝐼 −ℎ𝑟
∴ 𝑉1 = R .......... (22)
2 S +ℎ𝑖
𝐼1
Substituting value of from equ (22) in equ (20) we obtain,
𝑉2
ℎ ℎ𝑟
∴ 𝑌𝑂 = ℎ0 − ℎ 𝑓+R .......... (23)
𝑖 S
From this equation we can note that admittance is a function of the source resistance.
Power Gain (𝑨𝑷 ):
It is the ratio of average power delivered to the load R L , to the input power. Output power is given as
𝑃2 = 𝑉2 𝐼𝐿 = −𝑉2 𝐼2.......... (24)
Since the input power is 𝑃1 = 𝑉1 𝐼1 the operating power gain 𝐴𝑃 of the transistor is defined as,
𝑃 𝑉𝐼 RL 𝐴𝑖 RL
𝐴𝑃 = 𝑃2 = − 𝑉2 𝐼2 = 𝐴𝑉 𝐴𝑖 = 𝐴𝑖 2 𝑠𝑖𝑛𝑐𝑒 𝐴𝑉 = .......... (25)
1 1 1 𝑍𝑖 𝑍𝑖
Method For Analysis of a Transistor Circuit:
1. Draw the actual circuit diagram
2. Replace coupling capacitor and emitter bypass capacitor by short circuit.
3. Replace dc source by a short circuit. In other words, Short 𝑉𝐶𝐶 and ground lines
4. Mark the points B(Base),C(Collector),E(Emitter) on the circuit diagram and locate these points as the start
of the equivalent circuit.
5. Replace the transistor by its h-parameter model.
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Consider a common emitter amplifier with
voltage divider bias circuit as shown in fig 2.9.
Step 1 : Draw actual circuit diagram
Step 2: Short coupling and bypass capacitors
Step3 : Short 𝑉𝐶𝐶 and ground lines
Step 4 : Mark point B,C,E

Fig 2.9

Fig 2.9.1 Fig 2.9.2(e) Circuit with transistor replaced by h-parameter equivalent
Step5 : Replace transistor by its h-parameter model and calculate effective 𝑅𝑂 (𝑅 ′ 𝑂 ).
For example , in above circuit 𝑅 ′ 𝑖 = 𝑅1 ||𝑅2 ||𝑅𝑖
and𝑅 ′ 𝑜 = 𝑅𝑜 ||𝑅𝐶
For the CC transistor amplifier circuit, find the expressions for input impedance and voltage gain.
Assume suitable model for transistor.
Solution:

𝐼 𝐼
Current gain (𝑨𝒊 ) = 𝐼𝐿 = − 𝐼𝑒 …..(1)
𝑏 𝑏
From the circuit of fig (b) we have,
𝐼𝑒 = ℎ𝑓𝑐 𝐼𝑏 + ℎ𝑜𝑐 𝑉𝑒
= ℎ𝑓𝑐 𝐼𝑏 + ℎ𝑜𝑐 (−𝐼𝑒 𝑅𝐿 ) 𝑠𝑖𝑛𝑐𝑒 𝑉𝑒 = −𝐼𝑒 𝑅𝐿 …….(2)
∴ (1 + ℎ𝑜𝑐 𝑅𝐿 )𝐼𝑒 = ℎ𝑓𝑐 𝐼𝑏
𝐼𝑒 ℎ𝑓𝑐
∴ =
𝐼𝑏 1 + ℎ𝑜𝑐 𝑅𝐿
𝑰 −𝒉
∴ 𝑨𝒊 = − 𝑰𝒆 = 𝟏+𝒉 𝒇𝒄𝑹 …..(3)
𝒃 𝒐𝒄 𝑳
𝑉𝑏
Input Resistance (𝑅𝑖 ) = …..(4)
𝐼𝑏
From the input circuit of fig(b) we have,
𝑉𝑏 = ℎ𝑖𝑐 𝐼𝑏 + ℎ𝑟𝑐 𝑉𝑒 &𝑉𝑒 = −𝐼𝑒 𝑅𝐿 = 𝐴𝑖 𝐼𝑏 𝑅𝐿 …….(5)
ℎ𝑖𝑐 𝐼𝑏 +ℎ𝑟𝑐 𝐴𝑖 𝐼𝑏 𝑅𝐿
∴ 𝑅𝑖 = = ℎ𝑖𝑐 + ℎ𝑟𝑐 𝐴𝑖 𝑅𝐿 …..(6)
𝐼𝑏
−ℎ
Substituting 𝐴𝑖 = 1+ℎ 𝑓𝑐𝑅
𝑜𝑐 𝐿

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
ℎ𝑟𝑐 ℎ𝑓𝑐 𝑅𝐿
We get ,𝑅𝑖 = ℎ𝑖𝑐 − …..(7)
1+ℎ𝑜𝑐 𝑅𝐿
𝑽𝒆 𝑨𝒊 𝑹𝑳 𝑰𝒃 𝑨𝒊 𝑹𝑳 𝐼 1
Voltage gain (𝑨𝒗 ) = 𝑽 = = since 𝑉𝑏 = 𝑅 …….(9)
𝒃 𝑽𝒃 𝑹𝒊 𝑏 𝑖
𝐼2
Output Admittance (𝒀𝟎 ) = 𝑉 𝑤𝑖𝑡ℎ 𝑉𝑠 = 0 ……(9)
2
From equ (2) , we have, 𝐼𝑒 = ℎ𝑓𝑐 𝐼𝑏 + ℎ𝑜𝑐 𝑉𝑒
Dividing above equation by 𝑉𝑒 we get,
𝐼𝑒 ℎ𝑓𝑐 𝐼𝑏
𝑌0 = = + ℎ𝑜𝑐
𝑉𝑒 𝑉𝑒
From fig (b) , with 𝑉𝑠 = 0 we can write,
𝑅𝑠 𝐼𝑏 + ℎ𝑖𝑐 𝐼𝑏 + ℎ𝑟𝑐 𝑉𝑒 = 0….(10)

∴ (𝑅𝑠 + ℎ𝑖𝑐 )𝐼𝑏 = −ℎ𝑟𝑐 𝑉𝑒

𝐼𝑏 −ℎ𝑟𝑐
∴ =𝑅 ….(11)
𝑉𝑒 𝑠 +ℎ𝑖𝑐
𝐼
Substituting value of 𝑉𝑏 from equ(11) in equ (10) , we obtain,
𝑒
𝒉𝒇𝒄 𝒉𝒓𝒄 𝟏
𝒀𝟎 = 𝒉𝒐𝒄 − 𝒉 &𝑹𝟎 = 𝒀 ….(12)
𝒊𝒄 +𝑹𝒔 𝟎
For the CE transistor amplifier circuit, find the expressions for input impedance and voltage gain.
Assume suitable model for transistor.
Solution:

𝐼 𝐼
Current gain (𝑨𝒊 ) = 𝐼𝐿 = − 𝐼𝑐 …..(1)
𝑏 𝑏
From the circuit of fig(b) we have,
𝐼𝑐 = ℎ𝑓𝑒 𝐼𝑏 + ℎ𝑜𝑒 𝑉𝑐
𝐼𝑐 = ℎ𝑓𝑒 𝐼𝑏 + ℎ𝑜𝑒 (−𝐼𝑐 𝑅𝐿 ) 𝑠𝑖𝑛𝑐𝑒 𝑉𝑐 = −𝐼𝑐 𝑅𝐿 …….(2)
∴ (1 + ℎ𝑜𝑒 𝑅𝐿 )𝐼𝑐 = ℎ𝑓𝑒 𝐼𝑏
𝐼𝑐 ℎ𝑓𝑒
∴ =
𝐼𝑏 1 + ℎ𝑜𝑒 𝑅𝐿
𝐼 −ℎ
∴ 𝐴𝑖 = − 𝐼𝑐 = 1+ℎ 𝑓𝑒𝑅 …..(3)
𝑏 𝑜𝑒 𝐿
𝑉𝑏
Input Resistance (𝑅𝑖 ) = …..(4)
𝐼𝑏
From the input circuit of fig(b) we have,
𝑉𝑏 = ℎ𝑖𝑒 𝐼𝑏 + ℎ𝑟𝑒 𝑉𝑐 &𝑉𝑐 = −𝐼𝑐 𝑅𝐿 = 𝐴𝑖 𝐼𝑏 𝑅𝐿 …….(5)
ℎ𝑖𝑒 𝐼𝑏 +ℎ𝑟𝑒 𝐴𝑖 𝐼𝑏 𝑅𝐿
∴ 𝑅𝑖 = = ℎ𝑖𝑒 + ℎ𝑟𝑒 𝐴𝑖 𝑅𝐿 …..(6)
𝐼𝑏
−ℎ
Substituting 𝐴𝑖 = 1+ℎ 𝑓𝑒𝑅
𝑜𝑒 𝐿
ℎ𝑟𝑒 ℎ𝑓𝑒 𝑅𝐿
We get ,𝑅𝑖 = ℎ𝑖𝑒 − …..(7)
1+ℎ𝑜𝑒 𝑅𝐿
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝑉𝑐 𝐴𝑖 𝑅 𝐿 𝐼𝑏 𝐴𝑖 𝑅𝐿 𝐼𝑏 1
Voltage gain (𝑨𝒗 ) = 𝑉 = = since 𝑉 = 𝑅 …….(9)
𝑏 𝑉𝑏 𝑅𝑖 𝑏 𝑖
𝐼𝑐
Output Admittance (𝒀𝟎 ) = 𝑉 𝑤𝑖𝑡ℎ 𝑉𝑠 = 0 ……(9)
𝑐
From equ (2) , we have, 𝐼𝑐 = ℎ𝑓𝑒 𝐼𝑏 + ℎ𝑜𝑒 𝑉𝑐
Dividing above equation by 𝑉𝑐 we get,
𝐼𝑐 ℎ𝑓𝑒 𝐼𝑏
𝑌0 = = + ℎ𝑜𝑒
𝑉𝑐 𝑉𝑐
From fig (b) , with 𝑉𝑠 = 0 we can write,
𝑅𝑠 𝐼𝑏 + ℎ𝑖𝑒 𝐼𝑏 + ℎ𝑟𝑒 𝑉𝑐 = 0….(10)

∴ (𝑅𝑠 + ℎ𝑖𝑒 )𝐼𝑏 = −ℎ𝑟𝑒 𝑉𝑐

𝐼𝑏 −ℎ𝑟𝑒
∴ =𝑅 ….(11)
𝑉𝑐 𝑠 +ℎ𝑖𝑒
𝐼
Substituting value of 𝑉𝑏 from equ(11) in equ (10) , we obtain,
𝑐
ℎ𝑓𝑒 ℎ𝑟𝑒 1
𝑌0 = ℎ𝑜𝑒 − ℎ and𝑅0 = 𝑌 ….(12)
𝑖𝑒 +𝑅𝑠 0
For the CB transistor amplifier circuit, find the expressions for input impedance and voltage gain.
Assume suitable model for transistor.
Solution:
The fig shows the CB amplifier and its h-parameter equivalent circuit.

𝐼𝐿 𝐼
Current gain (𝑨𝒊 ) = = − 𝐼𝑐
𝐼𝑒 𝑒
From the circuit of fig(b) we have,
𝐼𝑐 = ℎ𝑓𝑏 𝐼𝑒 + ℎ𝑜𝑏 𝑉𝑐
= ℎ𝑓𝑏 𝐼𝑏 + ℎ𝑜𝑒 (−𝐼𝑐 𝑅𝐿 ) 𝑠𝑖𝑛𝑐𝑒 𝑉𝑐 = −𝐼𝑐 𝑅𝐿
∴ (1 + ℎ𝑜𝑏 𝑅𝐿 )𝐼𝑐 = ℎ𝑓𝑏 𝐼𝑒
𝐼𝑐 ℎ𝑓𝑏
∴ =
𝐼𝑒 1 + ℎ𝑜𝑏 𝑅𝐿
−ℎ𝑓𝑏
∴ 𝐴𝑖 =
1 + ℎ𝑜𝑏 𝑅𝐿
𝑉𝑒
Input Resistance (𝑅𝑖 ) = 𝐼𝑒
From the input circuit of fig(b) we have,
𝑉𝑒 = ℎ𝑖𝑏 𝐼𝑒 + ℎ𝑟𝑏 𝑉𝑐 𝑎𝑛𝑑 𝑉𝑐 = −𝐼𝑐 𝑅𝐿 = 𝐴𝑖 𝐼𝑒 𝑅𝐿
ℎ𝑖𝑏 𝐼𝑒 + ℎ𝑟𝑏 𝐴𝑖 𝐼𝑒 𝑅𝐿
∴ 𝑅𝑖 = = ℎ𝑖𝑏 + ℎ𝑟𝑏 𝐴𝑖 𝑅𝐿
𝐼𝑒
𝑉 𝐴𝑖 𝐼𝑒 𝑅𝐿 𝐴𝑖 𝑅𝐿 𝐼𝑒 1
Voltage gain (𝑨𝒗 ) = 𝑉𝑐 = = since =𝑅
𝑒 𝑉𝑒 𝑅𝑖 𝑉𝑒 𝑖
𝐼𝑐
Output Admittance (𝒀𝟎 ) = 𝑉 𝑤𝑖𝑡ℎ 𝑉𝑠 = 0
𝑐
We have, 𝐼𝑐 = ℎ𝑓𝑏 𝐼𝑒 + ℎ𝑜𝑏 𝑉𝑐

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Dividing above equation by 𝑉𝑐 we get,
𝐼𝑐 ℎ𝑓𝑏 𝐼𝑒
𝑌0 = = + ℎ𝑜𝑏
𝑉𝑐 𝑉𝑐
From fig (b) , with 𝑉𝑠 = 0 we can write,
𝑅𝑠 𝐼𝑒 + ℎ𝑖𝑏 𝐼𝑒 + ℎ𝑟𝑏 𝑉𝑐 = 0

∴ (𝑅𝑠 + ℎ𝑖𝑏 )𝐼𝑒 = −ℎ𝑟𝑏 𝑉𝑐

𝐼𝑒 −ℎ𝑟𝑏
∴ =
𝑉𝑐 𝑅𝑠 + ℎ𝑖𝑏
ℎ ℎ 1
𝑌𝑜 = ℎ𝑜𝑏 − 𝑅𝑓𝑏+ℎ𝑟𝑏 and 𝑅𝑜 = 𝑌
𝑠 𝑖𝑏 𝑜
Comparison of Transistor Configurations:
S.No Characteristic Common -Base Common-Emitter Common-Collector
1 Input resistance Very low (20Ω) Low (1𝑘Ω) High (500𝑘Ω)
2 Output resistance Very high (1𝑀Ω) High (40𝑘Ω) Low (50Ω)
3 Input current 𝐼𝐸 𝐼𝐵 𝐼𝐵
4 Output current 𝐼𝐶 𝐼𝐶 𝐼𝐸
5 Input voltage applied Emitter and Base Base and Emitter Base and Collector
between
6 Output voltage taken Collector and Base Collector and Emitter Emitter and Collector
between
7 Current amplification 𝐼𝐶 𝐼𝐶 𝐼𝐸
factor 𝛼 = 𝛽= 𝛾=
𝐼𝐸 𝐼𝐵 𝐼𝐵
8 Current gain Less than unity High (20 to few High (20 to few
hundreds) hundreds)
9 Voltage gain Medium Medium Low
10 Applications As a input stage of For audio signal For impedance
multistage amplifier amplification matching
MOSFET AS AN AMPLIFIER:
For the MOSFET to operate as a linear amplifier the transistor must be biased in the saturation region, and the
instantaneous drain current and drain-to-source voltage must also be confined to the saturation region
Graphical Analysis, Load Lines, and Small-Signal Parameters:
1. Fig 3.9(a) shows an NMOS common-source circuit with a time-varying (input signal sinusoidal)
voltage source in series with the dc source.
2. Fig 3.9(b) shows the transistor characteristics, dcload line and Q-point, where the dc load line and Q-
point are functions of 𝑣𝐺𝑆 , 𝑉𝐷𝐷 , 𝑅𝐷 and the MOSFET parameters.

Fig 3.9 (a) NMOS Common-source circuit with time-varying signal source in series with gate dc source
(b) Common-source transistor characteristics, dc loadline, and sinusoidal variation in gate-to-source
voltage, draincurrent, and drain-to-source voltage
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Small Signal Parameters:
 The instantaneous gate-to-source voltage is,
𝑣𝐺𝑆 = 𝑉𝐺𝑆𝑄 + 𝑣𝑖 ….(1)
Where 𝑉𝐺𝑆𝑄 is the dc component and 𝑣𝑔𝑠 is the ac component.
 As 𝑣𝑖 increases, the instantaneous value of 𝑣𝐺𝑆 increases, and the bias point moves up the load line.
 For a negative 𝑣𝑖 , the instantaneous value of 𝑣𝐺𝑆 decreases below the quiescent value, and the bias point
moves down the load line.
 The time-varying signal source 𝑣𝑖 in fig 3.9(a) generates a time-varying component of the gate-to-source
voltage.
 In this case, substitute 𝑣𝑔𝑠 = 𝑣𝑖 in equ(1)
𝑣𝐺𝑆 = 𝑉𝐺𝑆𝑄 + 𝑣𝑔𝑠 …..(2)
The instantaneous drain current is,
𝑖𝐷 = 𝐾𝑛 (𝑣𝐺𝑆 − 𝑉𝑇 )2 ……(3)
Substituting equ(2) into equ(3) produces
2 2
𝑖𝐷 = 𝐾𝑛 (𝑉𝐺𝑆𝑄 + 𝑣𝑔𝑠 − 𝑉𝑇 ) = 𝐾𝑛 [(𝑉𝐺𝑆𝑄 − 𝑉𝑇 ) + 𝑣𝑔𝑠 ] …..(4a)
2
or 𝑖𝐷 = 𝐾𝑛 (𝑉𝐺𝑆𝑄 − 𝑉𝑇 ) + 2𝐾𝑛 (𝑉𝐺𝑆𝑄 − 𝑉𝑇 )𝑣𝑔𝑠 + 𝐾𝑛 𝑣 2𝑔𝑠 …..(4b)

DC component Time varying 𝐼𝐷 component Produces harmonics

 For the sinusoidal input signal , the squared term produces undesirable harmonics or non linear distortion,
in the output voltage.
 To minimize these harmonics , we require
𝑉𝑔𝑠 ≪ 2(𝑉𝐺𝑆𝑄 − 𝑉𝑇 ) …..(5) is the small-signal condition that must be satisfied for linear amplifiers.
So we neglect 𝑣 2𝑔𝑠 term in equ(4b)
∴ 𝑖𝐷 = 𝐼𝐷𝑄 + 𝑖𝑑 …(6)
2
Where 𝐼𝐷𝑄 = 𝐾𝑛 (𝑉𝐺𝑆𝑄 − 𝑉𝑇 ) ……..DC component and
𝑖𝑑 = 2𝐾𝑛 (𝑉𝐺𝑆𝑄 − 𝑉𝑇 )𝑣𝑔𝑠 … … … AC component
The small-signal 𝑖𝑑 is related to the small-signal gate-to-source voltage by the transconductance 𝑔𝑚 . So 𝑔𝑚
is also called gain.
𝑖
It is given by, 𝑔𝑚 = 𝑣 𝑑 = 2𝐾𝑛 (𝑉𝐺𝑆𝑄 − 𝑉𝑇 ) ….(6)
𝑔𝑠
The transconductance can also be obtained from the derivative
𝜕𝑖
𝑔𝑚 = 𝜕𝑣 𝐷 = 2𝐾𝑛 (𝑉𝐺𝑆𝑄 − 𝑉𝑇 ) ….(7)
𝐺𝑆 |𝑣 =𝑉
𝐺𝑆 𝐺𝑆𝑄=𝑐𝑜𝑛𝑠𝑡.

𝑔𝑚 = 2√𝐾𝑛 𝐼𝐷𝑄 ……(8)

 𝑔𝑚 is the slope of the curve.
If 𝑣𝑔𝑠 is small, the 𝑔𝑚 is a constant. Fig 3.9.1 Drain current versus gate-to-source voltage characteristics,
with superimposed sinusoidal signals
 With the Q-point in the saturation region, the transistor operates as a current source that is linearly
controlled by 𝑣𝑔𝑠 .
If the Q-point moves into the non saturation region, the transistor no longer operates as a linearly controlled
current source.
 In equ (7),𝑔𝑚 is directly proportional to the conduction parameter 𝐾𝑛 which is a function of the width to
length ratio.
 Therefore, increase in the width of the transistor increases the 𝑔𝑚 , or gain, of the transistor.
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 EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
AC EQUIVALENT CIRCUIT:
From fig 3.9 (a) ,the output voltage is
𝑣𝐷𝑆 = 𝑣𝑂 = 𝑉𝐷𝐷 − 𝑖𝐷 𝑅𝐷 …..(9)
Substituting the value of 𝑖𝐷 from equ (6), we obtain
𝑣𝑂 = 𝑉𝐷𝐷 − (𝐼𝐷𝑄 + 𝑖𝑑 )𝑅𝐷 = (𝑉𝐷𝐷 − 𝐼𝐷𝑄 𝑅𝐷 ) − 𝑖𝑑 𝑅𝐷 …..(10)
The output voltage is also a combination of dc and ac values.
The time-varying 𝑣𝐷𝑆 is equal to 𝑣𝑜 and is given by
𝑣𝑂 = 𝑣𝐷𝑆 = −𝑖𝑑 𝑅𝐷
Also, from equ (6) and equ (7), we have
𝑖𝑑 = 𝑔𝑚 𝑣𝑔𝑠
The following equations are given in terms of the instantaneous ac values, as well as the phasors.
Instantaneous ac values Phasor form
𝑣𝑔𝑠 = 𝑣𝑖 𝑉𝑔𝑠 = 𝑉𝑖
𝑖𝑑 = 𝑔𝑚 𝑣𝑔𝑠 𝐼𝐷 = 𝑔𝑚 𝑉𝑔𝑠
𝑣𝑑𝑠 = −𝑖𝑑 𝑅𝐷 𝑉𝑑𝑠 = −𝐼𝑑 𝑅𝐷

 The ac equivalent circuit in fig 3.9.2 is developed by setting the dc

sources in fig 3.9 equal to zero.
 The node connecting 𝑅𝐷 and 𝑉𝐷𝐷 is at signal ground.
Fig 3.9.2 AC equivalent circuit of common-source amplifier with NMOS transistor
SMALL SIGNAL EQUIVALENT CIRCUIT:
(1) Common Source with NMOS:
 The input to the gate thus appears as an open circuit, or an infinite resistance.
 The finite output resistance of a MOSFET is biased in the saturation region

Fig 3.9.3 (a) Common-source NMOS transistor with small-signal parameters and (b) simplified small-
signal equivalent circuit for NMOS transistor
We know that, 𝑖𝐷 = 𝐾𝑛 [(𝑣𝐺𝑆 − 𝑉𝑇𝑁 )2 (1 + 𝜆𝑣𝐺𝑆 )]
Where 𝜆 is the channel-length modulation parameter and is a positive quantity.
The small-signal output resistance is
𝜕𝑖𝐷 −1
𝑟𝑜 = ( ) |𝑣𝐺𝑆 =𝑉𝐺𝑆𝑄=𝑐𝑜𝑛𝑠𝑡.
𝜕𝑣𝐷𝑆
2 −1 −1
or 𝑟𝑜 = [𝜆𝐾𝑛 (𝑉𝐺𝑆𝑄 − 𝑉𝑇 ) ] ≅ [𝜆𝐼𝐷𝑄 ] is also a function of the Q-point parameters.
 This equivalent circuit can now be inserted into the amplifier ac equivalent circuit in fig 3.9.2 to produce
the circuit in fig 3.9.4 (b).

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 EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS

Fig 3.9.4 (a)Expanded small signal equivalent circuit, including output resistance, for NMOS transistor
(b) Small-signal equivalent circuit of common-source circuit with NMOS transistor model
(2) Common Source with PMOS:
 This is similar to NMOS, except that all current directions and voltage polarities are reversed.

Fig 3.9.5(a) Common-source circuit with PMOS transistor and (b) corresponding ac equivalent circuit

Fig 3.9.6(a) Small-signal equivalent circuit of PMOS transistor (b) Small-signal equivalent circuit of
common-source amplifier with PMOS transistor model
The output voltage is, 𝑉𝑜 = 𝑔𝑚 𝑉𝑠𝑔 (𝑟𝑜 ||𝑅𝐷 )
The control voltage 𝑉𝑠𝑔 given in terms of the input signal voltage, is
𝑉𝑠𝑔 = −𝑉𝑖
and the small-signal voltage gain is
𝑣𝑜
𝐴𝑉 = = −𝑔𝑚 (𝑟𝑜 ||𝑅𝐷 )
𝑣𝑖
The negative sign indicates that a 1800 phase reversal exists between the output and input signals, for both
the PMOS and the NMOS circuit.

Steps in the AC Analysis of MOSFET Amplifier:

1. Perform the dc analysis of the circuit and check whether the MOSFET is biased in the saturation region in
order to produce a linear amplification.
2. Replace the MOSFET by its small-signal equivalent circuit.
3. Analyze the resulted circuit, making the dc source components equal to zero.
MODELING THE BODY EFFECT:
 For an NMOS device, the body is connected to the most negative potential in the circuit and will be at
signal ground.
 The 𝑣𝑆𝐵 must be greater than or equal to zero.
The simplified current-voltage relation is,
𝑖𝐷 = 𝐾𝑛 (𝑣𝐺𝑆 − 𝑉𝑇 )2 ……(1)
and the threshold voltage is given by
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝑉𝑇 = 𝑉𝑇𝑂 + 𝛾[√2𝜙𝑓 + 𝑣𝑆𝐵 − √2𝜙𝑓 ] ……..(2)

Fig 3.10 The four-terminal NMOS device with (a) dc voltages and (b) ac voltages
The back-gate transconductance can be defined as
𝜕𝑖𝐷 −𝜕𝑖𝐷 𝜕𝑖𝐷 𝜕𝑉𝑇
𝑔𝑚𝑏 = |𝑄−𝑝𝑜𝑖𝑛𝑡 = |𝑄−𝑝𝑜𝑖𝑛𝑡 = − ( ).( ) |𝑄−𝑝𝑜𝑖𝑛𝑡 …..(3)
𝜕𝑣𝐵𝑆 𝑣𝑆𝐵 𝜕𝑉𝑇 𝜕𝑣𝑆𝐵
From equ(1), we find
𝜕𝑖𝐷
= −2𝐾𝑛 (𝑣𝐺𝑆 − 𝑉𝑇 ) = −𝑔𝑚 ……(4)
𝜕𝑉𝑇
From equ (2), we find
𝜕𝑉𝑇 𝛾
= ≡𝜂
𝜕𝑣𝑆𝐵 2√2𝜙𝑓 + 𝑣𝑆𝐵
So the back-gate transconductance is then,
𝑔𝑚𝑏 = −(𝑔𝑚 ). (𝜂) = 𝑔𝑚 𝜂
 If 𝑣𝑏𝑠 > 0, then 𝑣𝑆𝐵 decreases, 𝑉𝑇
decreases, and 𝑖𝐷 increases.
 In general we will neglect 𝑔𝑚𝑏 .
Fig 3.10.1 Small-signal equivalent circuit of NMOS device including body effect
MOSFET CONFIGURATIONS:
1. Common-Source Configuration
2. Common-Drain Configuration (or) Source-Follower Amplifier
3. Common-Gate Configuration
COMMON-SOURCE CONFIGURATION:
1. For the circuit shown in fig 3.11, assume that the MOSFET is biased in the saturation region by resistors
𝑅1 and 𝑅2 and that the signal frequency is sufficiently large for the coupling capacitor to act essentially as a
short circuit.
2. Voltage source 𝑣𝑖 is in series with an equivalent source resistance 𝑅𝑠𝑖 .
3. In order to minimize loading effects, 𝑅𝑠𝑖 should be much less than the amplifier input resistance, 𝑅𝑖 =
𝑅1 ∥ 𝑅2 .
4. The source is at ground potential, there is no body effect.

Fig 3.11.1 Small-signal equivalent circuit

Fig 3.11 Common-source circuit with voltage divider biasing and coupling capacitor
Voltage Gain:
The output voltage is
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
𝑉𝑜 = −𝑔𝑚 𝑉𝑔𝑠 (𝑟𝑜 ||𝑅𝐷 ) …..(1)
From fig 3.11.1,the input gate -to-source voltage is
𝑅𝑖
𝑉𝑔𝑠 = ( ) . 𝑉𝑖 ……(2)
𝑅𝑖 +𝑅𝑆𝑖
𝑉𝑔𝑠
∴ 𝑉𝑖 = 𝑅𝑖 …..(3)
( )
𝑅𝑖 +𝑅𝑆𝑖

𝑣𝑜 −𝑔𝑚 𝑉𝑔𝑠 (𝑟𝑜 ||𝑅𝐷 )

𝐴𝑉 = = 𝑉𝑔𝑠
𝑣𝑖
𝑅𝑖
( )
𝑅𝑖 +𝑅𝑆𝑖
𝑹
𝑨𝑽 = −𝒈𝒎 (𝒓𝒐 ||𝑹𝑫 ). (𝑹 +𝑹𝒊 ) …..(4)
𝒊 𝑺𝒊
The ac drain current to the ac drain-to-source voltage, as
𝑉𝑑𝑠 = −𝐼𝑑 (𝑅𝐷 )
 Since 𝑅𝑆𝑖 is not zero, the amplifier input signal 𝑉𝑔𝑠 is less
than the signal voltage. This is known as loading effect.
 It reduces the voltage gain of the amplifier.
 In order to provide the maximum symmetrical output
voltage swing, keep the transistor biased in the saturation region
and the Q-point must be near the middle of the saturation region
as shown in fig 3.11.2.
 At the same time, the input signal must be small enough
for the amplifier to remain linear.
Fig 3.11.2 DC load line and transition point separating saturation and non-saturation region
Input Resistance:
𝑹𝒊 = 𝑹𝟏 ∥ 𝑹𝟐 ……(5)
Output Resistance: Set 𝑉𝑔𝑠 = 0
𝑹𝒐 = 𝑹𝑫 ∥ 𝒓𝒐 …..(6)
COMMON SOURCE AMPLIFIER WITH SOURCE RESISTOR:
1. A source resistor 𝑅𝑆 tends to stabilize the Q-point against variations in transistor parameters and also
reduces the signal gain as shown in fig 3.12.
2. Consider a situation in which the body effect should be taken into account.
3. The substrate (not shown) would normally be connected to the -5V supply, so that the body and substrate
terminals are not at the same potential. However, this body effect will be neglected.

Fig 3.12.1 Small-signal equivalent circuit

Fig 3.12 Common-source circuit with source resistor and positive and negative supply voltages

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Voltage gain:
The output voltage is, 𝑉𝑜 = −𝑔𝑚 𝑉𝑔𝑠 𝑅𝐷 ….(1)
Apply KVL to the gate source loop, as shown in fig 3.12.1,
𝑉𝑖 = 𝑉𝑔𝑠 + (𝑔𝑚 𝑉𝑔𝑠 )𝑅𝑆
𝑉𝑖 = 𝑉𝑔𝑠 (1 + 𝑔𝑚 𝑅𝑆 ) …..(2)
Substituting equ(1) and equ(2) in 𝐴𝑉

𝑉𝑜 −𝑔𝑚 𝑉𝑔𝑠 𝑅𝐷
𝐴𝑉 = =
𝑉𝑖 𝑉𝑔𝑠 (1 + 𝑔𝑚 𝑅𝑆 )
−𝒈𝒎 𝑹𝑫
𝑨𝑽 = …..(3)
𝟏+𝒈𝒎 𝑹𝑺
−𝑹𝑫
If 𝑔𝑚 is large, then 𝑨𝑽 ≅ 𝑹𝑺
COMMON SOURCE CIRCUIT WITH SOURCE BYPASS CAPACITOR:
1. A source bypass capacitor added to the CS circuit with a source resistor will minimize the loss in the
small-signal voltage gain, while maintaining the Q-point stability.
2. The Q-point stability can be further increased by replacing the source resistor with a constant-current
source as shown in fig 3.13.

Fig 3.13.1 Small-signal equivalent circuit

Fig 3.13 NMOS common-source circuit with source bypass capacitor
Voltage gain:
The output voltage is, 𝑉𝑜 = −𝑔𝑚 𝑉𝑔𝑠 𝑅𝐷
Since 𝑉𝑔𝑠 = 𝑉𝑖 the small-signal voltage gain is
𝑉𝑜
𝑨𝑽 = = −𝒈𝒎 𝑹𝑫
𝑉𝑖
COMMON-DRAIN CONFIGURATION (OR) SOURCE-FOLLOWER AMPLIFIER:
 For the circuit shown in fig 3.14, the output signal is taken off the source with respect to ground and the
drain is connected directly to 𝑉𝐷𝐷 .
 Since 𝑉𝐷𝐷 becomes signal ground in the ac equivalent circuit, we have the name common drain or source
follower.

Fig 3.14.1 Small-signal equivalent circuit

Fig 3.14 NMOS source-follower or common-drain amplifier

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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
 In the equivalent circuit, the coupling
capacitor acts as a short circuit, is shown in fig
3.14.1.
 The drain is at signal ground, and the small-
signal resistance 𝑟𝑜 of the transistor is in parallel
with the dependent current source.
Voltage Gain:
The output voltage is Fig 3.14.2 Equivalent circuit with all signal grounds at a common point
𝑉𝑜 = (𝑔𝑚 𝑉𝑔𝑠 )(𝑅𝑆 ||𝑟𝑜 ) …..(1)
Writing a KVL equation from input to output results in the following:
𝑉𝑖𝑛 = 𝑉𝑔𝑠 + 𝑉𝑜 …..(2)
Substituting the value of 𝑉𝑜 in equ(2) , we get
𝑉𝑖𝑛 = 𝑉𝑔𝑠 + 𝑔𝑚 𝑉𝑔𝑠 (𝑅𝑆 ||𝑟𝑜 ) ……(3)
1
𝑉𝑖𝑛 𝑔𝑚
∴ 𝑉𝑔𝑠 = ( )=[ 1 ] . 𝑉𝑖𝑛 ……(4)
1+𝑔𝑚 (𝑅𝑆 ||𝑟𝑜 ) +(𝑅𝑆 ||𝑟𝑜 )
𝑔𝑚
Using voltage divider rule we have,
𝑅
𝑉𝑖𝑛 = (𝑅 +𝑅𝑖 ) 𝑉𝑖 …..(5)
𝑖 𝑆𝑖

Substituting the value of 𝑉𝑖𝑛 in equ(4),

𝑉𝑜 𝑔𝑚 (𝑅𝑆 ||𝑟𝑜 ) 𝑅𝑖
𝐴𝑉 = = .( )
𝑉𝑖 1 + 𝑔𝑚 (𝑅𝑆 ||𝑟𝑜 ) 𝑅𝑖 + 𝑅𝑆𝑖
𝑹𝑺 ||𝒓𝒐 𝑹𝒊
Or 𝑨𝑽 = 𝟏 .( ) …..(6)
+𝑹𝑺 ||𝒓𝒐 𝑹𝒊 +𝑹𝑺𝒊
𝒈𝒎
Input resistance 𝑹𝒊 :
𝑅𝑖 = 𝑅1 ||𝑅2 ……(7)
Output Resistance 𝑹𝒐 :
 The input resistance to the gate of the MOSFET is essentially infinite, the input bias resistances to
provide a loading effect.
 To calculate the output resistance, we set all independent small-signal sources equal to zero, apply a test
voltage to the output terminals, and find the test current.
Set 𝑉𝑖 = 0 and apply a test voltage 𝑉𝑥 .
𝑉𝑥
𝑅𝑜 = 𝐼𝑥
…(8)
Applying KCL to the output node we have ,
𝑉 𝑉
𝐼𝑥 + 𝑔𝑚 𝑉𝑔𝑠 = 𝑅𝑥 + 𝑟𝑥 …..(9)
𝑆 𝑜

Since input current is zero, we have

𝑉𝑔𝑠 = −𝑉𝑥 …..(10)
Substituting the value of 𝑉𝑠 from equ(10) in equ(9), Fig 3.14.2 Equivalent circuit to determine 𝑹𝒐
𝑉𝑥 𝑉
𝐼𝑥 − 𝑔𝑚 𝑉𝑥 = 𝑅𝑆
+ 𝑟𝑥
𝑜
1 1
𝐼𝑥 = 𝑉𝑥 (𝑔𝑚 + + )
𝑅𝑆 𝑟𝑜
𝐼𝑥 1 1 1
= = 𝑔𝑚 + +
𝑉𝑥 𝑅𝑜 𝑅𝑆 𝑟𝑜
𝟏
𝑹𝒐 =
𝒈𝒎
||𝑹𝑺 ||𝒓𝒐 …..(11)
For PMOS the current direction and voltage polarities are varied.
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
COMMON-GATE CONFIGURATION:
 The input signal is applied to the source terminal and the gate is at signal ground.
 The circuit is biased with a constant-current source 𝐼𝑄 .
 The gate resistor 𝑅𝐺 prevents the static charge on the gate terminal, and the capacitor𝐶𝐺 ensures that the
gate is at signal ground.
 The coupling capacitor 𝐶𝐶1 couples the signal to the source, and the coupling capacitor 𝐶𝐶2 couples the
output voltage to load resistance 𝑅𝐿 .
 The small-signal transistor resistance 𝑟𝑜 is assumed to be infinite.

Fig 3.15.1 Small-signal equivalent circuit

Fig 3.15 Common-gate circuit
Voltage Gain:
The output voltage is,
𝑉𝑜 = −(𝑔𝑚 𝑉𝑔𝑠 )(𝑅𝐷 ||𝑅𝐿 ) ……(1)
Applying KVL to the input side , we have
𝑉𝑖 = 𝐼𝑖 𝑅𝑆𝑖 − 𝑉𝑔𝑠 ….(2)
𝑉𝑖 = −𝑔𝑚 𝑉𝑔𝑠 𝑅𝑆𝑖 − 𝑉𝑔𝑠 since 𝐼𝑖 = −𝑔𝑚 𝑉𝑔𝑠
−𝑉𝑖
∴ 𝑉𝑔𝑠 = 1+𝑔 …..(3)
𝑚 𝑅𝑆𝑖
Substituting the value of 𝑉𝑔𝑠 from equ(2) in equ(1),
−𝑉𝑖
𝑉𝑜 = −(𝑔𝑚 ) (𝑅 ||𝑅 )
1 + 𝑔𝑚 𝑅𝑆𝑖 𝐷 𝐿
𝑉𝑜 𝒈𝒎 (𝑹𝑫 ||𝑹𝑳 )
𝑨𝑽 = = …(4)
𝑉𝑖 𝟏+𝒈𝒎 𝑹𝑺𝒊
Current Gain:
 The signal input to CG circuit is a current.
The output current 𝐼𝑜 can be written as
𝑅𝐷
𝐼𝑜 = (𝑅 ) (−𝑔𝑚 𝑉𝑔𝑠 ) ….(5)
𝐷 +𝑅𝐿
Applying KCL at node A we have,
𝑉𝑔𝑠
𝐼𝑖 + 𝑔𝑚 𝑉𝑔𝑠 + 𝑅 = 0 …..(6)
𝑆𝑖
𝑅
∴ 𝑉𝑔𝑠 = −𝐼𝑖 (1+𝑔 𝑆𝑖𝑅 ) …….(7) Fig 3.15.2 Small-signal equivalent circuit to determine 𝑨𝒊
𝑚 𝑆𝑖
Substituting the value of 𝑉𝑔𝑠 from equ(2) in equ(1),
𝑅𝑆𝑖 𝑅𝐷
𝐼𝑜 = (−𝑔𝑚 )(−𝐼𝑖 ) ( )( )
1 + 𝑔𝑚 𝑅𝑆𝑖 𝑅𝐷 + 𝑅𝐿
𝑰𝒐 𝑹𝑫 𝒈𝒎 𝑹𝑺𝒊
𝑨𝒊 = =( ).( ) ….(8)
𝑰𝒊 𝑹𝑫 +𝑹𝑳 𝟏+𝒈𝒎 𝑹𝑺𝒊
If 𝑅𝐷 ≫ 𝑅𝐿 and 𝑔𝑚 𝑅𝑠𝑖 ≫ 1 , the current gain tends to unity.
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EC3353-ELECTRONIC DEVICES AND CIRCUITS UNIT-II AMPLIFIERS
Input Resistance:
−𝑉𝑔𝑠
𝑅𝑖 = ….(9)
𝐼𝑖
𝐼𝑖 = −𝑔𝑚 𝑉𝑔𝑠 ….(10)
Substituting the value of 𝐼𝑖 from equ(10) in equ(9),
𝟏
𝑹𝒊 = 𝒈 ….(11)
𝒎
Output Resistance:
 When the input signal voltage equal to zero i.e , 𝑉𝑖 = 0.
 This means that 𝑉𝑔𝑠 = 0 and hence 𝑔𝑚 𝑉𝑔𝑠 = 0
 The output resistance, looking back from the load resistance, is therefore
𝑹𝒐 = 𝑹𝑫 ….(12)
THE THREE BASIC AMPLIFIER CONFIGURATIONS:
Configuration Voltage gain Current gain Input resistance Output resistance
Common source 𝐴𝑉 > 1 - 𝑅𝑇𝐻 Moderate to high
Source follower 𝐴𝑉 ≅ 1 - 𝑅𝑇𝐻 Low
(Common drain)
Common gate 𝐴𝑉 > 1 𝐴𝑖 ≅ 1 Low Moderate to high

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