Ejemplo de Digilent para Un LCD Con El PmodCLP V
Ejemplo de Digilent para Un LCD Con El PmodCLP V
Se utiliza el módulo periférico Pmod CLP y el ejemplo de la referencia para la tarjeta Nexys 3.
Ahora se presenta el código en verilog para la tarjeta Nexys 3, como se encuentra en las referencias.
Observar que las líneas siguientes representan la declaración de un arreglo descrito como parámetros
(parameter), que sería el equivalente de realizar una memoria ROM.
// ==============================================================================
// Define Module
// ==============================================================================
module PmodCLP(
btnr,
CLK,
JA,
JB
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input btnr; // use BTNR as reset input
input CLK; // 100 MHz clock input
//lcd input signals
//signal on connector JA
output [7:0] JA; //output bus, used for data transfer (DB)
// signal on connector JB
//JB[4]register selection pin (RS)
//JB[5]selects between read/write modes (RW)
//JB[6]enable signal for starting the data read/write (E)
output [6:4] JB;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
wire [7:0] JA;
wire [6:4] JB;
// ===========================================================================
// Implementation
// ===========================================================================
// This process counts to 100, and then resets. It is used to divide the clock signal.
// This makes oneUSClock peak aprox. once every 1microsecond
always @(posedge CLK)
begin
if(clkCount == 7'b1100100)
begin
clkCount <= 7'b0000000;
oneUSClk <= ~oneUSClk;
end
else
begin
clkCount <= clkCount + 1'b1;
end
end
// Determines when count has gotten to the right number, depending on the state.
assign delayOK = (
((stCur == stPowerOn_Delay) && (count == 21'b111101000010010000000)) || // 2000000=20 ms
((stCur == stFunctionSet_Delay) && (count == 21'b000000000111110100000)) || // 4000 =40 us
((stCur == stDisplayCtrlSet_Delay) && (count == 21'b000000000111110100000)) || // 4000 =40 us
((stCur == stDisplayClear_Delay) && (count == 21'b000100111000100000000)) || // 160000 =1.6 ms
((stCur == stCharDelay) && (count == 21'b000111111011110100000)) // 260000=2.6 ms - Max Delay for
character writes and shifts
) ? 1'b1 : 1'b0;
// This process generates the sequence of outputs needed to initialize and write to the LCD screen
always @(stCur or delayOK or writeDone or lcd_cmd_ptr)
begin
case (stCur)
// Delays the state machine for 20ms which is needed for proper startup.
stPowerOn_Delay :
begin
if(delayOK == 1'b1)
begin
stNext <= stFunctionSet;
end
else
begin
stNext <= stPowerOn_Delay;
end
end
// Gives the proper delay of 37us between the function set and
// the display control set.
stFunctionSet_Delay :
begin
if(delayOK == 1'b1)
begin
stNext <= stDisplayCtrlSet;
end
else
begin
stNext <= stFunctionSet_Delay;
end
end
// Gives the proper delay of 37us between the display control set
// and the Display Clear command.
stDisplayCtrlSet_Delay :
begin
if(delayOK == 1'b1)
begin
stNext <= stDisplayClear;
end
else
begin
stNext <= stDisplayCtrlSet_Delay;
end
end
// stActWr
stActWr :
begin
stNext <= stCharDelay;
end
endcase
end
// Assign outputs
assign JA = LCD_CMDS[lcd_cmd_ptr][7:0];
assign JB[4] = LCD_CMDS[lcd_cmd_ptr][9];
assign JB[5] = LCD_CMDS[lcd_cmd_ptr][8];
assign JB[6] = (stCur == stFunctionSet || stCur == stDisplayCtrlSet || stCur == stDisplayClear || stCur == stActWr)
? 1'b1 : 1'b0;
endmodule
########################################################################
## This file is a general .ucf for Nexys3 rev B board
##Clock signal
Net "clk" LOC=V10 | IOSTANDARD=LVCMOS33;
## Buttons
Net "btnr" LOC = D9 | IOSTANDARD = LVCMOS33; # BTNR
## 12 pin connectors
##JA
Net "JA<0>" LOC = T12 | IOSTANDARD = LVCMOS33; # JA1
Net "JA<1>" LOC = V12 | IOSTANDARD = LVCMOS33; # JA2
Net "JA<2>" LOC = N10 | IOSTANDARD = LVCMOS33; # JA3
Net "JA<3>" LOC = P11 | IOSTANDARD = LVCMOS33; # JA4
Net "JA<4>" LOC = M10 | IOSTANDARD = LVCMOS33; # JA7
Net "JA<5>" LOC = N9 | IOSTANDARD = LVCMOS33; # JA8
Net "JA<6>" LOC = U11 | IOSTANDARD = LVCMOS33; # JA9
Net "JA<7>" LOC = V11 | IOSTANDARD = LVCMOS33; # JA10
##JB
#Net "JB<0>" LOC = K2 | IOSTANDARD = LVCMOS33; # JB1
#Net "JB<1>" LOC = K1 | IOSTANDARD = LVCMOS33; # JB2
#Net "JB<2>" LOC = L4 | IOSTANDARD = LVCMOS33; # JB3
#Net "JB<3>" LOC = L3 | IOSTANDARD = LVCMOS33; # JB4
Net "JB<4>" LOC = J3 | IOSTANDARD = LVCMOS33; # JB7
Net "JB<5>" LOC = J1 | IOSTANDARD = LVCMOS33; # JB8
Net "JB<6>" LOC = K3 | IOSTANDARD = LVCMOS33; # JB9
#Net "JB<7>" LOC = K5 | IOSTANDARD = LVCMOS33; # JB10
##JC
#Net "JC<0>" LOC = H3 | IOSTANDARD = LVCMOS33; # JC1
#Net "JC<1>" LOC = L7 | IOSTANDARD = LVCMOS33; # JC2
#Net "JC<2>" LOC = K6 | IOSTANDARD = LVCMOS33; # JC3
#Net "JC<3>" LOC = G3 | IOSTANDARD = LVCMOS33; # JC4
#Net "JC<4>" LOC = G1 | IOSTANDARD = LVCMOS33; # JC7
#Net "JC<5>" LOC = J7 | IOSTANDARD = LVCMOS33; # JC8
#Net "JC<6>" LOC = J6 | IOSTANDARD = LVCMOS33; # JC9
#Net "JC<7>" LOC = F2 | IOSTANDARD = LVCMOS33; # JC10
Referencias:
Pmod CLP
https://digilent.com/reference/_media/pmod:pmod:pmodclp_rm.pdf?msclkid=d33ffd08d01811ec94612c94b29
3e4b3
https://digilent.com/reference/pmod/pmodclp/start?msclkid=d3402d65d01811ec9a5ab95753699fec