Digital Electronics

Manoj Pandya
+91 - 9460378169
 UNIT - I
Positional Number System: Binary, decimal, octal and Hexadecimal number system.
conversion from one base to another base. Representation of positive and negative integers,
Real numbers, Characters.
Digital codes: weighted binary code, Non weighted code, Gray code. Binary to Gray
conversion, Gray to binary conversion. BCD code. Binary Arithmetic in 1's and 2's
complement.

UNIT-II
Boolean Algebra: Binary valued quantities, Logical Operations, Basic postulates of Boolean
Algebra, Principle of Duality , Basic theorems of Boolean algebra , De- Morgan's Theorem.
Finding complements of Boolean expressions. Minterm and Maxterm of Boolean Function.
Simplifications of SOP Boolean expressions using karnaugh map - 3 variables Boolean
function, 4 variables Boolean Function.

UNIT - III
Basic Logic Gate: Universal Logic gate , Exclusive -OR, Equivalence OR gates.
Combinational Circuits: Half Adder , Full Adder, Parallel Binary Adder, Subtractor,
Comparator , Decoder , Encoder , Multiplexer, Demultiplexer.

UNIT - IV
Combinational versus Synchronous circuits.
Flip Flop: : Edge Triggered versus Pulse Triggered Flip Flop, S-R , D , J-K , T edge triggered
Flip flop. J-K Master slave Flip flop

UNIT - V
Shift Register: Shift Register Function , Serial and Parallel Shift registers , Bi-directional
Shift registers.
Counters: Asynchronous and Synchronous counters, Up/Down Counters, Decade Counters

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Unit - I

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Introduction:-
Digital electronics deals with the electronic manipulation of numbers, or with
the manipulation of varying quantities by means of numbers. Because it is convenient to do so, today's
digital systems deal only with the numbers 'zero' and 'one', because they can be represented easily by
'off and 'on' within a circuit.

Positional Number System:

A positional (numeral) system is a system for representation of numbers by
an ordered set of numerals symbols (called digits) in which the value of a numeral symbol depends on
its position. There are four types of number systems.

1. Binary Number System:- All digital circuits and systems use this binary number system. The
base or radix of this number system is 2. So, the numbers 0 and 1 are used in this number system. The
part of the number, which lies to the left of the binary point is known as integer part. Similarly, the part
of the number, which lies to the right of the binary point is known as fractional part. In this number
system, the successive positions to the left of the binary point having weights of 20, 21, 22, 23 and so on.
Similarly, the successive positions to the right of the binary point having weights of 2-1, 2-2, 2-3 and so on.
That means, each position has specific weight, which is power of base 2.

2. Octal Number System: The base or radix of octal number system is 8. So, the numbers
ranging from 0 to 7 are used in this number system. The part of the number that lies to the left of
the octal point is known as integer part. Similarly, the part of the number that lies to the right of
the octal point is known as fractional part. In this number system, the successive positions to the
left of the octal point having weights of 80, 81, 82, 83 and so on. Similarly, the successive
positions to the right of the octal point having weights of 8-1, 8-2, 8-3 and so on. That means, each
position has specific weight, which is power of base 8.

3. Decimal Number System: The base or radix of Decimal number system is 10. So, the
numbers ranging from 0 to 9 are used in this number system. The part of the number that lies to
the left of the decimal point is known as integer part. Similarly, the part of the number that lies
to the right of the decimal point is known as fractional part. In this number system, the
successive positions to the left of the decimal point having weights of 100, 101, 102, 103 and so
on. Similarly, the successive positions to the right of the decimal point having weights of 10-1,
10-2, 10-3 and so on. That means, each position has specific weight, which is power of base 10.

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4. Hexa-Decimal Number System:- The base or radix of Hexa-decimal number system is 16.
So, the numbers ranging from 0 to 9 and the letters from A to F are used in this number system.
The decimal equivalent of Hexa-decimal digits from A to F are 10 to 15. The part of the number,
which lies to the left of the hexadecimal point is known as integer part. Similarly, the part of the
number, which lies to the right of the Hexa-decimal point is known as fractional part. In this
number system, the successive positions to the left of the Hexa-decimal point having weights of
160, 161, 162, 163 and so on. Similarly, the successive positions to the right of the Hexa-decimal
point having weights of 16-1, 16-2, 16-3 and so on. That means, each position has specific weight,
which is power of base 16.

Base Conversion:-

B -O B-D B-H Table

O-B O-D O-H Multiply

D-B D-O D-H Divide

H-B H-O H -D Via Binary

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Representation of Positive and negative Integer:-

In mathematics, positive numbers (including zero) are represented

as unsigned numbers. That is we do not put the +ve sign in front of them to show that they are
positive numbers. However, when dealing with negative numbers we do use a -ve sign in front of
the number to show that the number is negative in value and different from a positive unsigned
value, and the same is true with signed binary numbers.

However, in digital circuits there is no provision made to put a

plus or even a minus sign to a number, since digital systems operate with binary numbers that are
represented in terms of “0’s” and “1’s”. When used together in microelectronics, these “1’s” and
“0’s”, called a bit (being a contraction of BInary digiT), fall into several range sizes of numbers
which are referred to by common names, such as a byte or a word.

Mathematical numbers are generally made up of a sign and a value

(magnitude) in which the sign indicates whether the number is positive, ( + ) or negative, ( – )
with the value indicating the size of the number, for example 23, +156 or -274. Presenting
numbers is this fashion is called “sign-magnitude” representation since the left most digit can be
used to indicate the sign and the remaining digits the magnitude or value of the number.

But how do we represent signed binary numbers if all we have is a

bunch of one’s and zero’s. We know that binary digits, or bits only have two values, either a “1”
or a “0” and conveniently for us, a sign also has only two values, being a “+” or a “–“.

Then we can use a single bit to identify the sign of a signed binary
number as being positive or negative in value. So to represent a positive binary number (+n) and
a negative (-n) binary number, we can use them with the addition of a sign.

For signed binary numbers the most significant bit (MSB) is used
as the sign bit. If the sign bit is “0”, this means the number is positive in value. If the sign bit is
“1”, then the number is negative in value. The remaining bits in the number are used to represent
the magnitude of the binary number in the usual unsigned binary number format way.

Then we can see that the Sign-and-Magnitude (SM) notation stores

positive and negative values by dividing the “n” total bits into two parts: 1 bit for the sign and n–
1 bits for the value which is a pure binary number. For example, the decimal number 53 can be
expressed as an 8-bit signed binary number as follows.

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Representation of real numbers:-

The goal is to represent a number with a decimal point in binary (for example, 101.01, which is
not read one hundred one point zero one because it is in fact a binary number, i.e. 5.25 in
decimal) using the form 1.XXXXX... * 2n (in our example, 1.0101*22). IEEE standard 754
defines how to encode a real number.
This standard offers a way to code a number using 32 bits, and defines three components:

 the plus/minus sign is represented by one bit, the highest-weighted bit (furthest to the
left)
 the exponent is encoded using 8 bits immediately after the sign
 the mantissa (the bits after the decimal point) with the remaining 23 bits

Thus, the coding follows the form:

seeeeeeeemmmmmmmmmmmmmmmmmmmmmmm

 the s represents the sign bit.

 each e represents an exponent bit
 each m represents a mantissa bit

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However, there are some restrictions for exponents:

 the exponent 00000000 is forbidden

 the exponent 11111111 is forbidden However, they are sometimes used to report errors.
This numeric configuration is called NaN, for Not a number.
 127 (01111111) must be added to the exponent in order to convert the decimal to a real
number in binary. The exponents, therefore, can range from -254 to 255

Thus, the formula for expressing real numbers is:

(-1)^S * 2^( E - 127 ) * ( 1 + F )

where:

 S is the sign bit and so 0 is understood as positive ( -1^0=1 ).

 E is the exponent to which 127 must be added to obtain the encoded equivalent.
 F is the fraction part, the only one which is expressed, and which is added to 1 to perform
the calculation.

Here is an example:
The value 525.5 is to be encoded.

 525.5 is positive, so the first bit will be 0.

 Its representation in base 2 is: 1000001101.1
 By normalising it, we get: 1.0000011011*2^9
 Adding 127 to the exponent, which is 9, gives 136, or in base 2: 10001000
 The mantissa is composed of the decimal part of 525.5 in normalised base 2, which is
0000011011.
 As the mantissa must take up 23 bits, zeroes must be added to complete it:
00000110110000000000000
 The binary representation of 525.5 under IEEE standard 754 is therefore:
0 1000 1000 00000110110000000000000
0100 0100 0000 0011 0110 0000 0000 0000 (4403600 in hexadecimal)

Here is another example, this time using a negative real number :

The value -0.625 is to be encoded.

 The s bit is 1, as 0.625 is negative.

 0.625 is written in base 2 as follows: 0.101
 We want to write it in the form 1.01 x 2-1
 Consequently, the exponent is worth 1111110 as 127 - 1 = 126 (or 1111110 in binary)
 The mantissa is 01000000000000000000000 (only the digits after the decimal point are
represented, as the whole number is always equal to 1)
 The binary representation of the number 0.625 under IEEE standard 754 is:
1 1111 1110 01000000000000000000000
1111 1111 0010 0000 0000 0000 0000 0000 (FF 20 00 00 in hexadecimal)

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Representation of Characters:-

Binary Dec Ascii Binary Dec Ascii Binary Dec Ascii Binary Dec Ascii
000 010 100 110
0 NUL 32 space 64 @ 96 `
0000 0000 0000 0000
000 010 100 110
1 SOH 33 ! 65 A 97 a
0001 0001 0001 0001
000 010 100 110
2 STX 34 " 66 B 98 b
0010 0010 0010 0010
000 010 100 110
3 ETX 35 # 67 C 99 c
0011 0011 0011 0011
000 010 100 110
4 EOT 36 $ 68 D 100 d
0100 0100 0100 0100
000 010 100 110
5 ENQ 37 % 69 E 101 e
0101 0101 0101 0101
000 010 100 110
6 ACK 38 & 70 F 102 f
0110 0110 0110 0110
000 010 100 110
7 BEL 39 ' 71 G 103 g
0111 0111 0111 0111
000 010 100 110
8 BS 40 ( 72 H 104 h
1000 1000 1000 1000
000 010 100 110
9 HT 41 ) 73 I 105 i
1001 1001 1001 1001
000 010 100 110
10 LF 42 * 74 J 106 j
1010 1010 1010 1010
000 010 100 110
11 VT 43 + 75 K 107 k
1011 1011 1011 1011
000 010 100 110
12 FF 44 , 76 L 108 l
1100 1100 1100 1100
000 010 100 110
13 CR 45 -­- 77 M 109 m
1101 1101 1101 1101
000 010 100 110
14 SO 46 . 78 N 110 n
1110 1110 1110 1110
000 010 100 110
15 SI 47 / 79 O 111 o
1111 1111 1111 1111
001 011 101 111
16 DLE 48 0 80 P 112 p
0000 0000 0000 0000

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 001 011 101 111
17 DC1 49 1 81 Q 113 q
0001 0001 0001 0001
001 011 101 111
18 DC2 50 2 82 R 114 r
0010 0010 0010 0010
001 011 101 111
19 DC3 51 3 83 S 115 s
0011 0011 0011 0011
001 011 101 111
20 DC4 52 4 84 T 116 t
0100 0100 0100 0100
001 011 101 111
21 NAK 53 5 85 U 117 u
0101 0101 0101 0101
001 011 101 111
22 SYN 54 6 86 V 118 v
0110 0110 0110 0110
001 011 101 111
23 ETB 55 7 87 W 119 w
0111 0111 0111 0111
001 011 101 111
24 CAN 56 8 88 X 120 x
1000 1000 1000 1000
001 011 101 111
25 EM 57 9 89 Y 121 y
1001 1001 1001 1001
001 011 101 111
26 SUB 58 : 90 Z 122 z
1010 1010 1010 1010
001 011 101 111
27 ESC 59 ; 91 [ 123 {
1011 1011 1011 1011
001 011 101 111
28 FS 60 < 92 \ 124 |
1100 1100 1100 1100
001 011 101 111
29 GS 61 = 93 ] 125 }
1101 1101 1101 1101
001 011 101 111
30 RS 62 > 94 ^ 126 ~
1110 1110 1110 1110
001 011 101 110
31 US 63 ? 95 _ 127 DEL
1111 1111 1111 0000

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 Digital or Binary Codes:-

In the coding, when numbers, letters or words are represented

by a specific group of symbols, it is said that the number, letter or word is being encoded. The
group of symbols is called as a code. The digital data is represented, stored and transmitted as
group of binary bits. This group is also called as binary code. The binary code is represented by
the number as well as alphanumeric letter.

Advantages of binary code:

Following is the list of advantages that binary code offers.

 Binary codes are suitable for the computer applications.

 Binary codes are suitable for the digital communications.
 Binary codes make the analysis and designing of digital circuits if we use the binary
codes.
 Since only 0 & 1 are being used, implementation becomes easy.

Classification of binary codes:-

The codes are broadly categorized into following four categories.

 Weighted Binary Codes

 Non-Weighted Codes
 Gray Code
 Binary Coded Decimal Code

Weighted Binary Code:-

Weighted binary codes are those binary codes which obey the positional
weight principle. Each position of the number represents a specific weight. Several systems of
the codes are used to express the decimal digits 0 through 9. In these codes each decimal digit is
represented by a group of four bits.

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Non weighted codes:-

In this type of binary codes, the positional weights are not assigned. The
examples of non-weighted codes are Excess-3 code and Gray code.

Excess-3 codes:- The Excess-3 code is also called as XS-3 code. It is non-weighted code used to
express decimal numbers. The Excess-3 code words are derived from the 8421 BCD code words
adding (0011)2 or (3)10 to each code word in 8421. The excess-3 codes are obtained as follows-

Example:-

Gray Code:-
It is the non-weighted code and it is not arithmetic codes. That means there
are no specific weights assigned to the bit position. It has a very special feature that, only one bit
will change each time the decimal number is incremented as shown in fig. As only one bit
changes at a time, the gray code is called as a unit distance code. The gray code is a cyclic code.
Gray code cannot be used for arithmetic operation.

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Applications of gray code:-

 Gray code is popularly used in the shaft position encoders.

 A shaft position encoder produces a code word which represents the angular position of
the shaft.

Binary to Gray Conversion:-

1. The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the given
binary code.
2. Other bits of the output gray code can be obtained by XORing binary code bit at that
index and previous index.

Example:- Binary : 0011

Gray : 0010

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Gray to Binary Conversion:-

This gray to binary conversion method also uses the working concept of
EX-OR logic gate among the bits of gray as well as binary bits.

1. The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the
given binary number.
2. Other bits of the output binary code can be obtained by checking gray code bit at that
index. If current gray code bit is 0, then copy previous binary code bit, else copy invert of
previous binary code bit.

Example:- Binary : 0011

Gray : 0010

Binary Coded Decimal (BCD) :-

In this code each decimal digit is represented by a 4-bit binary

number. BCD is a way to express each of the decimal digits with a binary code. In the BCD, with
four bits we can represent sixteen numbers (0000 to 1111). But in BCD code only first ten of
these are used (0000 to 1001). The remaining six code combinations i.e. 1010 to 1111 are invalid
in BCD.

for example, 35710 (Three Hundred and Fifty Seven) in decimal would be presented in Binary
Coded Decimal as:

35710 = 0011 0101 0111 (BCD)

Then we can see that BCD uses weighted codification, because the binary bit of each 4-bit group
represents a given weight of the final value. In other words, the BCD is a weighted code and the
weights used in binary coded decimal code are 8, 4, 2, 1, commonly called the 8421 code as it
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forms the 4-bit
bit binary representation of the relevant decimal digit.

Advantages of BCD Codes:-

 It is very similar to decimal system.

 We need to remember binary equivalent of decimal numbers 0 to 9 only.

Disadvantages of BCD Codes:--

 The addition and subtraction of BCD have different rules.

 The BCD arithmetic is little more complicated
 BCD needs more number of bits than binary to represent the decimal number. So BCD is
less efficient than binary.

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Arithmetic in 1's and 2's complement:-

Binary Number System is one the type of most popular Number

Representation techniques that used in digital systems. In the Binary System, there are only two
symbols or possible digit values, i.e., 0 (off) and 1 (on). Represented by any device that only 2
operating states or possible conditions.

Generally, there are two types of complement of Binary number:

1’s complement and 2’s complement. To get 1’s complement of a binary number, simply invert
the given number. For example, 1’s complement of binary number 110010 is 001101. To get 2’s
complement of binary number is 1’s complement of given number plus 1 to the least significant
bit (LSB). For example 2’s complement of binary number 10010 is (01101) + 1 = 01110.

Example-1: Find 1’s complement of binary number 10101110.

Simply invert each bit of given binary number, so 1’s complement of given number will be
01010001.

Example-2: Find 1’s complement of binary number 10001.001.

Simply invert each bit of given binary number, so 1’s complement of given number will be
01110.110.

Additions by 1’s Complement:-

There are difference scenario for addition of two binary numbers using 1’s complement. These
are explained as following below.

Case-1: Addition of positive and negative number when positive number has greater
magnitude:

When positive number has greater magnitude, then take simply 1’s complement of negative
number and the end-around carry of the sum is added to the least significant bit (LSB).

Example: Add 1110 and -1101.

So, take 1’s complement of 1101, which will be 0010, then add with given number. So,
1110+0010=1 0000 , then add this carry bit to the LSB, 0000+1=0001 , which is the answer.

Note that if the register size is big then fill the same value of MSB to preserve sign magnitude
for inputs and output.

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Case-2: Addition of positive and negative number when negative number has greater
magnitude:

When the negative number has greater magnitude, then take 1’s complement of negative number
and add with given positive number. Since there will not be any end-around carry bit, so take 1’s
complement of the result and this result will be negative.

Example: Add 1010 and -1100 in five-bit registers.

Note that there are five-bit registers, so these new numbers will be 01010 and -01100.
Now take 1’s complement of 01100 which will be 10011 and add 01010+10011=11101 . Then
take 1’s complement of this result, which will be 00010 and this will be negative number, i.e., -
00010, which is the answer.

Case-3: Addition of two negative numbers:

You need to take 1’s complement for both numbers, then add these 1’s complement of numbers.
Since there will always be end-around carry bit, so add this again to the MSB of result. Now,
take 1’s complement also of previous result, so this will be negative number.

Alternatively, you can add both negative number directly, and get this result which will be
negative only.

Example: add -1010 and -0101 in five bit-register.

These five bit numbers are -01010 and -00101. Add complements of these numbers,
10101+11010 =1 01111 . Since, there is a carry bit 1, so add this to the LSB of result, i.e.,
01111+1=10000 . Now take the 1’s complement of this result, which will be 01111 and this
number is negative, i.e, -01111, which is answer.

Subtractions by 1’s Complement:-

The algorithm to subtract two binary number using 1’s complement is explained as following
below:

 Take 1’s complement of the subtrahend

 Add with minuend
 If the result of above addition has carry bit 1, then add it to the least significant bit (LSB)
of given result
 If there is no carry bit 1, then take 1’s complement of the result which will be negative

Note that subtrahend is number that to be subtracted from the another number, i.e., minuend.

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Example (Case-1: When Carry bit 1): Evaluate 10101 - 00101

According to above algorithm, take 1’s complement of subtrahend 00101, which will be 11010,
then add both of these. So, 10101 + 11010 =1 01111 . Since, there is carry bit 1, so add this to
the LSB of given result, i.e., 01111+1=10000 which is the answer.

Example (Case-2: When no Carry bit): Evaluate 11001 - 11100

According to above algorithm, take 1’s complement of subtrahend 11110, which will be 00011.
Then add both of these, So, 11001 + 00011 =11100 . Since there is no carry bit 1, so take 1’s
complement of above result, which will be 00011, and this is negative number, i.e, 00011, which
is the answer.

2’s complement of a binary number is 1 added to the 1’s complement of the binary number.
Examples:

2's complement of "0111" is "1001"

2's complement of "1100" is "0100"

Subtracting using 2s complement:-

For subtracting a smaller number from a larger number, the 2s complement method is as
follows:

1. Determine the 2s complement of the smaller number.

2. Add the 2s complement to the larger number.

3. Discard the final carry (there is always one in this case)

Example:

11001 - 10011

Result from Step1: 01101

Result from Step2: 100110

Result from Step3: 00110

Again, to verify, note that 25 - 19 = 6

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For subtracting a larger number from a smaller number, the 2s complement method is as follows:

1. Determine the 2s complement of the larger number.

2. Add the 2s complement to the smaller number.

3. There is no carry from the left-most column. The result is in 2s complement form and is
negative.

4. Change the sign and take the 2s complement of the result to get the final answer.

Example:

1001 - 1101

Result from Step1: 0011

Result from Step2: 1100

Result from Step3: -0100

Again to verify, note that 9 - 13 = - 4

Addition using 2s complement:-

A. Addition of a positive number and a negative number:-

We consider the following cases.

Case I: When the positive number has a greater magnitude
In this case the carry which will be generated is discarded and the final result is the result of
addition.
In a 5-bit register find the sum of the following by using 2’s complement:

(i) -1011 and -0101

Solution:
+1011 ⇒ 01011
-0101 ⇒ 11011 (2’s complement)

(Carry 1 discarded) 00110

Hence the sum is + 0110.

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(ii) + 0111 and – 0011.
Solution:
+0111 ⇒ 00111

-0011 ⇒ 11101

(Carry 1 discarded) 00100

Hence the sum is + 0100.

Case II: When the negative number is greater.

When the negative numbers is greater no carry will be generated in the sign bit. The result of
addition will be negative and the final result is obtained by taking 2’s complement of the
magnitude bits of the result.

In a 5-bit register find the sum of the following by using 2’s complement:

(i) + 0 0 1 1 and - 0 1 0 1
Solution:
+0011 ⇒ 00011

-0101 ⇒ 11011 (2’s complement)

11110
2’s complement of 1110 is (0001 + 0001) or 0010.
Hence the required sum is - 0010.

(ii) + 0 1 0 0 and - 0 1 1 1
Solution:
+0100 ⇒ 00100

-0111 ⇒ 11001 (2’s complement)

11101
2’s complement of 1101 is 0011.
Hence the required sum is – 0011.

B. When the numbers are negative.

When two negative numbers are added a carry will be generated from the sign bit which will be
discarded. 2’s complement of the magnitude bits of the operation will be the final sum.

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In a 5-bit register find the sum of the following by using 2’s complement:
(i) – 0011 and – 0101
Solution:
-0011 ⇒ 11101 (2’s complement)

-0101 ⇒ 11011 (2’s complement)

(Carry 1 discarded) 11000

2’s complement of 1000 is (0111 + 0001) or 1000.
Hence the required sum is – 1000.

(ii) -0111 and – 0010.

Solution:
-0111 ⇒ 11001 (2’s complement)

-0010 ⇒ 11110 (2’s complement)

(Carry 1 discarded) 10111

2’s complement of 0111 is 1001.
Hence the required sum is – 1001.

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Unit -II

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Boolean Algebra:-
In mathematics and mathematical logic, Boolean algebra is the
branch of algebra in which the values of the variables are the truth values true and false, usually
denoted 1 and 0 respectively. Instead of elementary algebra where the values of the variables are
numbers, and the prime operations are addition and multiplication.

Boolean Algebra is used to analyze and simplify the digital (logic)

circuits. It uses only the binary numbers i.e. 0 and 1. It is also called as Binary Algebra or
logical Algebra. Boolean algebra was invented by George Boole in 1854.

Rule in Boolean Algebra:-

Following are the important rules used in Boolean algebra.

 Variable used can have only two values. Binary 1 for HIGH and Binary 0 for LOW.
 Complement of a variable is represented by an overbar (-). Thus, complement of variable
B is represented as . Thus if B = 0 then = 1 and B = 1 then = 0.
 ORing of the variables is represented by a plus (+) sign between them. For example
ORing of A, B, C is represented as A + B + C.
 Logical ANDing of the two or more variable is represented by writing a dot between
them such as A.B.C. Sometime the dot may be omitted like ABC.

Binary Valued Quantities:-

Binary valued quantities can be 0 or 1, true or false, right or wrong. There
are only two possible values. Binary data is data whose unit can take only two possible states,
traditionally labeled 0 and in 1 accordance with the binary numeral system and Boolean algebra.
Binary variables are also known as Boolean Variables. Boolean variable can have only two
values, 0 and 1.

Logical Operations:-
There are three basic operations. These are used often in Boolean expressions
but are also used to create more complex operations.

Operator Symbol Precedence

NOT ‘ Highest
AND . Middle
Lowest
OR +

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Basic Postulates of Boolean Algebra:-

Boolean Algebra Laws are used to simplify boolean expressions.

Basic Boolean Algebra Laws

1. Idempotent Law
o A*A=A
o A+A=A
2. Associative Law
o (A * B) * C = A * (B * C)
o (A + B) + C = A + (B + C)
3. Commutative Law
o A*B=B*A
o A+B=B+A
4. Distributive Law
o A * (B + C) = A * B + A * C
o A + (B * C) = (A + B) * (A + C)
5. Identity Law
o A*0=0 A*1=A
o A+1=1 A+0=A
6. Complement Law
o A * ~A = 0
o A + ~A = 1
7. Involution Law
o ~(~A) = A
8. DeMorgan’s Law
o ~(A * B) = ~A + ~B
o ~(A + B) = ~A * ~B

Redundancy Laws

9. Absorption
o A + (A * B) = A
o A * (A + B) = A
o (A * B) + (A * ~B) = A
o (A + B) * (A + ~B) = A
o A + (~A * B) = A + B
o A * (~A + B) = A * B

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Rules for Boolean Algebra:-

25
Principle of Duality:-

The principle of duality in Boolean algebra states that if you have a

true Boolean statement (equation) then the dual of this statement (equation) is true. The dual of a
boolean statement is found by replacing the statement’s symbols with their counterparts. This
means a “0” becomes a “1”, “1” becomes a “0”, “+” becomes a “.” and “.” becomes a “+”.

Here’s an example of the principle of duality in Boolean algebra:

Suppose we have the following true Boolean statement (equation):

(*) 1 + 0 = 1

The dual of this statement is:

(**) 0 . 1 = 0

As we can see, the dual of the true Boolean statement (*) is (**). We found (**) by replacing
each symbol from (*) with its Boolean counterpart as described above. Clearly, (**) is also a true
Boolean statement.

De-Morgan's Theorem:-
De-Morgan, a mathematician who knew Boole, proposed
two theorems that are an important part of Boolean Algebra. In practical terms, De-Morgan's
theorems provide mathematical verification of the equivalency of the NAND and negative-OR
gates and the equivalency of the NOR and negative-AND gates.

Theorem 1- The complement of a product of variables is equal to the sum of the complements of
the variables.

Theorem 2- The complement of a sum of variables is equal to the product of the complements
of the variables.

26
Ex.-

27
28
Proof of De-Morgan's Theorem 2:

For any theorem X=Y, if we can show that X Y = 0, and that X + Y = 1, then
by the complement postulates, A A = 0 and A + A = 1,
X = Y. By the uniqueness of the complement, X = Y.
Thus the proof consists of showing that (A*B)*( A + B) = 0; and also that (A*B) + ( A + B) = 1.

Prove: (A*B)*( A + B) = 0
(A*B)*( A + B) = (A*B)*A + (A*B)*B) by distributive postulate
= (A*A)*B + A*(B*B) by associativity postulate
= 0*B + A*0 by complement postulate
=0+0 by nullity theorem
=0 by identity theorem
(A*B)*( A + B) = 0 Q.E.D.

Prove: (A*B) + ( A + B) =1
(A*B) + ( A + B) =(A + A + B))*(B + A + B) by distributive ***
(A*B) + ( A + B) =(A + A + B))*(B + B + A) by associativity postulate
=(1 + B)*(1 + A) by complement postulate
=1*1 by nullity theorem
=1 by identity theorem
(A*B) + ( A + B) =1 Q.E.D.

*** by distributivity B*C + A = (B + A)*(C + A)

29
Finding complements of the Boolean expressions:-

1. F = X'YZ' + X'Y'Z

Sol:-

Complement of F is F'

F' = ( X'YZ' + X'Y'Z)'

= (X'YZ')' . (X'Y'Z)'

= ( X + Y' + Z ) . (X + Y + Z')

2. F = X(Y'Z' + YZ)

Sol:-

F' = [X(Y'Z' + YZ)]'

= X' + (Y'Z' + YZ) '

= X' + (Y'Z')' . (YZ)'

= X' + (Y+Z) . (Y'Z')

= X' + YY' + YZ' +Y'Z + ZZ'

= X' + YZ' +Y'Z

Minterm and Maxterm of Boolean Function:-

Each row of a truth table can be associated with a minterm and a maxterm.

A minterm l is a product (AND) of all variables in the function, in direct or complemented form.
A minterm has the property that it is equal to 1 on exactly one row of the truth table.

A maxterm 0 is a sum (OR) of all the variables in the function, in direct or complemented form.
A maxterm has the property that it is equal to 0 on exactly one row of the truth table.

30
Truth Table:

Minterm we indicate that-

F = m0 + m4 +m7 = a'b'c' + ab'c' + abc

Maxterm is-

F = m1 . m2 . m3 . m5 . m6

= (a+b+c').(a+b'+c).(a+b'+c').(a'+b+c').(a'+b'+c)

Standard forms of Boolean Expressions:-

All Boolean expressions, regardless of their form, can be converted into
either of two standard forms-

1. Sum of Products (SOP)

2. Product of Sum (POS)

31
Sum of Products:-

Sum of Product is the abbreviated form of SOP. Sum of product form is a

form of expression in Boolean algebra in which different product terms of inputs are being
summed together. This product is not arithmetical multiply but it is Boolean logical AND and the
Sum is Boolean logical OR.

To understand better about SOP, we need to know about min term.

Min Term

Minterm means the term that is true for a minimum number of combination of inputs. That is
true for only one combination of inputs. Since AND gate also gives True only when all of its
inputs are true so we can say min terms are AND of input combinations like in the table given
below.

3 inputs have 8 different combinations. Each combination has a min terms denoted by
small m and its decimal combination number written in subscript. Each of these minterms will be
only true for the specific input combination.

There are three different forms of Sum of Product:-

 Canonical SOP Form

 Non-Canonical SOP Form
 Minimal SOP Form

32
Canonical SOP Form:-

This is the standard form of Sum of Product. It is formed by O Ring

the minterms of the function for which the output is true. This is also known as Sum of Min
terms or Canonical disjunctive normal form (CDNF). It is just a fancy name. “canonical” means
“standardized” and “disjunctive” means “Logical OR union”. Canonical SOP expression is
represented by summation sign ∑ and minterms in the braces for which the output is true. For
example, a functions truth table is given below.

For this function the canonical SOP expression is

F = ∑( m1, m2, m3, m5 )

Which means that the function is true for the min terms {1, 2, 3, 5}.

By expanding the summation we get.

F = m1 + m2 + m3 + m5

Now putting min terms in the expression

F = A̅B̅C + A̅BC̅ + A̅BC + AB̅C

Canonical form contains all inputs either complemented or non-complemented in its product
terms.

33
Non-Canonical SOP Form:-

As the name suggests, this form is the non-standardized form of SOP

expressions. The product terms are not the min terms but they are simplified. Let’s take the
above function in canonical form as an example.

F = A̅B̅C + A̅BC̅ + A̅BC + AB̅C

F = A̅B̅C + A̅B(C̅ + C) + AB̅C

F = A̅B̅C + A̅B(1) + AB̅C

F = A̅B̅C + A̅B + AB̅C

This expression is still in Sum of Product form but it is non-canonical or non-standardized form.

Minimal SOP Form:-

This form is the most simplified SOP expression of a function. It is also a

form of non-canonical form. Minimal SOP form can be made using Boolean algebraic theorems
but it is very easily made using Karnaugh map (K-map). Minimal SOP form is preferred because
it uses the minimum number of gates and input lines. it is commercially beneficial because of its
compact size, fast speed, and low fabrication cost. Let’s take an example of the function given
above in canonical form.

34
it's K-map is given below-

According to the K-map, the output expression will be:- F = B̅C + A̅B

This is the most simplified & optimized expression for the said function. This
expression requires only two 2-input AND gates & one 2-input OR gate. However, the canonical
form needs four 3-input AND gates & one 4-input OR gate, which is relatively more costly than
minimal form implementation.

Product of Sums:-

The product of Sum form is a form in which products of different sum terms
of inputs are taken. These are not arithmetic product and sum but they are logical Boolean AND
and OR respectively. To better understand about Product of Sum, we need to know about Max
term.

Max Term

Maxterm means the term or expression that is true for a maximum number of
input combinations or that is false for only one combination of inputs. Since OR gate also gives
false for only one input combination. So Maxterm is OR of either complemented or non-
complemented inputs. Max terms for 3 input variables are given below.

35
 3 inputs have 8 different combinations so it will have 8 maxterms. Maxterms
are denoted by capital M and decimal combination number In the subscript as shown in the table
given above. In maxterm, each input is complemented because Maxterm gives ‘0’ only when the
mentioned combination is applied and Maxterm is complement of minterm.

M3 = m̅3
M3 = (A̅BC)’
M3 = A + B̅ +C̅ DE Morgan’s law

Which is why for A=0 Max term consist A & for A=1 Max term consist A̅.

There are three types of Product of Sum forms.

 Canonical POS Form

 Non – Canonical Form
 Minimal POS Form

36
Canonical POS Form:-

It is also known as Product of Max term or Canonical conjunctive normal

form (CCNF). Canonical means standard and conjunctive means intersection. In this form,
Maxterms are AND together for which output is false. Canonical POS expression is represented
by ∏ and Maxterms for which output is false in brackets as shown in the example given below.

F = ∏ (M0, M4, M6, M7)

Expanding the product
F = M0.M4.M6.M7
Putting Max terms
F = (A+B+C)(A̅+B+C)(A̅+B̅+C)(A̅+B̅+C̅)

The canonical form contains all inputs either complemented or non-complemented in its each
Sum term.

Non – Canonical Form:-

The product of sum expression that is not in standard form is called non-
canonical form. Let’s take the above-given function as an example.
F = (A+B+C)(A̅+B+C)(A̅+B̅+C)(A̅+B̅+C̅)
F = (B+C) (A̅+B̅+C)(A̅+B̅+C̅)
Same but inverted terms eliminates from two Max terms and form a single term to prove it here
is an example.
= (A+B+C) (A̅+B+C)
= AA̅+AB+AC+A̅B+BB+BC+A̅C+BC+CC
= 0+AB+AC+A̅B+A̅C+B+BC+C
= A(B+C)+A̅(B+C)+B(1+C)+C
= (B+C)(A+A̅)+B(1)+C
= (B+C)(0)+B+C
= B+C
The expression achieved is still in Product of Sum form but it is non-canonical form.

37
Minimal POS Form:-

This is the most simplified and optimized form of a POS expression which is
non-canonical. Minimal Product of Sum form can be achieved using Boolean algebraic theorems
like in the non-canonical example given above. Another method of achieving minimal POS form
is by using Karnaugh map which is comparatively easier than using Boolean algebraic theorems.
Minimal POS form uses less number of inputs and logic gates during its implementation, that’s
why they are being preferred over canonical form for their compact,fast and low-cost
implementation. Let’s take the above-given function as example K-map of the function

Minimal expression using K-map

F = (B+C) (A̅+B̅)

The achieved expression is the minimal product of sum form. It is still Product of Sum
expression But it needs only 2 inputs two OR gates and a single 2 input AND gate. However, the
canonical form needs 4 OR gates of 3 inputs and 1 AND gate of 4 inputs.

Simplification of SOP Boolean Expressions using Karnaugh map - 3 variables Boolean

function:-

Karnaugh Map:- A Karnaugh map provides a systematic method for simplifying Boolean
expressions and, if properly used, will produce the simplest SOP or POS expression possible,
known as the minimum expression. We know that effectiveness of algebraic simplification
depends on your familiarity with all the laws, rules and theorems of Boolean algebra and on
your ability to apply them.

38
 A Karnaugh map is similar to a truth table because it presents all of
the possible values of input variables and the resulting output for each value. Instead of being
organized into columns and rows like a truth tab le, the karnaugh map is an array of cells in
which each cell represents a binary value of the input variables. The cells are arranged in a way
so that simplification of given expressions with two, three, four and five variables.

3- variable Karnaugh Map:-

Karnaugh maps can be modified to handle a greater number of

inputs. For example, combining two two-variable maps together can create a three-variable
Karnaugh map. Figure shows a three-variable truth table and a three-variable Karnaugh map.
Here x1 and x2 identify the rows of the map and x3 identifies the columns. To assure that all the
minterms in the adjacent cells of the map can be combined into a single product term, the
adjacent cells must differ by only one bit position. As you may notice, the values of x1 and x2
count in the order 00, 01, 11, 10 rather than the usual 00, 01, 10, 11. This ensures that each cell
varies by only one bit position from each adjacent cell. The map also wraps around itself, so the
top and bottom cells are also adjacent to each other. The cell adjacency of a Karnaugh map obeys
the Gray code, which consists of a sequence of code where each value differs by only one bit
position at a time.

39
4- variable Karnaugh Map:-

The 4-variable Karnaugh map is an array of sixteen cells, as shown in Figure(a). Binary
values of A and B are along the left side and the values of C and D are across the top. The value
of a given cell is the binary values of A and B at the left in the same row combined with the
binary values of C and D at the top in the same column. For example, the cell in the upper right
corner has a binary value of 0010 and the cell in the lower right corner has a binary value of
1010. Part (b) of the figure shows the standard product terms, which are represented by each cell
in the 4-variable Karnaugh map.

40
Mapping a Standard SOP Expression using 3 variables:-

Karnaugh map is used for simplifying Boolean expressions to their minimum

form. A minimized SOP expression contains the fewest possible terms with the fewest possible
variables per term. Generally, a minimum SOP expression can be implemented with fewer logic
gates than a standard expression. For an SOP expression in standard form, a 1 is placed on the
Karnaugh map for each product term in the expression. For example, for the product term AB'C,
a 1 goes in the 101 cell on a 3-variable map. When an SOP expression is completely mapped, the
number of 1 s on the Karnaugh map equal to the number of product terms in the standard SOP
expression. The cells that do not have a 1 are the cells for which the expression is 0. Usually,
when working with SOP expressions, the 0s are left off the map. The following steps and the
illustration in Figure show the mapping process.

Step 1. Determine the binary value of each product term in the standard SOP expression. After
some practice, you can usually do the evaluation of terms mentally.

Step 2. As each product term is evaluated, place a 1 on the Karnaugh map in the cell having the
same value as the product term. A Boolean expression must first be in standard form
before you use a Karnaugh map. If an expression is not in standard form, then it must be
converted to standard form by the procedure covered in earlier discussion or by
numerical expansion. Since an expression should be evaluated before mapping anyway,
numerical expansion is probably the most efficient approach.

41
42
Mapping a Standard SOP Expression using 4 variables:-

43
Ex:-

44
Unit - III

45
Basic Logic Gates:-
In electronics, Logic gates are the building blocks of every electronic
circuit. Logic gates defined as the simple electronic circuits having one or more input and a
single output. Their operation varies from one type of logic gate to another. The relationship
between input and output follow a certain logical equation.
Logic gate can be defined as a simple boolean function, which means
that it has only either of two outputs. Either 1 or 0, high or low, true or false, whatever you can
call it. It is the most elementary tool in building a circuit. A logic gate performs a logical
operation on input and gives the appropriate output for it.
The relationship between the i/p and the o/p is based on a certain logic.
These gates are implemented using electronic switches like transistors, diodes. But, in practice
basic logic gates are built using CMOS technology, FETS and MOSFET(Metal Oxide
Semiconductor FET)s. Logic gates are used in microprocessors, microcontrollers, embedded
system applications and in electronic and electrical project circuits.

Types of Logic Gates:-

The basic logic gates are categorized into seven: AND, OR, XOR, NAND,
NOR, XNOR and NOT. These logic gates with their logic gate symbols and truth tables are
explained below.

46
AND Gate:-

The AND gate is a digital logic gate with ‘n’ i/ps one o/p, which perform
logical conjunction based on the combinations of its inputs.The output of this gate is true only
when all the inputs are true. When one or more inputs of the AND gate’s i/ps are false, then only
the output of the AND gate is false. The symbol and truth table of an AND gate with two inputs
is shown below.

OR Gate:-

The OR gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs a
logical conjunction based on the combinations of its inputs.The output of the OR gate is true
only when one or more inputs are true. If all the i/ps of the gate are false, then only the output of
the OR gate is false. The symbol and truth table of an OR gate with two inputs is shown below.

47
NOT Gate:-

The NOT gate is a digital logic gate with one input and one output that
operates an inverter operation of the input. The output of the NOT gate is the reverse of the
input. When the input of the NOT gate is true then the output will be false and vice versa. The
symbol and truth table of a NOT gate with one input is shown below. By using this gate, we can
implement NOR and NAND gates.

NAND Gate:-

The NAND gate is a digital logic gate with ‘n’ i/ps and one o/p, that
performs the operation of the AND gate followed by the operation of the NOT gate. NAND gate
is designed by combining the AND and NOT gates. If the input of the NAND gate high, then the
output of the gate will be low. The symbol and truth table of the NAND gate with two inputs is
shown below.

48
NOR Gate:-

The NOR gate is a digital logic gate with n inputs and one output, that
performs the operation of the OR gate followed by the NOT gate. NOR gate is designed by
combining the OR and NOT gate. When any one of the i/ps of the NOR gate is true, then the
output of the NOR gate will be false. The symbol and truth table of the NOR gate with truth table
is shown below.

Exclusive-OR Gate (XOR):-

The Exclusive-OR gate is a digital logic gate with two inputs and one
output. The short form of this gate is Ex-OR. It performs based on the operation of OR gate. . If
any one of the inputs of this gate is high, then the output of the EX-OR gate will be high. The
symbol and truth table of the EX-OR are shown below.

49
 This logic gate symbol is seldom used in Boolean expressions because the
identities, laws, and rules of simplification involving addition, multiplication, and
complementation do not apply to it. However, there is a way to represent the Exclusive-OR
function in terms of OR and AND, as has been shown as: AB’ + A’B

As a Boolean equivalency, this rule may be helpful in simplifying some

Boolean expressions. Any expression following the AB’ + A’B form (two AND gates and an OR
gate) may be replaced by a single Exclusive-OR gate.

50
Exclusive-NOR Gate(XNOR):-

The Exclusive-NOR gate is a digital logic gate with two inputs and one
output. The short form of this gate is Ex-NOR. It performs based on the operation of NOR gate. When
both the inputs of this gate are high, then the output of the EX-NOR gate will be high. But, if any one of
the inputs is high (but not both), then the output will be low. The symbol and truth table of the EX-NOR
are shown below.

The expression of XNOR operation can be realized by using two NOT gates, two AND gates and
one OR gate as followers,

NOR gate is a NOT gate followed by an XOR gate. As we know that XOR operation of
inputs A and B is A ⊕ B, therefore XNOR operation those inputs will be (A + B) ̅. That means,
output of XOR gate is inverted in XNOR gate. In XOR operation, the output is only 1 when only
one input is 1. The output is logical 0 when both inputs are same that means they are either 1 or
0. But in the case of XNOR gate, the output is 0 when only one input is 0 and the output is 1
when both inputs are same that is either both of them are 0 or 1.

51
Logic Gates Formulas:-

This is all about the basic logic gates, which includes AND gate, OR gate,
NAND gate, NOR gate, EX-OR gate and EX-NOR gate. In this, AND, NOT and OR gates are
the basic logic gates. By using these gates we can create any logic gate by combining them.
Where, NAND and NOR gates are called universal gates. These gates have a particular property
with which they can create any logical Boolean expression if designed in a proper way.

Basic Logic Gates:- AND, OR, NOT

Universal Logic Gates:- NAND, NOR

Combinational Circuits:-

Combinational Circuits (CC) are circuits made up of different types of logic gates.
A logic gate is a basic building block of any electronic circuit. The output of the combinational
circuit depends on the values at the input at any given time. The circuits do not make use of any
memory or storage device.

Block Diagram:-

52
Some of the characteristics of combinational circuits are following:-

 The output of combinational circuit at any instant of time, depends only on the levels
present at input terminals.
 The combinational circuit do not use any memory. The previous state of input does not
have any effect on the present state of the circuit.
 A combinational circuit can have an n number of inputs and m number of outputs.

The Adder:- An Adder is a digital circuit that is used to perform the addition of numeric
values. It is one of the most basic circuits and is found in Arithmetic Logic Units of computing
devices. There are two types of adders. Half Adders compute single digit numbers while Full
Adders compute larger numbers.

Half Adder:-

The Half Adder adds two single digit binary numbers and forms the
foundation for all addition operations in computing. If we have two single binary digits A and B
then the Half Adder adds them with the circuit carrying two outputs; the sum and the carry. The
carry represents any overflow from the addition of the two numbers. This is represented in the
following block diagram figure

Block Diagram:-

Truth Table:-

53
Logic Circuit:-

The sum S is represented by the Boolean Expression S = A'B + AB' and C = AB

Full Adder:-
The Full Adder overcomes the disadvantages of the half adder in that it can
add two single bit numbers in addition to the carry digit at its input as seen in Figure

Block Diagram:-

Truth Table:-

54
Logic Circuit:-

Boolean expression for the full adder is S= A'B'Cin + A'BCin' + AB'Cin' + ABCin

and C = A'BCin + AB'Cin + ABCin' + ABCin

where A and B are all the possible binary inputs and C is the Carry in

Example if A is 0 and B is 0 and the Cin is 1 then

S = (0'0'1)+(0'01')+(00'1')+(001) = (111)+(100)+(010)+(001) = (1)+(0)+(0)+(0) = 1

C = (0'01)+(00'1)+(001')+(001) = (101)+(011)+(000)+(001) = (0)+(0)+(0)+(0) = 0

S = 1 and C = 0

Parallel Binary Adder:-

The Parallel binary adder is a combinational circuit consists of various

full adders in parallel structure so that when more than 1-bit numbers are to be added, then there
can be full adder for every column for the addition. The number of full adders in a parallel binary
adder depends on the number of bits present in the number for the addition. If 4-bits numbers are
to be added, then there will be 4-full adder in the parallel binary adder. he parallel binary adder
can be designed with the help of basic logic gates. The sub-modules in the logic circuit will
resemble the logic circuit of half adder and full adder. To understand it clearly let’s put light on
designing and working of the 2-bit parallel binary adder.

55
Block Diagram:-

Logic circuit of 2-Bit Parallel Binary Adder

56
 The 2-Bit parallel adder can be designed with the help of EX-OR
(Exclusive OR) gate and AND gate. If you will carefully observe the logic circuit of 2-Bit
Parallel Binary Adder, you will notice 2-full adder are connected in a parallel manner. Now, you
can easily guess how this will work.

Half adder is a logic circuit which adds two 1-bit numbers but does not add
carry from previous addition. Therefore, full adders came into existence. A full adder can add
two 1-bit numbers along with the carry from previous addition. Now, coming back to the parallel
binary adder, it also has two full adders. When we start addition of two numbers, the first step we
follow is the addition of LSB (Least Significant Bits) of two numbers. After this, if we have any
carry we forward it to higher order columns. Now, the adder performs the similar task; it adds
the LSBs of both the numbers and if any carry bit is there it passes it to the carry-in terminal of
another.

Subtractor:-
A Subtractor is used to subtract one number from the other
another. Because we are dealing with binary digits, the 1s complement and 2s complement of the
numbers are used to achieve this. Three bits are involved in performing the basic subtraction: the
minuend (X), the subtrahend (Y) and the borrow (Bi) which is input from the previous bit. The
outputs are the difference (D) and the borrow bit (Bout).

Half Subtractor:-

When a subtraction is done between just two bits a Half Subtractor is

used, similar to the Half Adder. The Half Subtractor's combinational circuit is represented below.

Logic Circuit:-

57
Truth Table:-

D = X'Y + XY'

Bout = X'Y

Example, if our inputs X and Y are 0 and 1 then Compliment of 0 is 1 and vice versa

D = (0'1)+(01') = (11)+(00) = 1 and Bout = (0'1) = (11) = 1

Full Subtractor:-

The combinational circuit of the Full Subtractor performs a subtraction operation

on 3 bits, the minuend, the subtrahend and the borrow-in bits. The circuit generates two outputs
comprising of the calculated difference D and the borrow-out.

58
Truth Table:-

D= X'Y'Bin + X'YBin' + XY'Bin' + XYBin

Bout = X'Y'Bin + X'YBin' + X'YBin + XYBin

Example: When X = 1 Y = 0 and Bin = 1

D = (1'0'1)(1'01')(10'1')(101) = (011)+(000)+(110)+(101) = (0)+(0)+(0)+(0) = 0

Bout = (1'0'1)(1'01')(1'01)(101) = (011)+(000)+(001)+(101) = (0)+(0)+(0)+(0) = 0

Camparator:-

Comparator is a device that used in combinational logic systems

for comparing two binary numbers. It takes binary numbers as inputs and produces 3 outputs;
whether the numbers are greater than, less than or equal to each other. They are made of AND,
NOT & NOR Gates. The comparator is a decision-making device and it can be implemented in
various control devices. Comparator IC has 2 inputs and 3 outputs. These 3 outputs are
connected with separate operations.

59
Basic Operation Terms of Comparator:-

Consider two binary numbers “A” and “B” as inputs to the digital comparator

 LESS THAN:

1. If binary number “A” is less than “B” than “less than” output will produce HIGH state
“1” also known as true.
2. If binary number “A” is greater than or equal to “B” than “less than” output will produce
LOW state “0” also known as false.

 EQUAL TO:

1. If and only if number A is equal to number B than “equal to” output will produce logic
HIGH state “1”. Otherwise, the output will be LOW state “0”.

 GREATER THAN:

1. If number A is greater than B than “greater than” output will produce HIGH state”1”.
2. If A is less than or equal to B than “greater than” output will produce LOW state “0”.

Single Bit Comparator:-

This is the basic unit of a multi bit comparator which compares a single binary bit and produces
output according to those bits.

Less than :- The output of “less than” is represented by (A< B)

According to the truth table of Single Bit Comparator Sum of Product expression for A<B is

(A<B) = A̅B

Which can be implemented as:

Its output will be only true when “A” is less than “B”.

60
Equal to :- The output of “Equal to ” is represented by (A = B)

According to the truth table of Single Bit Comparator Sum of Product expression for A=B is

Which can be implemented as:

Observe the expression above. You will notice that XNOR expression is exactly the same. So it
can also be replaced with XNOR as shown in below figure We will represent it with ‘X’ such
that

X = A̅B̅ + AB = (A XNOR B)

It will be only true when both A and B bits are same.

Greater than :- The output of “less than” is represented by (A>B)

According to the truth table of Single Bit Comparator Sum of Product expression for A>B is

(A>B) = AB̅

Which can be implemented as:

Its output will be only true when “A” is greater than “B”.

61
Decoder:-

A decoder is a combinational circuit. It has n input and to a maximum

m = 2n outputs. Decoder is identical to a demultiplexer without any data input. It performs
operations which are exactly opposite to those of an encoder.

Block Diagram:-

Examples of Decoders are following.

 Code converters
 BCD to seven segment decoders
 Nixie tube decoders
 Relay actuator

2 to 4 Line Decoder:-

The block diagram of 2 to 4 line decoder is shown in the fig. A and B

are the two inputs where D through D are the four outputs. Truth table explains the operations of
a decoder. It shows that each output is 1 for only a specific combination of inputs.

Block Diagram:-

62
Truth Table:-

Logic Circuit:-

63
Encoder:-

Encoder is a combinational circuit which is designed to perform the inverse

operation of the decoder. An encoder has n number of input lines and m number of output lines.
An encoder produces an m bit binary code corresponding to the digital input number. The
encoder accepts an n input digital word and converts it into an m bit another digital word.

Block Diagram:-

Examples of Encoders are following.

 Priority encoders
 Decimal to BCD encoder
 Octal to binary encoder
 Hexadecimal to binary encoder

Priority Encoder:-

This is a special type of encoder. Priority is given to the input lines. If

two or more input line are 1 at the same time, then the input line with highest priority will be
considered. There are four input D0, D1, D2, D3 and two output Y0, Y1. Out of the four input D3
has the highest priority and D0 has the lowest priority. That means if D3 = 1 then Y1 Y1 = 11
irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1 Y0 = 10 irrespective of the
other inputs.

Block Diagram:-

64
Truth Table:-

Logic Circuit:-

65
Multiplexer:-
Multiplexer is a special type of combinational circuit. There are n-data
inputs, one output and m select inputs with 2m = n. It is a digital circuit which selects one of the
n data inputs and routes it to the output. The selection of one of the n inputs is done by the
selected inputs. Depending on the digital code applied at the selected inputs, one out of n data
sources is selected and transmitted to the single output Y. E is called the strobe or enable input
which is useful for the cascading. It is generally an active low terminal that means it will perform
the required operation when it is low.

Block Diagram:-

Multiplexers come in multiple variations

 2 : 1 multiplexer
 4 : 1 multiplexer
 16 : 1 multiplexer
 32 : 1 multiplexer

66
2:1 Multiplexer:-

The input A of this simple 2-1 line multiplexer circuit constructed from standard NAND gates
acts to control which input ( I0 or I1 ) gets passed to the output at Q.

From the truth table above, we can see that when the data select input, A is LOW at logic 0,
input I1 passes its data through the NAND gate multiplexer circuit to the output, while input I0 is
blocked. When the data select A is HIGH at logic 1, the reverse happens and now input I0 passes
data to the output Q while input I1 is blocked.

So by the application of either a logic “0” or a logic “1” at A we can select the appropriate input,
I0 or I1 with the circuit acting a bit like a single pole double throw (SPDT) switch.

As we only have one control line, (A) then we can only switch 21 inputs and in this simple
example, the 2-input multiplexer connects one of two 1-bit sources to a common output,
producing a 2-to-1-line multiplexer. We can confirm this in the following Boolean expression.

Q = A.I0.I1 + A.I0.I1 + A.I0.I1 + A.I0.I1

and for our 2-input multiplexer circuit above, this can be simplified too:

Q = A.I1 + A.I0

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We can increase the number of data inputs to be selected further simply by following the same
procedure and larger multiplexer circuits can be implemented using smaller 2-to-1 multiplexers
as their basic building blocks. So for a 4-input multiplexer we would therefore require two data
select lines as 4-inputs represents 22 data control lines give a circuit with four inputs, I0, I1, I2, I3
and two data select lines A and B as shown.

4: 1 Multiplexer:-

The Boolean expression for this 4-to-1 Multiplexer above with inputs A to D and data select
lines a, b is given as:

Q = abA + abB + abC + abD

In this example at any one instant in time only ONE of the four analogue switches is closed,
connecting only one of the input lines A to D to the single output at Q. As to which switch is
closed depends upon the addressing input code on lines “a” and “b“.

So for this example to select input B to the output at Q, the binary input address would need to
be “a” = logic “1” and “b” = logic “0”. Thus we can show the selection of the data through the
multiplexer as a function of the data select bits as shown.

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4:1 Multipplexer

Demultiplexers:-

A demultiplexer performs the reverse operation of a multiplexer

i.e. it receives one input and distributes it over several outputs. It has only one input, n outputs, m
select input. At a time only one output line is selected by the select lines and the input is
transmitted to the selected output line. Demultiplexers comes in multiple variations.

 1 : 2 demultiplexer
 1 : 4 demultiplexer
 1 : 16 demultiplexer
 1 : 32 demultiplexer

Block diagram:-

69
The truth table for a 1-to-2 demultiplexer is

4 Channel Demultiplexer using Logic Gates:-

70
Unit - IV

71
Sequential Circuits:-

The combinational circuit does not use any memory. Hence the
previous state of input does not have any effect on the present state of the circuit. But sequential
circuit has memory so output can vary based on input. This type of circuits uses previous input,
output, clock and a memory element.

Block Diagram:-

A synchronous circuit is a digital circuit in which the changes in the

state of memory elements are synchronized by a clock signal. In a sequential digital logic circuit,
data is stored in memory devices called flip-flops or latches. The output of a flip-flop is constant
until a pulse is applied to its "clock" input, upon which the input of the flip-flop is latched into its
output. In a synchronous logic circuit, an electronic oscillator called the clock generates a string
of pulses, the "clock signal". This clock signal is applied to every storage element, so in an ideal
synchronous circuit, every change in the logical levels of its storage components is simultaneous.
Ideally, the input to each storage element has reached its final value before the next clock occurs,
so the behavior of the whole circuit can be predicted exactly. Practically, some delay is required
for each logical operation, resulting in a maximum speed at which each synchronous system can
run.

Flip-Flop:-

Flip flop is a sequential circuit which generally samples its inputs and
changes its outputs only at particular instants of time and not continuously. Flip flop is said to be
edge sensitive or edge triggered rather than being level triggered like latches.

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Edge Triggerd Flip-Flop:-

An edge-triggered flip-flop changes states either at the positive edge (rising

edge) or at the negative edge (falling edge) of the clock pulse on the control input. The three
basic types are introduced here: S-R, J-K and D.

The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are
transferred to the flip-flop's output only on the triggering edge of the clock pulse. On the other
hand, the direct set (SET) and clear (CLR) inputs are called asynchronous inputs, as they are
inputs that affect the state of the flip-flop independent of the clock. For the synchronous
operations to work properly, these asynchronous inputs must both be kept LOW.

Pulse Triggered Flip Flops:-

The term pulse-triggered means that data are entered into the flip-flop
on the rising edge of the clock pulse, but the output does not reflect the input state until the
falling edge of the clock pulse. As this kind of flip-flops are sensitive to any change of the input
levels during the clock pulse is still HIGH, the inputs must be set up prior to the clock pulse's
rising edge and must not be changed before the falling edge. Otherwise, ambiguous results will
happen. The three basic types of pulse-triggered flip-flops are S-R, J-K and D. Their logic
symbols are shown below. Notice that they do not have the dynamic input indicator at the clock
input but have postponed output symbols at the outputs.

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S-R Flip Flop:-

It is basically S-R latch using NAND gates with an additional enable input.
It is also called as level triggered SR-FF. For this, circuit in output will take place if and only if
the enable input (E) is made active. In short this circuit will operate as an S-R latch if E = 1 but
there is no change in the output if E = 0.

Block Diagram:-

Circuit Diagram:-

Truth Table:-

74
Operation:-

S.N. Condition Operation

If S = R = 0 then output of NAND gates 3 and 4 are forced to
become 1.
1 S = R = 0 : No change
Hence R' and S' both will be equal to 1. Since S' and R' are the
input of the basic S-R latch using NAND gates, there will be no
change in the state of outputs.
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output
of NAND-4 i.e. S' = 0.
2 S = 0, R = 1, E = 1
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.
Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.
3 S = 1, R = 0, E = 1
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0.
This is the reset condition.
As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4
both are 0 i.e. S' = R' = 0.
4 S = 1, R = 1, E = 1
Hence the Race condition will occur in the basic NAND latch.

Delay Flip Flop / D Flip Flop:-

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a
NAND inverter connected between S and R inputs. It has only one input. The input data is
appearing at the output after some time. Due to this data delay between i/p and o/p, it is called
delay flip flop. S and R will be the complements of each other due to NAND inverter. Hence S =
R = 0 or S = R = 1, these input condition will never appear. This problem is avoid by SR = 00
and SR = 1 conditions.

Block Diagram:-

75
Circuit Diagram:-

Truth Table:-

Operations:-

S.N. Condition Operation

1 E=0 Latch is disabled. Hence no change in output.
If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the
2 E = 1 and D = 0 present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is the reset
condition.
If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and Qn+1
3 E = 1 and D = 1
= 1 and Qn+1 bar = 0 irrespective of the present state.

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J-K Flip Flop:-

This simple JK flip Flop is the most widely used of all the flip-flop designs and
is considered to be a universal flip-flop circuit. The two inputs labelled “J” and “K” are not
shortened abbreviated letters of other words, such as “S” for Set and “R” for Reset, but are
themselves autonomous letters chosen by its inventor Jack Kilby to distinguish the flip-flop
design from other types.

The sequential operation of the JK flip flop is exactly the same as for the
previous SR flip-flop with the same “Set” and “Reset” inputs. The difference this time is that the
“JK flip flop” has no invalid or forbidden input states of the SR Latch even when S and R are
both at logic “1”.

The JK flip flop is basically a gated SR flip-flop with the addition of a clock
input circuitry that prevents the illegal or invalid output condition that can occur when both
inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK flip-flop
has four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The
symbol for a JK flip flop is similar to that of an SR Bistable Latch as seen in the previous tutorial
except for the addition of a clock input.

T edge trigered Flip-Flop:-

The essential characteristic of a flip-flop is that it changes its output

state in response to a positive or negative transition on the control signal. But there is more to a
flip-flop than this: we also have to define the input-to-output relationship. This is why there are
different types of flip-flops; they are all sensitive to clock edges, but they perform different
actions in response to the input states. The “T” in “T flip-flop” stands for “toggle.” When you
toggle a light switch, you are changing from one state (on or off) to the other state (off or on).
This is equivalent to what happens when you provide a logic-high input to a T flip-flop: if the
output is currently logic high, it changes to logic low; if it’s currently logic low, it changes to
logic high. A logic-low input causes the T flip-flop to maintain its current output state.

77
Here is the same information in truth-table form

JK Master Slave Flip Flop:-

Master slave JK FF is a cascade of two S-R FF with feedback

from the output of second to input of first. Master is a positive level triggered. But due to the
presence of the inverter in the clock line, the slave will respond to the negative level. Hence
when the clock = 1 (positive level) the master is active and the slave is inactive. Whereas when
clock = 0 (low level) the slave is active and master is inactive.

Circuit Diagram:-

78
Truth Table:-

Operations:-

S.N. Condition Operation

When clock = 0, the slave becomes active and master is
inactive. But since the S and R inputs have not changed, the
1 J = K = 0 (No change)
slave outputs will also remain unchanged. Therefore outputs
will not change if J = K =0.
Clock = 1 − Master active, slave inactive. Therefore outputs of
the master become Q1 = 0 and Q1 bar = 1. That means S = 0 and
R =1.

Clock = 0 − Slave active, master inactive. Therefore outputs of

the slave become Q = 0 and Q bar = 1.
2 J = 0 and K = 1 (Reset)
Again clock = 1 − Master active, slave inactive. Therefore even
with the changed outputs Q = 0 and Q bar = 1 fed back to
master, its output will be Q1 = 0 and Q1 bar = 1. That means S
= 0 and R = 1.

Hence with clock = 0 and slave becoming active the outputs of

slave will remain Q = 0 and Q bar = 1. Thus we get a stable

79
 output from the Master slave.
Clock = 1 − Master active, slave inactive. Therefore outputs of
the master become Q1 = 1 and Q1 bar = 0. That means S = 1 and
R =0.

3 J = 1 and K = 0 (Set) Clock = 0 − Slave active, master inactive. Therefore outputs of

the slave become Q = 1 and Q bar = 0.

Again clock = 1 − then it can be shown that the outputs of the

slave are stabilized to Q = 1 and Q bar = 0.
Clock = 1 − Master active, slave inactive. Outputs of master will
toggle. So S and R also will be inverted.

Clock = 0 − Slave active, master inactive. Outputs of slave will

toggle.
4 J = K = 1 (Toggle)
These changed output are returned back to the master inputs.
But since clock = 0, the master is still inactive. So it does not
respond to these changed outputs. This avoids the multiple
toggling which leads to the race around condition. The master
slave flip flop will avoid the race around condition.

80
Unit - V

81
Shift Register:-

The Shift Register is another type of sequential logic circuit that can be
used for the storage or the transfer of binary data. This sequential device loads the data present
on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name
Shift Register.

A shift register basically consists of several single bit “D-Type Data Latches”, one for each data
bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so
that the output from one data latch becomes the input of the next latch and so on.

Data bits may be fed in or out of a shift register serially, that is one after the other from either the
left or the right direction, or all together at the same time in a parallel configuration.

The number of individual data latches required to make up a single Shift Register device is
usually determined by the number of bits to be stored with the most common being 8-bits (one
byte) wide constructed from eight individual data latches.

Shift Registers are used for data storage or for the movement of data and are therefore commonly
used inside calculators or computers to store data such as two binary numbers before they are
added together, or to convert the data from either a serial to parallel or parallel to serial format.
The individual data latches that make up a single shift register are all driven by a common clock
( Clk ) signal making them synchronous devices.

Shift register IC’s are generally provided with a clear or reset connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register being:

 Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time,
with the stored data being available at the output in parallel form.
 Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the
register, one bit at a time in either a left or right direction under clock control.
 Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.
 Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.

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Serial In − Serial Out (SISO) Shift Register:-

The shift register, which allows serial input and produces serial output is
known as Serial In – Serial Out (SISO) shift register. The block diagram of 3-bit SISO shift
register is shown in the following figure.

This block diagram consists of three D flip-flops, which are cascaded. That means,
output of one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are
synchronous with each other since, the same clock signal is applied to each one. In this shift
register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is
also called as serial input. For every positive edge triggering of clock signal, the data shifts from
one stage to the next. So, we can receive the bits serially from the output of right most D flip-
flop. Hence, this output is also called as serial output.

Serial In - Parallel Out (SIPO) Shift Register:-

The shift register, which allows serial input and produces parallel output is
known as Serial In – Parallel Out (SIPO) shift register. The block diagram of 3-bit SIPO shift
register is shown in the following figure.

83
 This circuit consists of three D flip-flops, which are cascaded. That means, output of
one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are synchronous
with each other since, the same clock signal is applied to each one.In this shift register, we can
send the bits serially from the input of left most D flip-flop. Hence, this input is also called as
serial input. For every positive edge triggering of clock signal, the data shifts from one stage to
the next. In this case, we can access the outputs of each D flip-flop in parallel. So, we will get
parallel outputs from this shift register.

Parallel In − Serial Out (PISO) Shift Register:-

The shift register, which allows parallel input and produces serial output is
known as Parallel In − Serial Out (PISO) shift register. The block diagram of 3-bit PISO shift
register is shown in the following figure.

84
Parallel In - Parallel Out (PIPO) Shift Register:-

The shift register, which allows parallel input and produces parallel output is
known as Parallel In − Parallel Out (PIPO) shift register. The block diagram of 3-bit PIPO shift
register is shown in the following figure.

This circuit consists of three D flip-flops, which are cascaded. That means,
output of one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are
synchronous with each other since, the same clock signal is applied to each one. In this shift
register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. We
can apply the parallel inputs through preset or clear. These two are asynchronous inputs. That
means, the flip-flops produce the corresponding outputs, based on the values of asynchronous
inputs. In this case, the effect of outputs is independent of clock transition. So, we will get the
parallel outputs from each D flip-flop.

85
Bi-directional Shift Registers:-

A bidirectional, or reversible, shift register is one in which the data can be

shift either left or right. A four-bit bidirectional shift register using D flip-flops is shown below.

Here a set of NAND gates are configured as OR gates to select data inputs from the right or left
adjacent bistables, as selected by the LEFT/RIGHT control line.

Counters:-
Counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal. Counters are used
in digital electronics for counting purpose, they can count specific event happening in the circuit.
For example, in UP counter a counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on our design like any random
sequence 0,1,3,2… .They can also be designed with the help of flip flops.

Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter

86
Asynchronous Counter:-

In asynchronous counter we don’t use universal clock, only first flip flop is
driven by main clock and the clock input of rest of the following counters is driven by output of
previous flip flops. We can understand it by following diagram-

It is evident from timing diagram that Q0 is changing as soon as the rising

edge of clock pulse is encountered, Q1 is changing when rising edge of Q0 is encountered
(because Q0 is like clock pulse for second flip flop) and so on. In this way ripples are generated
through Q0,Q1,Q2,Q3 hence it is also called RIPPLE counter.

87
Synchronous Counter:-

Unlike the asynchronous counter, synchronous counter has one global

clock which drives each flip flop so output changes in parallel. The one advantage of
synchronous counter over asynchronous counter is, it can operate on higher frequency than
asynchronous counter as it does not have cumulative delay because of same clock is given to
each flip flop.

88
 From circuit diagram we see that Q0 bit gives response to each falling edge
of clock while Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on
Q2,Q1 and Q0.

Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows −

 Up counters
 Down counters
 Up/Down counters

UP/DOWN Counter:-

Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode
control (M) input is also provided to select either up or down mode. A combinational circuit is
required to be designed and used between each pair of flip-flop in order to achieve the up/down
operation.

 Type of up/down counters

 UP/DOWN ripple counters
 UP/DOWN synchronous counter

UP/DOWN Ripple Counters

In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops or
JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every
other FF is obtained from (Q = Q bar) output of the previous FF.

 UP counting mode (M=0) − The Q output of the preceding FF is connected to the clock
of the next stage if up counting is to be achieved. For this mode, the mode select input M
is at logic 0 (M=0).
 DOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF is
connected to the next FF. This will operate the counter in the counting mode.

89
Decade Counters:-

A decade counter counts ten different states and then reset to its initial states. A simple
decade counter will count from 0 to 9 but we can also make the decade counters which can go
through any ten states between 0 to 15(for 4 bit counter).

We see from circuit diagram that we have used nand gate for Q3 and Q1 and feeding this to clear
input line because binary representation of 10 is-1010

And we see Q3 and Q1 are 1 here, if we give NAND of these two bits to clear input then counter
will be clear at 10 and again start from beginning.

Important point: Number of flip flops used in counter are always greater than equal to (log2 n)
where n=number of states in counter.

90