TEKNIK DIGITAL (A)

(TI 2104)

Materi Kuliah ke
ke--7

FLIP--FLOPS
FLIP

Basic RS Flip-Flop (NAND)

1

0 S (set) S R Q Q’
1 Q
1 0 0 1
1 1 0 1 (after S = 1, R = 0)
1 0 1 1 0
1 1 1 0 (after S = 0, R = 1)
0 R (reset) 2 Q’
’ 0 0 1 1
(a) Logic diagram (b) Truth table

A flip-flop holds 1 "bit".

"Bit" ::= "binary digit."

1
 Clocked D Flip-Flop
D
3
1 Q

CP

2 Q’
4
5

The present state is held when CP is low.

Clock Pulse Definition

Positive Pulse Negative Pulse

Positive Negative Negative Positive

Edge Edge Edge Edge

Edges can also be referred to as leading and trailing.

2
 Master-Slave Flip-Flop

Y
S S S Q
Master Slave
Y’
R R R Q’

CP

MASTER-SLAVE FLIP-FLOP

Flip-Flop on RT54SX-A
(Not hardened)

Master Slave

3
 RT54SX-A SEU Performance
10 -6
October, 2000
Flip-Flop String
Flip-Flop String w/ Buffers
Cross-section (cm /flip-flop)

10 -7
2

Notes:

1. S/N LAN4001
10 -8 2. Ions = 210 MeV Cl-35, 284 MeV Br-81, 345 MeV I-127
7 2
3. Fluence ~ 10 ions/cm
4. Bias = 4.5, 2.25 VDC
5. Checkerboard pattern
6. Frequency = 1 MHz
7. 200 flip-flops / string
8. Regular CLK Buffer
10 -9
0 10 20 30 40 50 60
LET (MeV-cm2/mg)

RT54SX-S Latch
(SEU Hardened)
AFB

D B ANQ A Y A A Y A
Y A A
A S B B Y

C
C

BFB

B BNQ A Y B A Y A A
Y B
A S B B Y A Y

C
C

CFB

B CNQ A Y C A Y A A
Y C
A S B B Y

C C
G

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 Flip-Flop Timing: RT54SX-S

Worst-case Military Conditions, V CCA=2.3, V CCI=3.0V, T J=125°C

-1 Speed Grade
Min Max Units
t RCO Sequential Clock-to-Q 1.0 ns
t CLR Asynchronous Clear-to-Q 0.9 ns
t PRESET Asynchronous Preset-to-Q 1.0 ns
t SUD Flip-Flop Data Input Set-Up 0.6 ns
t HD Flip-Flop Data Input Hold 0.0 ns
t WASYN Asynchronous Pulse Width 1.8 ns

Metastability - Introduction
• Can occur if the setup, hold time, or clock pulse width of a
flip- flop is not met.
• A problem for asynchronous systems or events.
• Can be a problem in synchronous systems.
• Three possible symptoms:
– Increased CLK -> Q delay.
– Output a non-logic level
– Output switching and then returning to its original state.
• Theoretically, the amount of time a device stays in the
metastable state may be infinite.
• Many designers are not aware of metastability.

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 Metastability
• In practical circuits, there is sufficient noise to move the
device output of the metastable state and into one of the
two legal ones. This time can not be bound. It is
statistical.
• Factors that affect a flip-flop's metastable "performance"
include the circuit design and the process the device is
fabricated on.
• The resolution time is not linear with increased circuit time
and the MTBF is an exponential function of the available
slack time.

Metastability - Calculation
• MTBF = eK2*t / ( K1 x FCLK x FDATA)

t is the slack time available for settling

K1 and K2 are constants that are characteristic of the flip-flop

Fclock and Fdata are the frequency of the synchronizing clock and
asynchronous data.
• Software is available to automate the calculations with
built- in tables of parameters.
• Not all manufacturers provide data.

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 Metastability - Sample Data
Sample Metastable Time Data
CX2001 Technology
50 MHz clock, 10 MHz data rate
25

20

15
log10 (MTBF (years))

10

-5

-10
Note: Each flip-flop has its own K1, K2 parameters.

-15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Slack Time (ns)

Synchronizer (Bad Circuit)

VCC

D Q D Q
DFC1B DF1

EVENT CLK
CLR
CLK

SYSRESET B AND 2A
Y
A

SYSCLK

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 Metastable State:
Possible Output from a Flip-flop

CLK

Metastable

Metastable State:
Possible Outputs from a Flip-flop
CLK

Q Correct Output

8
 9
D Q Q[3:0]
DATA [ 3 : 0 ]
DF1
CLOCK CLK

4-Bit Parallel Register

Parallel Registers

D Q
DF1
CLK
D Q
DF1
CLK
D Q
DF1
CLK
 4-Bit Register With Enable

DATA [ 3 : 0 ]
CLOCK
D

D
CLK

CLK

CLK

CLK
DF1

DF1

DF1

DF1
Q

Q
Q[3:0]

Register Files (Simplified)

Register 2
Q
D
Register 1
CLK

Address - log2(num registers)

D and Q are both sets of lines, with the number of lines

equal to the width of each register. There are often multiple
address ports, as well as additional data ports.

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 Memory Devices

Magnetic
Core
Memory

Register

Decoder
(AND plane)

Sense wires serve as OR plane.

11
 Data
inputs
Semiconductor D0
Word 0

Memory BC BC BC

D1 Word 1
Address
inputs BC BC BC

Decoder D2 Word 2

(AND plane)
BC BC BC

Word3
D3

Memory BC BC BC
enable
Read/write

OR plane
Data
outputs

Rad-Hard PROM Architecture

A5 - A11 Row Decoders Memory Array

A0 - A4 Column Decoders Column Muxing

and
A12 - A14 Section Select Sense Amps

CE
OE Control Logic I/O Buffers
VPP*

DQ0 - 7
No latches in this architecture

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 W28C64 EEPROM
Simplified Block Diagram
E2
Row Row Memory
Address Address Array
A 6-12
Latches Decoder

Column Column 64 Byte

A 0-5 Address Address Page
Latches Decoder Buffer

CE* Edge
Detect &
WE* Timer
Latches

Latch Enable I/O Buffer/

Data Polling
OE* Control Control
Latch Logic

PE RSTB CLK VW I/O 0-7

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