PAE2248 System-on-Chip Design

UI-SoC Design Issues

L1: Architecture of the SoC

Presented By
Dr. V. Vaithianathan
Associate Professor, ECE Dept
 Lesson Plan
Sl. No. of
Lecture
No Hours
L1 Architecture of the SoC 1
L2 Design Issues of SoC 1

Hardware-Software Codesign - Codesign Flow &

L3 2
Codesign Tools

L4 Core Libraries, EDA tools, Web Pointers 1

L5 SoC Design Flow 1
L6 General Guidelines for Design Reuse 1
L7 On Chip Buses – Clock Distribution 1
L8 Physical Design and Deliverable Models 1
 Lecture 1
• Architecture of the SoC
– Introduction
– Architecture of Present-Day SoC
 Session Objectives
• To understand basic of SoC
• To learn the Architecture of Present-Day
SoC
 Session Outcomes
• At the end of this lecture, the students will
be able to know about
– Basics of SoC
– Architecture of Present-Day SoC
 Introduction
• In the mid-1990s, ASIC technology evolved from a
chip-set philosophy to an embedded-cores-based
system-on-a-chip (SoC) concept.
• In simple terms, let us define an SoC as an IC,
designed by stitching together multiple stand-alone
VLSI designs to provide full functionality for an
application.
• This definition of SoC clearly emphasizes predesigned models
of complex functions known as cores (terms such as
intellectual property block, virtual components, and macros
are also used) that serve a variety of applications.
• In SoC, an ASIC vendor may use a library of cores
designed in-house as well as some cores from
fabless/chipless design houses also known as
intellectual property (IP) companies.
 Introduction
• The scenario for SoC design today is primarily
characterized by three forms:
1. ASIC vendor design: This refers to the design in which all
the components in the chip are designed as well as
fabricated by an ASIC vendor.
2. Integrated design: This refers to a design by an ASIC
vendor in which all components are not designed by that
vendor. It implies the use of one or multiple cores obtained
from some other source such as a core/IP vendor or a
foundry. The fabrication of these designs is done by either
the ASIC vendor or a foundry company.
3. Desktop design: This refers to the design by a fabless
company that uses cores which for the most part have been
obtained from other sources such as IP companies, EDA
companies, design services companies, or a foundry. In
most cases, an independent foundry company fabricates
these designs.
 Introduction
• Because of the increasing integration of cores and the
use of embedded software in SoC, the design
complexity of SoC has increased dramatically and is
expected to increase continuously at a very fast rate.
• Conceptually this trend is shown in figure 1.1

Figure 1.1 Trend toward increasing design complexity due to integration

 Introduction
• Every three years, silicon complexity quadruples
following Moore’s law.
• This complexity accounts for the increasing size of cores and
the shrinking geometry that makes it necessary to include
more and more parameters in the design criterion.
• A few years ago it was sufficient to consider functionality,
delay, power, and testability.
• Today, it is becoming increasingly important to also consider
signal integrity, electromigration, packaging effects,
electromagnetic coupling, and RF analysis.
• In addition to the increasing silicon IP complexity, the
embedded software content has increased at a rate
much higher than that of Moore’s law.
• Hence, on the same scale, overall system complexity
has a much steeper slope than that of silicon
complexity.
 Present-Day SoC: Architecture
• In all SoC designs, predesigned cores are the
essential components.
• A system chip may contain combinations of cores for
on-chip functions such as microprocessors, large
memory arrays, audio and video controllers, modems,
Internet tuner, 2D and 3D graphics controllers, DSP
functions, and so on.
• These cores are generally available in either
synthesizable high-level description language (HDL)
form such as in Verilog/VHDL, or optimized transistor-
level layout such as GDSII.
• The flexibility in the use of cores also depends on the
form in which they are available.
 Present-Day SoC: Architecture
• The soft, firm, and hard cores are defined as follows.
• Soft cores: These are reusable blocks in the form of a
synthesizable RTL description or a netlist of generic library
elements. This implies that the user of soft core (macro) is
responsible for the actual implementation and layout.
• Firm cores: These are reusable blocks that have been
structurally and topologically optimized for performance and
area through floorplanning and placement, perhaps using a
range of process technologies. These exist as synthesized
code or as a netlist of generic library elements.
• Hard cores: These are reusable blocks that have been
optimized for performance, power, and size, and mapped to a
specific process technology. These exist as a fully placed and
routed netlist and as a fixed layout such as in GDSII format.
• The trade-off parameters among hard, firm, and soft
cores are reusability, flexibility, portability, optimized
performance, cost and time-to-market.
 Present-Day SoC: Architecture
• Qualitatively, this trade-off is shown in figure 1.2.

Figure 1.2 Trade-offs among soft, firm, and hard cores.

 Present-Day SoC: Architecture
• Examples of core-based SoC
• High-end microprocessors, media processors, GPS
controllers, single-chip cellular phones, GSM phones, smart
pager ASICs, and even PC-on-a-chip.
• Some people do not consider microprocessors within the
definition of SoC. However, the architecture and design
complexity of microprocessors such as the Alpha 21264,
PowerPC, and Pentium III is no less than that of SoC by any
measurement.
• To understand the general architecture of SoC, figure
1.3 shows an example of high-end microprocessors,
and figure 1.4 illustrates two SoC designs.
• Both figures show the nature of components used in
today’s SoC.
• Based on these examples, a generalized structure of
SoC can be shown as given in figure 1.5.
Present-Day SoC: Architecture

Figure 1.3 Intel’s i860 microprocessor.

Present-Day SoC: Architecture

Figure 1.4 Examples of today’s SoC

(a) Codec sign processor. (b) MPEG2 video coding/decoding.
 Present-Day SoC: Architecture

Figure 1.5 General architecture of today’s embedded core-based system-on-

a-chip
 Present-Day SoC: Architecture
• Figures 1.3 to 1.5 illustrate examples of common
components in today’s SoC:
• Multiple SRAM/DRAM, CAM, ROM, and flash memory blocks
• On-chip microprocessor/microcontroller;
• PLL; sigma/delta and ADC/DAC functional blocks; function-
specific cores such as DSP;
• 2D/3D graphics
• Interface cores such as PCI, USB, and UART.
 Review Questions
1. What is meant by system on chip?
2. What is SoC and its types?
3. What is System on Chip vs CPU?
4. What is SoC in chips?
5. What are the components in SoC?
6. What is SoC and its types?
7. What is an example of the system on a chip?
8. What is a system on chip device?
 Session Summary
• In this lecture, we have discussed about
– Basics of SoC
– Architecture of Present-Day SoC
 Text Books & References
1. Rochit Rajsuman, “System-on-a-chip: Design and
Test”, Advantest America R & D Centre, 2000.
2. Hubert Kaeslin, “Digital Integrated Circuit Design: From
VLSI Architectures to CMOS Fabrication”, Cambridge
University Press, 2008.
3. B. Al Hashimi, “System on chip-Next generation
electronics”, The IET, 2006.
4. P Mishra and N Dutt, “Processor Description Languages”,
Morgan Kaufmann, 2008.
5. Michael J. Flynn and Wayne Luk, “Computer System
Design: System-on-Chip”, Wiley, 2011.
Thank You