Module 3 – 1st Part

PROGRAMMABLE DIGITAL SIGNAL

PROCESSORS
Presented by:
Bhargavi K Rao
Assistant Professor
Dept. of ECE
TEXT BOOK:
1. “Digital Signal Processing”, Avatar Singh and S. Srinivasan,
Thomson Learning, 2004.

REFERENCE BOOKS:
1.Digital Signal Processing: A practical approach, Ifeachor
E. C., Jervis B. W Pearson- Education, PHI, 2002.
2.“Digital Signal Processors”, B Venkataramani and M Bhaskar
TMH, 2nd, 2010.
3. “Architectures for Digital Signal Processing”, Peter Pirsch
John Weily, 2008.
 Learning objectives:
 To understand the architecture and data addressing modes of
TMS320C54xx processors.
 Memory space, program control, instructions and programming of
TMS320C54xx processors.
 On-chip peripherals and interrupts of TMS320C54xx processors.
 Pipeline operation of TMS320C54xx processors.
 Lesson plan:
Sl No Topic Date Date Hours
planned engaged

1. Introduction 1st

2. Commercial digital Signal-processing Devices 2nd

3. Data Addressing Modes of TMS32OC54xx 3rd

4. Memory Space of TMS32OC54xx Processors 4th

5. Program Control 5th

 Content:
 Introduction
 Commercial digital Signal-processing Devices
 Data Addressing Modes of TMS32OC54xx
 Memory Space of TMS32OC54xx Processors
 Program Control
3.1 Introduction
 Leading manufacturers of integrated circuits such as Texas
Instruments (TI), Analog devices & Motorola, manufacture the
digital signal processor (DSP) chips.
 These manufacturers have developed a range of DSP chips with
varied complexity.
 The TMS320 family consists of two types of single chips DSPs: 16-bit
fixed point & 32-bit floating-point.
 These DSPs possess the operational flexibility of high-speed
controllers and the numerical capability of array processors
 3.3. The architecture of TMS320C54xx digital signal
processors

 TMS320C54xx processors retain in the basic Harvard architecture of

their predecessor, TMS320C25, but have several additional features,
which improve their performance over it.
 Figure 3.1 shows a functional block diagram of TMS320C54xx
processors.
 They have one program and three data memory spaces with separate
buses, which provide simultaneous accesses to program instruction and
two data operands and enables writing of result at the same time.
 Part of the memory is implemented on-chip and consists of
combinations of ROM, dual-access RAM, and single-access RAM.
Transfers between the memory spaces are also possible.
 The central processing unit (CPU) of TMS320C54xx processors consists of
a 40- bit arithmetic logic unit (ALU), two 40-bit accumulators, a
barrel shifter, a 17x17 multiplier, a 40-bit adder, data address
generation logic (DAGEN) with its own arithmetic unit, and program
address generation logic (PAGEN).
 These major functional units are supported by a number of registers and
logic in the architecture.
 A powerful instruction set with a hardware-supported, single-instruction
repeat and block repeat operations, block memory move instructions,
instructions that pack two or three simultaneous reads, and arithmetic
instructions with parallel store and load make these devices very efficient
for running high-speed DSP algorithms.
 Several peripherals, such as a clock generator, a hardware timer, a wait
state generator, parallel I/O ports, and serial I/O ports, are also
provided on-chip.
 These peripherals make it convenient to interface the signal processors to
the outside world.
3.3.1 Bus Structure
 The performance of a processor gets enhanced with the provision
of multiple buses to provide simultaneous access to various parts of
memory or peripherals.
 The 54xx architecture is built around four pairs of 16-bit buses
with each pair consisting of an address bus and a data bus. As shown
in Figure 3.1, these are
 The program bus pair (PAB, PB); which carries the instruction
code from the program memory.
 Three data bus pairs (CAB, CB; DAB, DB; and EAB, EB); which
interconnects the various units within the CPU. In Addition the pair
CAB, CB and DAB, DB are used to read from the data memory, while
 The pair EAB, EB; carries the data to be written to the memory. The
„54xx can generate up to two data-memory addresses per cycle using
the two auxiliary register arithmetic unit (ARAU0 and ARAU1) in the
DAGEN block. This enables accessing two operands simultaneously.
3.3.2 Central Processing Unit (CPU):

 The „54xx CPU is common to all the „54xx devices. The ‟54xx
CPU contains a 40-bit arithmetic logic unit (ALU); two 40-bit
accumulators (A and B); a barrel shifter; a 17 x 17-bit multiplier; a
40-bit adder; a compare, select and store unit (CSSU); an exponent
encoder(EXP); a data address generation unit (DAGEN); and a
program address generation unit (PAGEN).
 Figure 3.2 shows the Functional diagram of the central processing
unit of the TMS320C54xx processors.
 The ALU performs 2‟s complement arithmetic operations and bit-
level Boolean operations on 16, 32, and 40-bit words.
 It can also function as two separate 16-bit ALUs and perform two
16-bit operations simultaneously.
 Figure 3.2 show the functional diagram of the ALU of the
TMS320C54xx family of devices.
 Accumulators A and B; store the output from the ALU or the
multiplier/adder block and provide a second input to the ALU. Each
accumulators is divided into three parts: guards bits (bits 39-32),
high-order word (bits-31-16), and low-order word (bits 15-0),
which can be stored and retrieved individually.
 Each accumulator is memory-mapped and partitioned. It can be
configured as the destination registers. The guard bits are used as a
head margin for computations.
 ALU supports both saturation logic and sign extension. Saturation
Logic prevents the result from underflow or overflow condition by
keeping the result at maximum or minimum.
 ALU also contains many status flags,
 OVM(overflow mode bit): this determines what is loaded into the
accumulator when an overflow occurs.
 If OVM=0, the overflow result is placed in the accumulator without
any modification.
 If OVM=1, accumulator is loaded with, most positive value & least
negative value, depending on the direction of overflow.
 TC(test and control flag): this flag is used to indicate the result of any
bit test instruction.
 C(carry flag): it is used to set or reset after an arithmetic operation.
After the addition if there is a carry then C bit is set to „1‟
After the subtraction if there is a borrow then it is set to „0‟
 OVA (overflow flag of accumulator A):
OVA=0, if there is no overflow
OVA=1, if there is a overflow in accumulator A
 OVB (overflow flag of accumulator B):
OVB=0, if there is no overflow
OVB=1, if there is a overflow in accumulator B
 SXM(sign extension mode bit)
if SXM=0, sign extension is not done.
SXM=1, sign extension is done before being used by ALU.
 ZA/ZB: Determines whether the output is present in accumulator A
or B
Barrel shifter
Figure 3.3.Functional diagram of the barrel shifter
 Barrel shifter provides the capability to scale the data during an
operand read or write.
 No overhead is required to implement the shift needed for the
scaling operations.
 Scaling operation performs
 Pre scaling of the input data from the memory or from the
accumulator before ALU operation.
 Performing logical or arithmetic shift of the accumulator value.
 Normalizing the accumulator value.
 Post scaling of the accumulator before storing the accumulator value
into the memory.
 The‟54xx barrel shifter can produce a left shift of 0 to 31 bits or a
right shift of 0 to 16 bits on the input data.
 The shift requirements are defined in the shift count field of
instruction, the shift count field of status registers ST1, or in the
temporary register T.
 Figure 3.3 shows the functional diagram of the barrel
shifter of TMS320C54xx processors.
 The barrel shifter and the exponent encoder normalize the
values in an accumulator in a single cycle. The LSBs of the output
are filled with zeros, and the MSBs can be either zero filled or sign
extended, depending on the state of the sign-extension mode bit in
the status register ST1.
 An additional shift capability enables the processor to perform
numerical scaling, bit extraction, extended arithmetic, and overflow
prevention operations.
Multiplier/Adder Unit
 The kernel of the DSP device architecture is multiplier/adder unit.
The multiplier/adder unit of TMS320C54xx devices performs 17 x
17 2‟s complement multiplication with a 40-bit addition effectively in
a single instruction cycle.
 In addition to the multiplier and adder, the unit consists of control
logic for integer and fractional computations and a 16-bit temporary
storage register, T.
 Figure 3.4 show the functional diagram of the multiplier/adder unit
of TMS320C54xx processors.
 The compare, select, and store unit (CSSU) is a hardware unit
specifically incorporated to accelerate the add/compare/select
operation.
 This operation is essential to implement the Viterbi algorithm used in
many signal-processing applications.
 The exponent encoder unit supports the EXP instructions, which
stores in the T register the number of leading redundant bits of
the accumulator content.
 This information is useful while shifting the accumulator content for
the purpose of scaling.
3.3.3 Internal Memory and Memory-Mapped Registers:
 The amount and the types of memory of a processor have direct
relevance to the efficiency and performance obtainable in
implementations with the processors.
 The „54xx memory is organized into three individually selectable
spaces: program, data, and I/O spaces.
 All „54xx devices contain both RAM and ROM. RAM can be either
dual-access type (DARAM) or single-access type (SARAM).
 The on-chip RAM for these processors is organized in pages having
128 word locations on each page.
 The „54xx processors have a number of CPU registers to support
operand addressing and computations.
 The CPU registers and peripherals registers are all located on page 0
of the data memory.
 Figure 3.5(a) and (b) shows the internal CPU registers and peripheral
registers with their addresses. The processors mode status (PMST)
registers that is used to configure the processor. It is a memory-
mapped register located at address1Dh on page 0 of the RAM.
 A part of on-chip ROM may contain a boot loader and look-up tables
for function such as sine, cosine, µ - law, and A- law.
Figure 3.5(a) Internal memory-mapped registers of TMS320C54xx processors.
Figure 3.5(b).peripheral registers for the TMS320C54xx processors
Status registers (ST0,ST1):
 ST0: Contains the status flags (OVA, OVB, C, TC) produced by
arithmetic operations & bit manipulations.
 ST1: Contain the status of various conditions & modes. Bits of
ST0&ST1registers can be set or clear with the SSBX & RSBX
instructions.
 PMST: Contains memory-setup status & control information.
 Status register0 diagram:

 ARP: Auxiliary register pointer.

 TC: Test/control flag.
 C: Carry bit.
 OVA: Overflow flag for accumulator A.
 OVB: Overflow flag for accumulator B.
 DP: Data-memory page pointer.
 ARP: Auxiliary register pointer
This is 3 bit field selects the auxiliary register to be used in indirect single-
operand addressing. ARP must always be set to zero when the dsp is in
standard mode (CMPT=0)
 TC(test and control flag): This flag is used to indicate the result of any bit
test instruction.
 C(carry flag): it is used to set or reset after an arithmetic operation.
After the addition if there is a carry then C bit is set to „1‟
After the subtraction if there is a borrow then it is set to „0‟
 OVA (overflow flag of accumulator A):
OVA=0, if there is no overflow
OVA=1, if there is a overflow in accumulator A
 OVB (overflow flag of accumulator B):
OVB=0, if there is no overflow
OVB=1, if there is a overflow in accumulator B
 DP(Data memory page pointer): This 9 bit field is concatenated with the
seven LSBs of an instruction word to form a direct memory address of 16
bits for single data memory operand addressing.
 Status register1 diagram:

 BRAF: Block repeat active flag

BRAF=0, the block repeat is deactivated. BRAF=1, the block repeat
is activated.
 CPL: Compiler mode
CPL=0, the relative direct addressing mode using data page pointer
is selected. CPL=1,the relative direct addressing mode using stack
pointer is selected.
 XF status: XF indicates the status of the external flag(XF) pin,
which is a general-purpose output pin. The SSBX instruction can set
XF and the RSBX instruction can reset XF.
 HM: Hold mode, indicates whether the processor continues
internal execution when acknowledging an active HOLD signal:
HM=0, the processor continues execution from internal program
memory but places its external interface in the high-impedance
state.
HM=1, the processor halts internal execution.
 INTM: Interrupt mode, it globally masks or enables all interrupts.
INTM=0, all unmasked interrupts are enabled.
INTM=1 all masked interrupts are disabled.
 0: Always read as 0
 OVM: Overflow mode.
OVM=1,the destination accumulator is set either the most positive
value or the least negative value.
OVM=0, the overflowed result is in destination accumulator.
 SXM: Sign extension mode. Determines whether sign extension is
performed.
SXM=0, Sign extension is suppressed. SXM=1, Data is sign extended
 C16: Dual 16 bit/double-Precision arithmetic mode.
C16=0 ALU operates in double-Precision arithmetic mode. C16=1
ALU operates in dual 16-bit arithmetic mode.
 FRCT: Fractional mode.
FRCT=1, the multiplier output is left-shifted by 1 bit to compensate
an extra sign bit.
 CMPT: Compatibility mode. Determines compatibility mode for ARP
CMPT=0 ,ARP is not updated in the indirect addressing mode.
CMPT=1 , ARP is updated in the indirect addressing mode.
 ASM: Accumulator Shift Mode. 5 bit field, & specifies the Shift value
within -16 to 15 range and is coded as a 2s complement value.
Processor Mode Status Register (PMST):

 IPTR: Interrupt vector pointer, the 9 bit INTR field points to the 128-word
program page where the interrupt vectors reside.
 MP/MC: Microprocessor/Microcomputer mode, MP/MC=0, the on chip
ROM is enabled. MP/MC=1, the on chip ROM is not available.
 OVLY: RAM OVERLAY, OVLY enables on chip dual access data RAM
blocks to be mapped into program space.
OVLY=0, the on-chip RAM is addressable in data space but not in program
space.
OVLY=1, the on-chip RAM is mapped into data space and program space.
 AVIS: address visibility mode. It enables/disables the internal program
address to be visible at the address pins.
AVIS=0, the external address lines do not change with the internal program
address.
AVIS=1, this mode allows the internal program address to appear at the pins
of the ‟54X so that the internal program address can be traced.
 DROM: Data ROM, DROM enables on-chip ROM to be mapped into data
space.
DROM=0, a on chip ROM is not mapped into data space.
DROM=1, a portion of the on chip ROM is mapped into data space.
 CLKOFF: CLOCKOUT off. When the CLKOFF bit is 1, the output of
CLKOUT is disabled and remains at a high level
 SMUL: Saturation on multiplication.
SMUL=1, saturation of a multiplication result occurs before performing the
accumulation in a MAC instruction.
 SST: Saturation on store.
SST=1,saturation of the data from the accumulator is enabled before storing
in memory. The saturation is performed after the shift operation.
3.4 Data Addressing Modes of TMS320C54X Processors:
Data addressing modes provide various ways to access operands to execute
instructions and place results in the memory or the registers. The 54XX devices
offer seven basic addressing modes

1. Immediate addressing.

2. Absolute addressing.

3. Accumulator addressing.

4. Direct addressing.

5. Indirect addressing.

6. Memory mapped addressing

7. Stack addressing.
3.4.1 Immediate addressing:
 The instruction contains the specific value of the operand. The operand can
be short (3,5,8 or 9 bit in length) or long (16 bits in length). The
instruction syntax for short operands occupies one memory location and
long operand occupies two memory locations. This addressing modes can
be used to initialize registers and memory locations.
Example: LD #20, DP.
RPT #0FFFFh.

3.4.2 Absolute Addressing:

 The instruction contains a specified address in the operand.
1. Dmad addressing (data memory location): This uses specific value to
specify an address in data space. The syntax for dmad addressing uses a
symbol or a number to specify an address in data space.
MVDK Smem,dmad
MVDM dmad,MMR
2.Pmad addressing(program memory location):This uses
specific value to specify an address in program space. The syntax for
pmad addressing uses a symbol or a number to specify an address in
program space.
MVDP Smem, pmad
MVPD pmem, Smad
3. PA addressing(port address):This uses specific value to specify
an external I/O port address. The syntax for PA addressing uses a
symbol or a number to specify the port address.
PORTR PA, Smem,
4.*(lk) addressing(a location in the data space specified directly)
Example:
MVKP 1000h, *AR5 ; 1000 H *AR5 (dmad addressing)
MVPD 1000h, *AR7 ; 1000h *AR7 (pmad addressing)
PORTR 05h, *AR3 ; 05h *AR3(PA addressing)
LD *(1000h), A ; *(1000h) A(*(lk) addressing)
3.4.3 Accumulator Addressing:
 Accumulator content is used as address to transfer data between
Program and Data memory. Examples of instructions in this mode are
READA and WRITA. READA transfers a word from a program-
memory location specified by accumulator A to a data memory
location. WRITA transfers a word from a data memory location to a
program-memory location specified by accumulator A.
Ex: READA *AR2
 3.4.4. Direct addressing
 In the addressing mode, the 16 bit address of the data-memory
location is formed by combining the lower 7 bits of the data-memory
address contained in the instruction with a base address given by the
data-page pointer(DP) or the stack pointer(SP).
 A page of 128 locations can be accessed without changing the DP or
SP. Compiler mode bit (CPL) located in the ST1 register, is used to
select between two pointers used to generate the address.
 If CPL =0 selects DP and CPL = 1 selects SP.
 It should be remembered that when SP is used instead of DP, the
effective address is computed by adding the 7-bit offset to SP.
 Example:
LD #4, DP ; DP=4=upper 9 bits of address
ADD=0, B ; Lower 7 bits of the address
Figure3.7: Block diagram of the direct addressing mode for
TMS320C54xx Processors.
3.4.5 Indirect Addressing:
 Data space is accessed by address present in an auxiliary register.
 „54xx have eight 16 bit auxiliary register (AR0 – AR 7).
 Used to access memory location in fixed step size. AR0 register is
used for indexed and bit reverse addressing modes.
 Two auxiliary register arithmetic units (ARAU0 & ARAU1) are used
to modify the contents of the auxiliary registers and it perform
unsigned, 16 bit arithmetic operations.
 ARAUs are used to generate an address in the indirect addressing
mode using a single data-memory operand.
For single – operand addressing
MOD type of indirect addressing
ARF AR used for addressing
 An address can be modified before or after accessing the location or
can be left unchanged. Modification can be by incrementing or
decrementing the address by 1, adding a 16 bit offset, or indexing
with the value in AR0. Each of these modification may be carried out
either before or after accessing memory location.
Figure 3.8 Block diagram of the indirect addressing mode for TMS320C54xx Processors
 Operand syntax Function

*Arx Addr ARx;

*ARx - Addr = ARx ; ARx = ARx -1

*ARx + Addr = ARx; ARx = ARx +1

*+ARx Addr = ARx+1; ARx = ARx +1

*ARx - 0B Addr = ARx ; ARx = B(ARx – AR0)

*ARx - 0 Addr = Arx ; ARx = ARx – AR0

*ARx + 0 Addr = Arx ; ARx = ARx +AR0

*ARx + 0B Addr = ARx ; ARx = B(ARx + AR0)

*ARx - % Addr = ARx ; ARx = circ(ARx – 1)

Table 3.2 Indirect addressing options with a single data –memory operand.
Operand syntax Function

*ARx + % addr ARx ; Arx circ(ARx +1)

*ARx – 0% addr ARx ; ARx circ(ARx – AR0)

*ARx + 0% addr ARx ; ARx circ(ARx +AR0)

*(lk) addr lk

*ARx (lk) aadr ARx+lk

*+ARx(lk) Arx ARx+lk, addr ARx

*+ARx(lk)% Arx circ (ARx+lk), addr ARx

Example Problem
 1. Assuming the current content of AR3 to be 200h, what will be its
contents after each of the following TMS320C54xx addressing
modes is used? Assume that the contents of AR0 are 20h.
a. *AR3+0
b. *AR3-0
c. *AR3+
d. *AR3
e. *AR3
f. *+AR3(40h)
g. *+AR3(-40h)
 Solution:
a. AR3 AR3 + AR0;
AR3 = 200h + 20h = 220h
b. AR3 AR3 - AR0;
AR3 = 200h - 20h = 1E0h
c. AR3 AR3 + 1;
AR3 = 200h + 1 = 201h
d. AR3 AR3 - 1;
AR3 = 200h - 1 = 1FFh
e. AR3 is not modified.
AR3 = 200h
f. AR3 AR3 + 40h;
AR3 = 200 + 40h = 240h
g. AR3 AR3 - 40h;
AR3 = 200 - 40h = 1C0h
Circular Addressing:
 Used in convolution, correlation and FIR filters, require the
implementation of a circular buffer memory.
 A circular buffer is a sliding window contains most recent data.
 Circular buffer of size R must start on a N-bit boundary, where 2N >
R.
 The circular buffer size register (BK): specifies the size of circular
buffer.
 Effective base address (EFB): By zeroing the N LSBs of a user
selected AR (ARx).
 End of buffer address (EOB) : By repalcing the N LSBs of ARx with
the N LSBs of BK.
If 0 ≤ index + step < BK ; index = index +step;
else if index + step ≥ BK ; index = index + step - BK;
else if index + step < 0; index + step + BK
Fig3.9 Block diagram of the circular addressing mode for TMS320C54xx Processors.
Fig3.10 circular addressing mode implementation for TMS320C54xx Processors.
 Bit-Reversed Addressing:
 Used for FFT algorithms.
 AR0 specifies one half of the size of the FFT.
 The value of AR0 = 2N-1: N = integer FFT size = 2N
 AR0 + AR (selected register) = bit reverse addressing.
 The carry bit propagating from left to right.
 Dual-Operand Addressing:
 Dual data-memory operand addressing is used for instruction that
simultaneously perform two reads (32-bit read) or a single read (16-bit
read) and a parallel store (16-bit store) indicated by two vertical bars, II.
 These instructions access operands using indirect addressing mode.
 If in an instruction with a parallel store the source operand the
destination operand point to the same location, the source is read before
writing to the destination.
 Only 2 bits are available in the instruction code for selecting each
auxiliary register in this mode.
 Thus, just four of the auxiliary registers, AR2-AR5, can be used, The
ARAUs together with these registers, provide capability to access two
operands in a single cycle.
 Figure 3.11 shows how an address is generated using dual data-memory
operand addressing.
Table 3.3.Function of the different field in dual data memory operand addressing

Name Function

Opcode This field contains the operation code for the instruction

Xmod Defined the type of indirect addressing mode used for accessing the
Xmem operand
XAR Xmem AR selection field defines the AR that contains the address of Xmem

Ymod Defies the type of inderect addressing mode used for accessing the
Ymem operand

Yar Ymem AR selection field defines the AR that contains the address of Ymem
Figure 3.11 Block diagram of the Indirect addressing options with a dual data –memory
operand.
3.4.6. Memory-Mapped Register Addressing:
 Used to modify the memory-mapped registers without affecting the current data- page
pointer (DP) or stack-pointer (SP)
– Overhead for writing to a register is minimal
– Works for direct and indirect addressing
– Scratch pad RAM located on data PAGE0 can be modified
• STM #x, DIRECT
• STM #tbl, AR1

Figure 3.12.16 bit memory mapped register address generation.

3.4.7 Stack Addressing:
 Used to automatically store the program counter during interrupts and
subroutines.
 Can be used to store additional items of context or to pass data values.
 Uses a 16-bit memory-mapped register, the stack pointer (SP).
 PSHD X2

Figure 3.13. Values of stack &SP before and after operation.

2. Assume that the register AR3 with contents 1020h is selected as the
pointer for the circular buffer. Let BK = 40h to specify the
circular buffer size as 40h.Determine the start and the end
addresses fort the buffer. What will be the contents of register AR3
after the execution to the instruction LD*AR3 + 0%, A, if the
contents of register AR0 are 0025h?

 Solution:
 AR3 = 1020h means that currently it points to location 1020h.
Masking the lower 6 bits zeros gives the start address of the buffer as
1000h. Replacing the same bits with the BK gives the end address as
1040h.
 The Instruction LD*AR3 + 0%, A modifies AR3 by adding AR0
to it and applying the circular modification. It yields
 AR3 = circ(1020h+0025h) = circ(1045h) = 1045h - 40h = 1005h.
 Thus the location 1005h is the one pointed to by AR3.

3. Assuming the current contents of AR3 to be 200h, what will be its

contents after each of the following TMS320C54xx addressing
modes is used? Assume that the contents of AR0 are 20h
a. *AR3 + 0B
b. *AR3 – 0B
 Solution:
a. AR3 AR3 + AR0 with reverse carry propagation;
AR3 = 200h + 20h (with reverse carry propagation)=220h.
b. AR3 AR3 - AR0 with reverse carry propagation;
AR3 = 200h - 20h (with reverse carry propagation) = 23Fh.

 3.5. Memory Space of TMS320C54xx Processors

 A total of 128k words extendable up to 8192k words.
 Total memory includes RAM, ROM, EPROM, EEPROM or Memory
mapped peripherals.
 Data memory: To store data required to run programs & for external
memory mapped registers.
 Size 64k words

 Program memory: To store program instructions &tables used in the execution of

programs.
 Organized into 128 pages, each of 64k word size
3.6. Program Control
 It contains program counter (PC), the program counter related H/W,
hard stack, repeat counters &status registers.
 PC addresses memory in several ways namely:
 Branch: The PC is loaded with the immediate value following the
branch instruction
 Subroutine call: The PC is loaded with the immediate value
following the call instruction
 Interrupt: The PC is loaded with the address of the appropriate
interrupt vector.
 Instructions such as BACC, CALA, etc ;The PC is loaded with the
contents of the accumulator low word
 End of a block repeat loop: The PC is loaded with the contents of the
block repeat program address start register.
 Return: The PC is loaded from the top of the stack.
 Questions
1. Compare architectural features of TMS320C25 and DSP6000 fixed point
digital signal processors.
(Dec.09-Jan.10, 6m)
2.Write an explanatory note on direct addressing mode of TMS320C54XX
processors. Give example. (Dec.09-Jan.10, 6m)
3.Describe the operation of the following instructions of TMS320C54XX
processors.
i) MPY *AR2-,*AR4+0B (ii) MAC *ar5+,#1234h,A
(iii)STHA,1,*AR (iv)SSBXSXM (Dec.09-Jan.10, 8m)
4. With a block diagram explain the indirect addressing mode of
TMS320C54XX processor using dual data memory operand. (June.12, 6m)
5. What is the function of an address generation unit explain with the help of
block diagram. (Dec.12, 6m)
6. Why circular buffers are required in DSP processor? How they are
implemented? (Dec.12, 2m)
7. Explain the direct addressing mode of the TMS320C54XX processor with the
help of a block diagram. (Dec.12, 2m)
8. Describe the multiplier/adder unit of TMS320c54xx processor with a
neat block diagram.(May/June2010, 6m)
9. Describe any four data addressing modes of TMS320c54xx
processor(May/June2010, 8m)
10. Assume that the current content of AR3 is 400h, what will be its
contents after each of the following. Assume that the content of AR0 is
40h. (May/June2010, 8m).
11. Explain PMST register. (May/June2011, 8m)
12. With an example each, explain immediate, absolute, and
direct addressing mode.(May/June2011, 12m)
13. Explain the functioning of barrel shifter in TMS320C54XX processor.
(June.12, 6m)
14. Explain sequential and other types of program control(June.11, 7m)
15. With an example each, explain immediate, absolute, and direct
addressing mode.
16. Explain the functioning of barrel shifter in TMS320C54XX processor.
17. Explain sequential and other types of program control
18. Assume that the current content of AR3 is 400h, what will be its
contents after each of the following. Assume that the content of AR0 is
40h.
19. Explain PMST register.
20. Compare architectural features of TMS320C25 and DSP6000 fixed
point digital signal processors
 Module 3 – 2nd Part
Instruction and programming

Presented by:
Bhargavi K Rao
Assistant Professor
Dept. of ECE
TEXT BOOK:
1. “Digital Signal Processing”, Avatar Singh and S. Srinivasan, Thomson
Learning, 2004.

REFERENCE BOOKS:
1.Digital Signal Processing: A practical approach, Ifeachor E. C.,
Jervis B. W Pearson- Education, PHI, 2002.
2.“Digital Signal Processors”, B Venkataramani and M Bhaskar TMH, 2nd,
2010.
3. “Architectures for Digital Signal Processing”, Peter Pirsch John
Weily, 2008.
 Lesson Plan
TOPICS HOURS
Arithmetic operations. 1st
Load and store instructions. 2nd
Logical operations. 3rd
Program-control operations 4th
Programs 5th
Programs 6th
Programs 7th
On chip peripherals 8th
Pipeline operation 9th
Pipeline operation 10th
Contents
 Arithmetic operations
 Load and store instructions
 Logical operations
 Program-control operations
 Programs
 On chip peripherals
 Pipeline operation
 Pipeline operation
 Assembly language instructions can be classified as:
 Arithmetic operations.
 Load and store instructions.
 Logical operations.
 Program-control operations
Arithmetic operations
BANZ: Branch on Auxiliary Register Not Zero
SSBX: Set Status Register Bit
Hardware Timer
 An on chip down counter
 Used to generate signal to initiate any interrupt or any other process
 Consists of 3 memory mapped registers:
 The timer register (TIM)
 Timer period register (PRD)
 Timer controls register (TCR)
 Prescaler block (PSC)
 TDDR (Time Divide Down ratio)
 TIN &TOUT
SSBX: Set Status Register Bit
 STL: Store Accumulator Low Into Memory
 STH : Store Accumulator High Into Memory
 Example3: Write a Program to compute multiply and accumulate
using indirect addressing mode

 Let us assume auxiliary register AR2 to address the data using the
indirect addressing mode.
 AR2 is initialized to 310h, the location where x(n) is stored, and is
advanced to the next address after each multiply operation.
[310h,311h,312h]
 AR3 is used as the pointer to access coefficients starting at h.
 At the end of three multiply operations, AR2 points to 313h, the
address at which the lower 16 bits of y(n) are to be stored.
 And in 314h, higher 16 bits of y(n) are to be stored.
* y(n)= h(0)x(n)+h(1)x(n-1)+h(2)x(n-2)
* h(0), h(1) and h(2) are stored in data memory locations starting
at location h,
*x(n), x(n-1) and x(n-2) are stored in data memory location 310h,
311h, & 312h resp.
*y(n) is saved in data memory location 313h and 314h.
Write a program to compute multiply and accumulate using
MAC instruction.
* y(n)= h(0)x(n)+h(1)x(n-1)+h(2)x(n-2)
* h(0), h(1) and h(2) are stored in program memory locations starting
at location h,
*x(n), x(n-1) and x(n-2) are stored in data memory locations starting at
x.
*y(n) is to be saved in location y and y+1.
 The MAC instruction multiplies the contents of two data-memory
locations and adds the result to the previous contents of the
accumulator being used(note that only auxiliary register AR2-AR5
can be used) This instruction is repeated twice using RPT
instruction.
 After each MAC instruction the auxiliary registers, which are being
used, should be incremented by 1.
 Finally, the result is stored in the memory location pointed by “y”
using STL & STH.
 On chip peripherals
 It facilitates interfacing with external devices.
 The peripherals are:
 General purpose I/O pins
 A software programmable wait state generator
 Hardware timer
 Host port interface (HPI)
 Clock generator
 Serial port
 It has two general purpose I/O pins:
 BIO input pin used to monitor the status of external devices.
 XF output pin, software controlled used to signal external devices.
 Software programmable wait state generator:
 Extends external bus cycles up to seven machine cycles.
Hardware Timer
 An on chip down counter
 Used to generate signal to initiate any interrupt or any other process
 Consists of 3 memory mapped registers:
 The timer register (TIM)
 Timer period register (PRD)
 Timer controls register (TCR)
 Prescaler block (PSC)
 TDDR (Time Divide Down ratio)
 TIN &TOUT
 The timer register (TIM) is a 16-bit memory-mapped register that
decrements at every pulse from the prescaler block (PSC).
 The timer period register (PRD) is a 16-bit memory-mapped
register whose contents are loaded onto the TIM whenever the TIM
decrements to zero or the device is reset (SRESET).
 The timer can also be independently reset using the TRB signal.
 The timer control register (TCR) is a 16-bit memory-mapped
register that contains status and control bits.
Table shows the functions of the various bits in the TCR
When TRB is set, the TIM is loaded with the value in the
PRD and PSC is loaded with the value in TDDR. TRB
always read as a 0.

TSS=0 The timer is started

TSS=1 The timer is stopped

Specifies the timer divide down ratio (period) for the on

chip timer
 The prescaler block is also an on-chip counter. Whenever the
prescaler bits count down to 0, a clock pulse is given to the TIM
register that decrements the TIM register by 1.
 The TDDR bits contain the divide-down ratio, which is loaded onto
the prescaler block after each time the prescaler bits count down to
0.
 That is to say that the 4-bit value of TDDR determines the divide-by
ratio of the timer clock with respect to the system clock.
 In other words, the TIM decrements either at the rate of the system
clock or at a rate slower than that as decided by the value of the
TDDR bits.
 TOUT and TINT are the output signal generated as the TIM register
decrements to 0.
 TOUT can trigger the start of the conversion signal in an ADC
interfaced to the DSP. The sampling frequency of the ADC
determines how frequently it receives the TOUT signal.
 TINT is used to generate interrupts, which are required to service a
peripheral such as a DRAM controller periodically.
 The timer can also be stopped, restarted, reset, or disabled by
specific status bits.
 Host port interface (HPI):
 Allows to interface to an 8bit or 16bit host devices or a host processor.
 The HPI features allow the host to interrupt the DSP, or vice versa,
when it is required.
 Signals in HPI are:
 Host interrupt (HINT)
 HRDY
 HCNTL0 &HCNTL1
 HBIL
 HR/W
 Important signals in the HPI are as follows:
 The 16-bit data bus and the 18-bit address bus.
 The host interrupt, Hint, for the DSP to signal the host when it
attention is required.
 HRDY, a DSP output indicating that the DSP is ready for transfer.
 HCNTL0 and HCNTL1, control signal that indicate the type of
transfer to carry out. The transfer types are data, address, etc.
 HBIL. If this is low it indicates that the current byte is the first byte;
if it is high, it indicates that it is second byte.
 HR/W indicates if the host is carrying out a read operation or a
write operation.
1.
Questions
Describe Host Port Interface and explain its signals.
2. writes an assembly language program of TMS320C54XX processors to compute the sum of three
product terms given by the equation y(n)=h(0)x(n)+h(1)x(n-1)+h(2)x(n-2) with usual
notations. Find y (n) for signed 16 bit data samples and 16 bit constants.
3. Describe the pipelining operation of TMS320C54XX processors.
4. Explain the operation of serial I/O ports and hardware timer of TMS320C54XX on chip
peripherals.
5. Expalin the different types of interrupts in TMS320C54xx Processors.
6. Describe the operation of the following instructions of TMS 320c54xx processor, with example
7. Describe the operation of hardware timer with neat diagram.
8. By means of a figure explain the pipeline operation of the following sequence of instruction if the
initial values of AR1,AR3,A are 104,101,2 and the values stored in the memory locations
101,102,103,104 are 4,6,8,12. Also provide the values of registers AR3, AR1,T & A.
9. Describe the operation of the following instructions of TMS320C54XX processors
9. Describe the operation of the following instructions of TMS320C54XX processors. (July 12, 8m)
10. Explain the following assembler directives of TMS320C54XX processors (i) .mmregs (ii).global (iii)
.include „xx‟ (iv) .data ( v) .end (vi) .bss (Dec 09/Jan 13 6marks).
11. Describe Host Port Interface and explain its signals. (Dec 09/Jan 10 6marks).
12. writes an assembly language program of TMS320C54XX processors to compute the sum of three product
terms given by the equation y(n)=h(0)x(n)+h(1)x(n-1)+h(2)x(n-2) with usual notations. Find y (n) for
signed 16 bit data samples and 16 bit constants. (May/June 2011, 6m).
13. Describe the pipelining operation of TMS320C54XX processors.(Dec.11, 8m).
14. Explain the operation of serial I/O ports and hardware timer of TMS320C54XX on chip peripherals.
(Dec.11, 8m).
15. Expalin the differents types ofinterrupts in TMS320C54xx Processors.(May/June 2009, 6m)
Thank you