Pimonpelins wihou

pijdalina.
pipeline fetch1Excu 1feh 2 E 2
pieelinarh
feth 2 E 2
fteh3 [8e 3

T/ T T T T
Tdepends (yde cycle to eneute instruc"
Gn osilla ? neyde to feteh next
ohen no ipeline
Crystal
T=. DelayCalulathion for ArR
q find size of dlay ,if wstal freq is lo MMz
T
instru?
-DEF cOUNT =R20
yde
DELAY: LDI coUNT, Ox fF
1
AGAIN : NOP
Nop
tOfDEC coUNT: cydu to chut
BRNE AGAIN 2/4 if count is zew
RET ofee y cde to
2retusun
4 to AGAIN.
OR

DELAY =1+ (1+1142)x 255 -1*4x 0-1 4s. eny ydeto

des check z fag =1
instru when R go to net
repeut for 255 z tay =1.
instruc
times (last
coun tee).
Q tind e vize of delay f f-1MHz
DELAY : LDT inbte yde
R20, oxff.
AGAIN NoP
Nop Ddlay -(sras) -1 *1
+4
DEC R20
8RNE AGAIN 2/1
RET. 4. = l279 yS.

loep_ inide aaloop dly

0 DELAY : LDI RI6, 200 intru"uyde each instruc
AqAIN LDI Ri7,250 . (ii) tukes up
HERE Nop Qby te of eary
Nop in prog vam
DEC RI7
(6) BRNE HERE. 2/4
gx2
) DEC RI6
BRNE AGAIN 2/1 Is byte
) RET. 4

HERE locp
AGAIN loop
= Q498 ys. (RI6).
(250 epecuting

20ox (1+ti+2)-1 I 45. 799 ys.

AGAIN Loop
Delay 498+ 799 +(1+4)t4s
().
 T=145
inbtruc ycle
DELAY : LDI RI6, 20D
AqAIN : Nop
Nop
Nop 12 tims. RoM spue
rqwrnd.
NOP l6x2 =32 by te
DEC RI6 1
BRNE AGAIN 2/1
RET

Deluy 1+ 20o(15) -1+]x i4s : 3004 48

Disadu : tqçres more memony spuce but vsty less dlelay

is obtuned

T/0 proqumming in AVR

Port A, 0, C, D> I/0 pors.
Each port bas Some func' such us ADC , tiners, interrup sy
use for I/o these fns fixed by cPU deslqn ex
PoRT
Fach port ’ 3 vegistes (I/o) ’ DDE« (datu direc reyilas).
SPIN (port input pins)
PoRTX ’ /p
DDRX ’ ietian PINX ’ input
bins.
ach ip- o/p rsisJoe is bit wrde, mux. 8

DDRX regsto role in _outputing the det

8’ outpud port 8’ input pont.
LDI RI6, Ox ff lDI RI6, ox00 ’ inputing the dute.
OUT DDRO, RI6 oUT DDRB, RI6
 time deau
rogreum to toggle ul S bis of port & fortre oi th Some
LDI RI6, oxPf
LDI iotializu
DDR6, RI6 -J (assigring povt B as op pot).
LDIL RI6, Ox 55
OUT PORT B, R6J Strunsclatu
fe ot
CALL DELAY
com RIG

CALL DELAY.
RgMP Li.
coite hu dutu clute
(trunsfe t pin).
DDRX-n
trom cpUto
pin n of PoRTX-n
HPIN*n
oukid insiele ’ead ke clat.
celle cduta fno m pins
to coU.
DDRx =0 PDRx =i.

pORT
f
poRT

HPIN HPIN
Gnly read datu. ik He data. 2
tunsf to PIN to recolit,

o% Poot G { send it to port

pryrum to get the datu at pins
E adeling value 5R to it:
io dafirity, altee
.INLUDE "M32DE F. INC
LD I RI6, oKo0

FF
LDI RI6, ox
OUT PDRB, RI6
IN RI6, PING
LDI R I7, 5
RI6, R17
ADD RÊMP L1.
OUT PORTB, RI6
 MC minor
prog rum Huh memora Boot progru sectien
Botk o App lic atien proyum setion.
Stack ’ when one fxnt calls fen 2, ohile rtwening fom the call ,stack
Stores the addoess af fn (storiog etn adloress)
alocatd from 8RAM) Space
rhepto- pointee : acd es of mem ony loccation
Addus
pointo ’k e megis es l6 bit memorg
fEPRom’ ohen erbed, l . bis ce set to fFr.
o3
R22
R3I ox2

Cutl irshuctian asouoted oitfh addres /label.

wnen Suboutine is coutled, processoT Sewes the acdcless of ins trueis
two reyisto Addressing mode
<bit Sbit Gbit
op ode RyRa

progrumthet conti nuously seuncls out to port c th altoen atin

vues of ox55 2 ox A
M32D EF. IN C
LD I ;RI6=lI|
DDRC, RI6 ; mete pot G an o/p port
L1: LDI RI6,0x55
t p UT PORTC,RI6
Pak LDT Rj 6, 0 xAA
OuT
PoRTC,.R16 :

-progrum to send data from pot A sawre in RAM ocatien

INLUDEm32 D£E. IN
)
! IN RI6, P IN A
LDI RI6. oxO0 STS MY JEMP, R6.
DpR DUT DDRA, Ri6
Nop
 ize
dyn chons
dlay
/p dt. of AvR hus u dely of 1 dock yde
PIN egistee conbis bof the data ohi ch oas present 1dock bejo
I<O bit munipulatien proyrunming
cgpicuble t o-31 Io qitte
s8I(Set bit in Lo eyistee), 7454 3 2|0

SBI poRT D, 0
L65 49 2 o
S8I DDRC, 5 ,b b i t no.
SBI
|(001010 qaad abbb 6* bit of Jocatien aas I
setting
for SBI s bit

C8I (deut bit in IO rcyistex),

O 0
PORT D, 0 j PoRTD.
C8I DDRC.5 ; DDRC.5 =O

progran to toggle PIN82 ontinously,

S6I DDR8, 2.
AGAIN : 881 PoRTB, 2
CALL DÀLAY
C8I PORTB,2
CAL DELAY.

poot D. wAP o tun on each LED from'pio Do to D7

of
an LeD conneted to each pio tuning sn e t LED.
delay sub routi e before
·INuvDE "M32DEF. INC
LDI R20, oxfE
OUT RAD, R20
DDR
SBI PORT D, D
CAL DELAY.
S8I PORT, I
CAAL DPLAY:
S8I POkT, 2
S8IC (skip if bi't in Io eqistee cleared)
S8IC CoReg, bit num.
S8IC o, b 10o10olaaaa abbb
wed for his
°=32 eqistees can beinbtrution:
$81C PoRTD, 0 ; skop nert
TNC R20 instruction if PORTD.0 =0
TDI Ri9, Ox23

SBIS (sip it bit in Io reuistket set.

PoRTD.O 1
581S PDRTD, O; sio oet inbtruton if
INC R20
LDI RI9, 0x23
monitoni ng PB2 unil it beLomes high.
e Progrcum ’ ) keep to pot c.
i)then PB2 is high, ori e volue S45 PDs.
also sund a high -to-low puse to
.INLUDE "M32.DEF. INC
CBI DDR B, 2 make PB2 an input
5BI PoRT8;2
LDI RI6, oxff mlke port Can ofp porf.
OUT DDR C, RI6
S8I DDR D, 3 j
muke PD3 aun o/p

AGAIN : sgIS PINB, 2 ;skip nent inbtruc? if bit PB2 is high

RZMP AGAIN ; check if LOw
LDI Rl6, ox45
wite ox 45 to Port C:
DUT PORTC, RI6
SeI PORD,3
CBI PoRTD) 3 high to low pule
MERE : RZrMP HERE.
.INUUDE "M32 DEF.TNC?
to get C&I DDRB, 0
AYR pogram
stutus of Sw S8I PPRB, 7
47k P80 de
serd it AGAIN: S8lG PINB,;ski) et i
Sw C8T PORT8, 7
70 t LED.
RTMPpgAIN
QVER :S8I PORTB, 7
Aithmutic logiccal_cpr atitn pyummiog,
5

unsigned numbes o 255 256 ’ 2 UT

65 4
Siqntd nun bes ’ -128 to -l 27
Oto 127

sign
negatire positiie.
p. add 3cE7 and 388D, location - R30 R’E7
Stoe tsult in

ADD Ry,R ; Ra=

Ry Rut R
R,R iadd uith cury Rg=Rgt +C
Substruction, y=Kstgnuroedat attee
SUB Ra, Ry

Rd, Ry ; Ry= Ra- R,-G.. (c qenertd io

pretous steps).
SuBI Ra, K; Ra = Rj-k.
Ra, K ; R = Ri-k-c.
: Rd , k
s liited to sGPR's R23 to R3|

f. Bubstrat 18H from 2917 K

LDI R23, Ox(14.
LDI R24, 0x23

S8IW R24 : R23. 0x18

H.
Q. substrat 6 bit oun beres 2762 M - 296
= 624 and R27 = 27# place he oli ffene in
R26
lowet byte
R26 cund Re7: R26 should howe
LDI R24, 0x96
LDI R25, 0x 12
8RT) SUB R26, R24
S68C R27, R25
ROR instru tion
otute ig ht Le ; dear eamy fuy
CLC C=0.

Camy
RoL fla
otuBe left,
SEC
;set curr flaq > (=1 .
DI R20,0x15 ; R20 = o0ol ol0| c .
msB RoL R20, RR0 ooIo10)|C=D
RoL R20 R20 = Ol0|0|o c

shitt instution, C;C

LSL, logicad shift lext. LDI R20,0X26 R20 = 0ol0 o O3
LSL R20 ;R2D ol 00 loo6) c=0
HmsB (Se0. LSL R20 ; R20 z l00| I000052)co
LSL R20 R20 = oo|| 0000()c=1 .
ontens of R20 m bung mutiplied
by 2 ohen the cumy ay c=0. by
multiplicd
when c=1, R20 oill not be
LSR logicad shift mght DI R20, 0x26 R20=00lo ol1D (38)
C0
0’]ms8 LSB LSR R20 R202000) 00u(19),
C=
willeach SK R20: R20 = 0000 l00l (9) ,
contens of regitkex
afr LSR R20 R20 = o00D oJ00(4),
cJ:
be divided by 2
instucton cwil show he
neminde
tDI R2o, axDA R20 110lou0
ASR, ornthmaie shift ight
only for oR R20: R20>TT0 ToTt ,

LS8-C signed
Dumbe. 23tomplimunt
0XDO:R20 I|0| 0000 (-48),C=O.
LDI R20,
1000(-24)) C0.
ASR R20 R20 =||0 oj00 (-12), C0.

| Joo -6), C -0
AsR R20 R20
ASR (-3)
ASR (-2)
ASR ()
 Assum e hut R20 hab the ho. - 6,
shoob that SR can't be
6
Used to diide he content of e20 by 2
LDI R20, oxFA
LsR R20

450
IR5.
tre
wmbe
Q. . shou how we CCun ude RoR to diide by 8
CLC
LDI R20, OX 3o 48= 00 16| 0000
ROR R20 ; RR0 = oo01 1000,CEo
Rao = 3
S(24)
ROR K20 ; R000o0 oo (i2, C 0
CLC
C0.
KOR R20 RR0= 000o ouo(6),

SOAP
Rd.
Before, |D, - D4 JD,-Do

-D. D,-Dy Rd.

execution of code.
e. tind contents of R20 after o010 (72 H).
R20, OX 72 ; R20 Oll!
LDI
SwAP R20; R20 oo0 O | (274)

ence of swp instruction, how coould you exch an ge oibbles

Q. in the cabs