VLSI Design Flow (RTL to GDS-ll)

A Vocational Training Report submitted

To
Chhattisgarh Swami Vivekanand Technical University Bhilai (C.G.),
India

In fulfilment for award of the degree

Of
BACHELOR OF TECHNOLOGY
In
Electronics & Telecommunication Engineering
By
Nikhil Sahu (301602821016)

Department of Electronics & Telecommunication Engineering

Government Engineering College, Sejbahar
Raipur (C.G.)
Session: 2024–2025
 DECLARATION BY THE CANDIDATES

We the undersigned solemnly declare that the report of the Vocational Training on
“VLSI Design Flow (RTL to GDS-ll)”, is based on our own work.
We assert that the statements made, and conclusions drawn are an outcome of the
training work. We further declare that to the best of our knowledge and belief that the
report does not contain any part of any work which has been submitted for the award of
any other degree/diploma/certificate in this University/deemed the University of India or
any other country. All help received and citations used for the preparation of the
Vocational Training Report have been duly acknowledged.

(Signature of the candidate)

Name: Nikhil Sahu
Roll No: 301602821016
Enrolment No: CA9265
 TABEL OF CONTENT

Chapter 1 Introduction…………………………………………….……..…………………1
Chapter 2 Training Program Details………………………………………...……...………2
2.1 Course Structure and
Duration……………………………………………..2
2.2 Prerequisites and
Eligibility………………………………………………..2
2.3 Mode of Delivery…………………………………………………………..2
2.4 Institution
Details…………………………………………………………..2
Chapter 3 Course Content……………………………………………………………………
3
3.1 Overview of VLSI and its Design Flow……………………………………
3
3.2 Hardware Mode0ling and RTL
Synthesis…………………………………..6
3.3 Static Timing Analysis (STA)
……………………………………………....7
3.4 Physical Design
Concepts………………………………………………….8
Chapter 4 Tools and
Software………………………………………………………………..9

4.1 Yosys : RTL Synthesis and Logic Optimization……………………………

9

4.2 OpenSTA: Static Timing Analysis………………………………………..

10

4.3 Magic and OpenROAD : Physical

Design………………………………...11

4.4 GTKWave : Waveform Analysis and Debugging…………………………

12

Chapter 5 Learnings and Project………………………………………………………….13

 5.1 Learning
Outcomes……………………………………………………….13

5.2 Project Work……………………………………………………………...13

Chapter 6 Conclusion……………………………………………………………………….15

List of Figures

Fig. 1: A typical VLSI Design Flow……………………………………………………………

5
Fig. 2: VLSI layout of an inverter circuit using Magic software………………………………
11
Fig. 3: Waveform analysis using GTKWave…………………………………………………
12

INTRODUCTION CHAPTER 1

The vocational training program on VLSI Design Flow (RTL to GDS-II) was organized by
the National Institute of Electronics and Information Technology (NIELIT), Noida in
collaboration with SoC Teamup Semiconductors Pvt. Ltd. This online training aimed to
equip participants with a comprehensive understanding of the VLSI design process, from
Register Transfer Level (RTL) design to physical layout generation (GDS-II).

The course emphasized hands-on experience with industry-relevant tools and methodologies,
providing participants insights into digital design, ASIC and FPGA technologies, and
emerging trends in power-efficient design strategies. The training also included lectures by
experts with extensive industry experience in chip design and manufacturing. Additionally,
the program highlighted practical applications through project work and encouraged
interaction with peers and instructors for effective learning.

This training addressed the growing demand for skilled VLSI engineers capable of designing
advanced chips for diverse applications, including consumer electronics, telecommunications,
and automotive systems. By bridging the gap between academia and industry requirements,
the program aimed to foster the development of future-ready professionals.
 1

TRAINING PROGRAM DETAILS CHAPTER 2

2.1 Course Structure and Duration

The training program spanned 30 days or 6 weeks with a total of 60 hours of learning.
Sessions were conducted in online mode for two hours daily. The curriculum was designed
to balance theoretical lectures and practical assignments, ensuring participants grasp both
fundamental concepts and their real-world applications. Special focus was given to the
integration of interactive tutorials and problem-solving sessions to enhance participant
engagement.

2.2 Prerequisites and Eligibility

Participants were required to have:

 Basic knowledge of digital circuits and logic gates.

 Familiarity with hardware description languages like Verilog or VHDL.
 Experience working in a Unix/Linux environment.

The course was open to B.Tech/M.Tech/B.Sc/M.Sc students, diploma holders, faculty,

research scholars, and industry professionals. This inclusivity aimed to attract a diverse group
of learners with varying levels of expertise in electronics and VLSI design. Applicants were
encouraged to review preparatory material on digital design and Unix basics to maximize
their learning experience.

2.3 Mode of Delivery

The training was delivered entirely online through interactive lectures, tutorials, and
assignments. Participants accessed the sessions via the NIELIT Kaushal Setu app or the
institute’s official registration portal. The use of digital platforms ensured accessibility and
allowed participants to review recorded sessions for better understanding. This mode of
delivery enabled learners from remote locations to benefit from the program without
geographical constraints, fostering inclusivity and widespread participation.

2.4 Institution Details

National Institute of Electronics and Information Technology (NIELIT), Noida, a
premier institute under the Ministry of Electronics and Information Technology (MeitY),
Government of India. It offers industry-relevant training in areas like Artificial Intelligence,
Data Science, Cybersecurity, Embedded Systems, and more. The institute is known for its
advanced infrastructure, expert faculty, and collaboration with leading tech companies.
NIELIT Noida provides certifications, short-term courses, and diploma programs aimed at
empowering students and professionals with cutting-edge IT and electronics skills. It plays a
vital role in building a skilled digital workforce for India's tech-driven future.

2
COURSE CONTENT CHAPTER 3

3.1 Overview of VLSI and its Design Flow

What is VLSI?

VLSI refers to the process of creating an integrated circuit (IC) by combining millions (or
billions) of transistors onto a single chip. This technology has revolutionized electronics by
enabling compact, high-performance devices such as smartphones, laptops, and IoT gadgets.

Integration Levels:

o SSI (Small-Scale Integration): A few tens of gates (e.g., flip-flops).

o MSI (Medium-Scale Integration): Hundreds of gates (e.g., multiplexers).
o LSI (Large-Scale Integration): Thousands of gates (e.g., simple processors).
o VLSI(Very Large Scale Integration): Millions/billions of transistors (e.g.,
modern CPUs, GPUs).

What is VLSI Design Flow?

VLSI design flow is a structured process that converts a high-level specification of a

digital/analog system into a physical chip. The steps are as follows:

1. Design Specification

 Define the functional requirements, performance criteria, power constraints, and area
goals for the IC.
 This stage involves creating the architectural design based on the desired system
functionality.

2. RTL Coding

 Use Hardware Description Languages (HDLs) like Verilog or VHDL to describe the
design at the Register Transfer Level (RTL).
 The design specifies how data flows between registers and the logic for processing it.

3. Functional Simulation

 Simulate the RTL design to verify the intended functionality.

 Functional correctness is ensured before moving forward.

4. Coverage Analysis

 Analyze how well the functional test cases cover all possible scenarios in the design.
 Ensures thorough testing to catch design errors early.

3
5. Logic Synthesis

 Convert the RTL design into a gate-level netlist, mapping it to the target technology
library.
 Tools like Synopsys Design Compiler or YOSYS are used for synthesis.

6. DFT Synthesis (Design for Testability)

 Add testability features, such as scan chains, to facilitate testing during production.
 This ensures that manufacturing defects can be detected effectively.

7. ATPG Vector Generation

 Generate test vectors using Automatic Test Pattern Generation (ATPG) techniques.
 These vectors are used during chip testing to identify faults.

8. Logic Equivalency Checking

 Verify that the synthesized gate-level design is functionally equivalent to the original
RTL design.
 Ensures no functionality is lost during synthesis.

9. Floor planning

 Define the physical layout of the chip, arranging major functional blocks.
 The layout considers area and performance constraints.

10. Power Planning

 Design the power distribution network to ensure consistent power delivery across the
chip.
 Avoid power drops and ensure reliability.

11. Placement

 Place the synthesized gates and cells within the defined floorplan.
 Tools optimize for timing, area, and power during this step.

12. Clock Tree Synthesis (CTS)

 Design the clock distribution network to minimize clock skew and maintain
synchronization.
 Essential for the proper timing of sequential elements.

13. Routing

 Connect all placed cells using metal layers to form the signal and power paths.
 Ensure proper connectivity while minimizing delays and congestion.

4
14. Static Timing Analysis (STA)

 Verify the timing constraints of the design, ensuring that signals meet setup and hold
time requirements.
 Detect and resolve timing violations.

15. Gate-Level Simulation

 Simulate the gate-level netlist to validate functionality and timing after physical
implementation.
 Ensures the design behaves as intended post-synthesis and routing.

16. GDSII (Graphic Data System II)

 Generate the final layout file (GDSII), which is sent to the foundry for fabrication.
 The GDSII file contains the complete physical representation of the chip.

Fig. 1: A typical VLSI Design Flow

5
3.2 Hardware Modeling and RTL Synthesis

What is Hardware Modeling?

Hardware modeling refers to the process of representing the behavior and structure of
hardware systems using formal description methods. It is a fundamental step in the design of
digital systems, enabling designers to simulate, analyze, and verify the system's functionality
before physical implementation. Models are represented at different abstraction levels, such
as behavioral, dataflow, structural, or register-transfer level (RTL), and are described using
Hardware Description Languages (HDLs) like Verilog or VHDL. Hardware modeling
enables simulation and validation, allowing designers to verify functionality, timing, and
performance under various conditions.

Levels of Hardware Modeling:

1. Behavioral Modeling: Describes what the hardware does without specifying how it is
implemented.
2. Dataflow Modeling: Specifies the flow of data through the system using operators
and assignments.
3. Structural Modeling: Represents the hardware as interconnected components or
gates.
4. Register Transfer Level (RTL) Modeling: Combines behavioral and structural
elements to describe how data is transferred between registers under clock control.

What is RTL Synthesis?

RTL (Register Transfer Level) synthesis is the process of transforming an RTL hardware
description into a gate-level netlist. This step maps the high-level description to the
technology-specific logic gates and flip-flops using a target library. The synthesis process
involves analyzing the RTL code to build an intermediate representation, optimizing the
design for area, timing, and power, and mapping it to the target technology library to produce
a gate-level netlist. RTL synthesis ensures the design meets performance and power
requirements while automating the transformation of abstract descriptions into
manufacturable forms.

Steps in RTL Synthesis:

1. Input Specification: RTL code and constraints (e.g., timing, area, power) are
provided.
2. Elaboration: Hierarchical definitions are resolved, and the design is analyzed.
3. Optimization: The design is optimized for area, timing, and power efficiency.
4. Technology Mapping: High-level constructs are converted into standard cells from
the target library.
5. Netlist Generation: The final gate-level netlist is generated for implementation.
 6
3.3 Static Timing Analysis (STA)

What is Static Timing Analysis?

Static Timing Analysis (STA) is a method of verifying the timing performance of a digital
design without requiring simulation. It evaluates the timing of all possible paths in a circuit
based on the design constraints, ensuring that the design meets its timing requirements such
as setup and hold times for sequential elements (e.g., flip-flops and latches). STA is a
cornerstone of digital design verification, particularly in large and complex circuits like
ASICs and FPGAs, where exhaustive simulation is infeasible.

Steps in Static Timing Analysis

1. Design Netlist: The process begins with a gate-level netlist obtained from RTL
synthesis or post-layout steps.
2. Timing Constraints: The designer provides constraints such as clock definitions,
input/output delays, setup and hold times, and clock skew tolerances.
3. Timing Models: Timing libraries containing cell delay information for the target
technology are used for delay calculations.
4. Path Analysis: STA identifies all timing paths in the circuit, including:
 Combinational paths between sequential elements.
 Clock paths for distributing clock signals.

5. Delay Calculation: The delays of each cell and interconnect in a path are calculated
using technology-specific timing models.
6. Slack Calculation: For each path, the slack (difference between required time and
actual arrival time) is calculated:
 Positive Slack: The path meets timing requirements.
 Negative Slack: The path fails to meet timing requirements and needs
optimization.

7. Critical Path Identification: STA highlights the paths with the most negative slack
(or the least positive slack), which require optimization.
8. Report Generation: Timing reports summarize violations, slack values, and critical
paths for further analysis.

Key Metrics in STA

1. Setup Time: The minimum time before the clock edge during which the input data
must remain stable.
2. Hold Time: The minimum time after the clock edge during which the input data must
remain stable.
 3. Clock Skew: The difference in arrival times of the clock signal at different flip-flops
or sequential elements.
4. Propagation Delay: The time it takes for a signal to propagate through a logic gate or
interconnect.
5. Slack: Indicates whether the design meets or fails timing requirements 7

3.4 Physical Design Concepts

What is physical design?

Physical design is a crucial step in the VLSI (Very Large-Scale Integration) design flow,
where the logical design is translated into a physical layout suitable for manufacturing. This
phase ensures that the chip will function correctly and meet performance, area, and power
specifications. The key concepts in physical design are as follow:

1. Floor planning: Floor planning is the process of determining the optimal placement of
modules (e.g., functional blocks) within the chip area. The goal is to minimize the wire
lengths between blocks to reduce delay and power consumption. Floor planning also involves
the allocation of space for routing channels and ensuring that the chip’s design meets area
constraints.

2. Placement: Placement refers to the positioning of standard cells (basic functional units like
AND, OR gates, flip-flops) within the chip area after the floorplan is decided. It aims to
optimize the performance by minimizing wire lengths and congestion.

3. Clock Tree Synthesis (CTS): The Clock Tree Synthesis (CTS) is a critical step to
distribute the clock signal evenly across all flip-flops within the design. The clock signal
needs to reach every sequential element at roughly the same time to prevent timing errors.
CTS ensures a balanced and low-skew clock network.

4. Routing: Routing is the process of connecting the cells and blocks in the chip using metal
layers. This step involves creating the physical wires (interconnections) between the standard
cells as per the netlist provided by the designer.

5. Design Rule Checking (DRC): Design Rule Checking is a verification step in physical
design where the layout is checked against a set of manufacturing rules defined by the
foundry. These rules ensure that the design can be fabricated correctly and that there are no
violations that might cause manufacturing defects.

6. Layout versus Schematic (LVS): Layout versus Schematic (LVS) is a verification process
to ensure that the physical layout matches the original circuit design (schematic). This step
checks for errors in connectivity and ensures that the circuit operates as intended.
7. Physical Verification: Physical verification involves checking the layout for various issues
that could affect manufacturability, such as incorrect layer usage, violations of design rules,
and electrical issues like shorts and opens.

8
TOOLS AND SORTWARE CHAPTER 4
4.1 Yosys : RTL Synthesis and Logic Optimization

Yosys is an open-source tool for RTL synthesis and logic optimization, widely used in VLSI
design. It converts high-level Verilog code into optimized gate-level netlists, which are
essential for hardware implementation.

RTL Synthesis with Yosys

1. Parsing: Yosys reads and parses Verilog code to check for syntax errors and creates
an internal representation.
2. Optimization: It applies techniques like constant folding and dead code elimination
to reduce design complexity.
3. Technology Mapping: Yosys maps the optimized design to a gate-level netlist using a
specific gate library.
4. Netlist Creation: The final output is a gate-level netlist for further physical design or
simulation.

Logic Optimization with Yosys

Yosys applies various optimizations to improve design efficiency:

 Constant Folding: Simplifies constant expressions.

 Dead Code Elimination: Removes unused logic to reduce area.
 Boolean Simplification: Reduces gate count by applying Boolean algebra.
 Logic Sharing & Merging: Minimizes gates by reusing and merging logic.

Example Usage

Yosys is controlled using synthesis scripts. For example, the following Yosys synthesis script
reads a design (with the top module mytop) from the verilog file mydesign.v, synthesizes it to
a gate-level netlist using the cell library in the Liberty file mycells.lib and writes the
synthesized results as Verilog netlist to synth.v:

# read design

read_verilog mydesign.v

# elaborate design hierarchy

hierarchy -check -top mytop

# the high-level stuff

proc; opt; fsm; opt; memory; opt

# mapping to internal cell library

techmap; opt 9

# mapping flip-flops to mycells.lib

dfflibmap -liberty mycells.lib

# mapping logic to mycells.lib

abc -liberty mycells.lib

# cleanup

clean

# write synthesized design

write_verilog synth.v

4.2 OpenSTA: Static Timing Analysis

OpenSTA is an open-source tool used for static timing analysis (STA) in digital design,
primarily for ASIC and FPGA designs. It analyzes the timing of a circuit to ensure that it
meets required performance constraints without the need for simulation.

Key Features of OpenSTA:

1. Timing Verification: OpenSTA checks setup and hold violations by analyzing the
delay of signals through the design.
2. Path Analysis: It evaluates all possible paths from inputs to outputs, ensuring they
meet timing constraints.
3. Clock Domain Crossing: OpenSTA handles multi-clock designs and ensures proper
synchronization between different clock domains.
4. Optimization Feedback: It provides critical timing information to guide
optimizations during the design process.

A sample command file that reads a library and a Verilog netlist and reports timing checks is
shown below.
read_liberty example1_slow.lib
read_verilogexample1.v
link_design top
read_sdf example1.sdf
create_clock -name clk -period 10 {clk1 clk2 clk3}
set_input_delay -clock clk 0 {in1 in2}
report_checks

10

4.3 Magic and OpenROAD : Physical Design

Magic and OpenROAD are powerful open-source tools used for physical design tasks like
placement and routing in VLSI design.

Magic:

Magic is a layout editor and a tool for designing and editing integrated circuit layouts. It
supports:

 Manual Layout Editing: Create and edit layouts at the transistor level.
 Design Rule Checking (DRC): Ensures that the design adheres to fabrication rules.
 Layout Versus Schematic (LVS): Verifies the layout against the schematic to ensure
correct functionality.

OpenROAD:

OpenROAD is a comprehensive open-source toolchain for physical design automation,

focusing on:

 Placement: Optimizes the placement of cells to meet timing, power, and area
constraints.
 Routing: Automatically connects cells while minimizing wire lengths and congestion.
  Clock Tree Synthesis (CTS): Generates the clock distribution network to ensure
balanced clocking.

Fig. 2: VLSI layout of an inverter circuit using Magic software 11

4.4 GTKWave : Waveform Analysis and Debugging

GTKWave is an open-source waveform viewer used for analyzing and debugging Verilog
simulations. It helps visualize simulation results and troubleshoot issues in digital designs.

Key Features of GTKWave:

 Waveform Visualization: Displays signal transitions over time for easy analysis of
Verilog simulation outputs.
 Multiple Signal Support: Handles large sets of signals, enabling detailed inspection
of complex designs.
 Customizable Display: Allows users to adjust the format, zoom levels, and signal
grouping for better clarity.
 Integrated with Simulators: Works with various simulators (e.g., ModelSim, Icarus
Verilog) to view simulation results.
 Fig. 3: Waveform analysis using GTKWave

12
LEARNINGS AND PROJECT CHAPTER 5

5.1 Learning Outcomes

The key learnings are:

 A robust understanding of the VLSI design flow, encompassing RTL design,

synthesis, timing analysis, and physical design.
 Mastery of Verilog HDL for modeling digital systems.
 Proficiency in using industry-standard EDA tools for various design stages.
 Skills to identify and resolve timing violations using static timing analysis techniques.
 An appreciation of challenges like power, performance, and area trade-offs in chip
design.
 Improved problem-solving skills through exposure to real-world design challenges.
5.2 Project Work

32-bit ALU Design

The 32-bit ALU designed using QFlow implements a variety of arithmetic and logical
operations on 32-bit inputs a and b. The ALU is controlled by a 4-bit selection signal (sel)
and can perform operations such as addition, subtraction, multiplication, division, bitwise
AND, OR, XOR, and shifts. The design is implemented in Verilog, with a clock and reset
input, and outputs a 32-bit result (out) and a carry flag. The QFlow toolchain is used for
synthesizing and optimizing the design, handling placement and routing, and ensuring the
ALU operates correctly in a physical layout. This ALU can be integrated into larger VLSI
systems for various computational tasks.

The Verilog code for 32-bit ALU is as follow:

module alu(
input clk,rst,
input [31:0] a,
input [31:0] b,
input [3:0] sel,
output reg [31:0] out,
output reg carry);
wire [31:0] tmp;
assign tmp = {1'b0,a}+{1'b0,b};
assign carry = tmp[31]; 13
always @(posedge clk)
begin
if(!rst)
out <= 32'b0;
else
case(sel)
4'b0000 : out = a+b;
4'b0001 : out = a-b;
4'b0010 : out = a*b;
4'b0011 : out = a/b;
 4'b0100 : out = a|b;
4'b0101 : out = a&b;
4'b0110 : out = a^b;
4'b0111 : out = ~(a|b);
4'b1000 : out = ~(a&b);
4'b1001 : out = ~(a^b);
4'b1010 : out = a<<1;
4'b1011 : out = a>>1;
4'b1100 : out = {a[0],a[31:1]};
4'b1101 : out = {a[30:0],a[31]};
4'b1110 : out = (a>b)?32'b1:32'b0;
4'b1111 : out = (a==b)?32'b1:32'b0;
default: out = a+b;
endcase;
end
endmodule

14
CONCLUSION CHAPTER 6

The vocational training on VLSI Design Flow (RTL to GDS-II) provided a solid foundation
for participants aspiring to pursue careers in VLSI design and semiconductor industries. The
blend of theoretical lectures and practical sessions helped bridge the gap between academic
concepts and industrial applications.

For students and professionals like the participants, this program was an excellent stepping
stone toward contributing to cutting-edge chip design and fabrication technologies.
Additionally, the exposure to industry-standard tools and expert guidance prepared
participants to handle real-world challenges in the semiconductor field effectively.
15