TP 01 VHDL
Uploaded by
Adoui HanaTP 01 VHDL
Uploaded by
Adoui HanaSupprimer Wondershare
filigrane PDFelement
University of Skikda Electrical engineering department
PS VHDL - FPGA
Practical session 01: Introduction to VHDL and ModelSim
-. .Adoui
. . . . .Hana.
...................................
Student -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
names
-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1. Write the VHDL program below on the ModelSim software.
Press: File/New/Project.
Give a name for the project, then press OK.
Press 'Create new file'.
Give a name for the file, then press OK.
Close the window ‘Add items to the project’.
Double-click on the file name which is in the ‘Workspace’ window.
Write the following VHDL description (there is no difference between upper- and lower-case
letters in VHDL):
library IEEE;
use IEEE.std_logic_1164.all;
entity f1 is
port (a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
r : out std_logic);
end f1;
architecture rtl of f1 is
begin
s <= (a xor b) xor c;
r <= (a and b) or (c and a) or (c and b);
end rtl;
2. Determine inputs and outputs.
Inputs are: . a,b,c
............................
Outputs are: .s,r
............................
Dr. A. Ganouche
Supprimer Wondershare
filigrane PDFelement
3. Give the corresponding logic circuit (using the following logic gates):
r=ad+ac+bc
S=(a⊕b)⊕c |
a
|
a ⊕
| b
b S | ab r
c c
| ac
bc
| c
|
|
4. Compile the program by pressing File/Save, then Compile/Compile Selected.
At the bottom, in the 'Transcript' window, there is a message in green that says 'Compile of
****.vhd was successful.'. This means that the compilation was successful.
If the message is in red saying '# Compile of ****.vhd failed with 1 errors.', double click on it to
open the error message → fix the error → save (File/Save) → compile another time
(Compile/Compile Selected) → repeat these steps until the message on the 'Transcript' window
turns green.
5. Simulate the program with different inputs and give the truth table.
Press Simulate → start simulation → + work → select entity name → OK → View → Wave →
Drag entity name from 'Instance' to 'wave' → right click on entry 'a' → force → value → put 0
or 1 → in the same way force the inputs 'b' and 'c' → then press 'Simulate' → 'Run' → 'Run
100'.
If nothing appears on 'wave' change '0 ns' to '100 ns', then press 'Simulate' → 'Run' → 'Run
100'
The truth table:
a b c r s
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
6. What is the function performed by f1? full-adder.
.............................
7. Change the VHDL description to perform the function f1 ignoring input ‘c’. half-adder
library IEEE;
architecture rtl of f1 is
use IEEE.std_logic_1164.all;
begin
entity f1 is s <= a xor b ;
c <= a and b ;
port ( a : in std_logic; end rtl;
b : in std_logic;
s : out std_logic;
c : out std_logic);
Dr. A. Ganouche
end f1;