TP 02 VHDL
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Adoui HanaTP 02 VHDL
Uploaded by
Adoui HanaUniversity of Skikda Electrical Engineering Department
PS VHDL-FPGA
Practical session 02: Comparator in VHDL language
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Student
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names
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1. PS objectives:
At the end of this PS, you will be able to: use the ModelSim interface, write a
VHDL description of a comparator, compile and simulate a VHDL description,
and use conditional assignment.
2. The Comparator:
The comparator is a combinatorial circuit which makes it possible to compare
between two binary numbers. It has two inputs and three outputs.
a s : superior (a > b)
Comparator e : equal (a = b)
b
i : inferior (a < b)
The truth table of the comparator of two one-bit numbers is given by:
Inputs Outputs
a b s (a>b) i (a<b) e (a=b)
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1
Inputs 'a' and 'b' can be multi-bit.
Exp: a = 10, b = 11. 10<11 so a < b ; inferior = 1, superior = 0, equal = 0.
3. Methodology:
Consider the following VHDL program of a comparator of two two-bit numbers:
library ieee;
use ieee.std_logic_1164.all;
entity comp2bit is
port (a,b :in std_logic_vector(1 downto 0);
s,e,i :out std_logic);
end comp2bit ;
architecture rr of comp2bit is
Dr. A. Ganouche
begin
s <= (a(1) and not(b(1))) or (a(0) and not(b(0)) and
not(b(1))) or ( a(0) and a(1) and not(b(0)));
-- in this case ‘s’ is simplified using Karnaugh map
e <= ................................................
...............................................
............................. ;
i <= .................................................
...............................................
............................... ;
end rr;
1. Identify the inputs, the outputs, and their width.
Inputs Outputs
Name
a b s e i
Width
2 2 1 1 1
2. Complete the previous program with simple assignments.
NB: ‘i’ is the inverse of ‘s’.
3. Compile and simulate the program on ModelSim with different inputs and check
the truth table.
If you want to do all the combinations quickly:
right click on the input ‘a(0)’ → Clock → periode=10 →
right click on the input ‘a(1)’ → Clock → periode=20 →
right click on the input ‘b(0)’ → Clock → periode=40 →
right click on the input ‘b(1)’ → Clock → periode=80 → Simulate → Run 100
4. Complete the following architecture with conditional assignments in order to
achieve the same previous program.
architecture rr of comp2bit is
begin
s <= '1' when a > b else '0';
‘1’ when
e <= ... a = b else ‘0’
.......................;
Dr. A. Ganouche
i ...‘1’ when a < b else ‘0’
.......................
end rr;
5. Modify the program to make a comparator of two 4-bit numbers.
a = (a3 a2 a1 a0), and b = (b3 b2 b1 b0)
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6. Modify the program to make a comparator of two 4-bit numbers and the three
inputs for cascading.
s0, e0 et i0 are the result of another comparator which compare between two
numbers of higher weight (great significance).
a s : superior (a > b)
s0 e0 i0 Comparator e : equal (a = b)
b i : inferior (a < b)
In this case: the output 's' is worth 1 if and only if (s0=1) or (e0=1 and a>b)
The cascading of four comparator circuits is given by the following diagram:
b3 a3 b2 a2 b1 a1 b0 a0
s0 s0 s
0 s0 s0
e0 e
1 e0 Comp e0 Comp e0 Comp
i0
Comp
0 i0 i0 i0 i
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Dr. A. Ganouche