DEBRE TABOR UNIVRSITY

FACULTY OF TECHNOLOGY
Department of Electrical and Computer
Engineering
Digital Logic Design Module for 5th year ECE students
 DIGITAL LOGIC DESIGN MODULE FOR 5TH YEAR ECE STUDENTS

CHAPTER ONE
NUMBER SYSTEM
Number systems are the technique to represent numbers in the computer system architecture, every
value that you are saving or getting into/from computer memory has a defined number system.

Computer architecture supports following number systems.

• Binary number system

• Octal number system
• Decimal number system
• Hexadecimal (hex) number system BINARY

NUMBER SYSTEM

A Binary number system has only two digits that are 0 and 1. Every number (value) represents with
0 and 1 in this number system. The base of binary number system is 2, because it has only two digits.

OCTAL NUMBER SYSTEM

Octal number system has only eight (8) digits from 0 to 7. Every number (value) represents with
0,1,2,3,4,5,6 and 7 in this number system. The base of octal number system is 8, because it has only
8 digits.

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DECIMAL NUMBER SYSTEM

Decimal number system has only ten (10) digits from 0 to 9. Every number (value) represents with
0,1,2,3,4,5,6, 7,8 and 9 in this number system. The base of decimal number system is 10, because it
has only 10 digits.

HEXADECIMAL NUMBER SYSTEM

A Hexadecimal number system has sixteen (16) alphanumeric values from 0 to 9 and A to F. Every
number (value) represents with 0,1,2,3,4,5,6, 7,8,9,A,B,C,D,E and F in this number system. The base
of hexadecimal number system is 16, because it has 16 alphanumeric values. Here A is 10, B is 11,
C is 12, D is 14, E is 15 and F is 16.

Number system Base(Radix) Used digits Example

Binary 2 0,1 (11110000)2
Octal 8 0,1,2,3,4,5,6,7 (360)8
Decimal 10 0,1,2,3,4,5,6,7,8,9 (240)10
0,1,2,3,4,5,6,7,8,9,
Hexadecimal 16 (F0)16
A,B,C,D,E,F

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CONVERSIONS
DECIMAL TO OTHER
DECIMAL TO BINARY
Decimal Number System to Other Base
To convert Number system from Decimal Number System to Any Other Base is quite easy; you have to
follow just two steps:
A) Divide the Number (Decimal Number) by the base of target base system (in which you want to convert the
number: Binary (2), octal (8) and Hexadecimal (16)).
B) Write the remainder from step 1 as a Least Signification Bit (LSB) to Step last as a Most Significant Bit
(MSB).

Decimal to Binary Conversion Result

Decimal Number is : (12345)10

Binary Number is
(11000000111001)2

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DECIMAL TO OCTAL DECIMAL TO HEXADECIMAL

Decimal to Octal Conversion Result Decimal to Hexadecimal Result
Conversion
Decimal Number is : (12345)10 Example 1
Decimal Number is :
(12345)10
Octal Number is Hexadecimal Number is
(30071)8 (3039)16

Example 2
Decimal Number is : Hexadecimal Number is
(725)10 (2D5)16
Convert
10, 11, 12, 13, 14, 15
to its equivalent... A, B, C,
D, E, F

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BINARY TO OTHER
BINARY TO DECIMAL

Multiply the digit with 2(with place value exponent). Eventually add all the multiplication becomes the
Decimal number.

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1. BINARY TO OCTAL

An easy way to convert from binary to octal is to group binary digits into sets of three,
starting with the least significant (rightmost) digits.

Binary: 11100101 = 11 100 101

011 100 101 Pad the most significant digits with zeros if
necessary to complete a group of three.

Then, look up each group in a table:

Binary: 000 001 010 011 100 101 110 111
Octal: 0 1 2 3 4 5 6 7

Binary = 011 100 101

Octal = 3 4 5 = 345 oct

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BINARY TO HEXADECIMAL

An equally easy way to convert from binary to hexadecimal is to group binary digits into sets
of four, starting with the least significant (rightmost) digits.

Binary: 11100101 = 1110 0101

Then, look up each group in a table:

Binary: 0000 0001 0010 0011 0100 0101 0110 0111
Hexadecimal: 0 1 2 3 4 5 6 7

Binary: 1000 1001 1010 1011 1100 1101 1110 1111

Hexadecimal: 8 9 A B C D E F

Binary = 1110 0101

Hexadecimal = E 5 = E5 hex

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OCTAL TO OTHER
OCTAL TO BINARY
Converting from octal to binary is as easy as converting from binary to octal. Simply look
up each octal digit to obtain the equivalent group of three binary digits.

Octal: 0 1 2 3 4 5 6 7
Binary: 000 001 010 011 100 101 110 111

Octal = 3 4 5
Binary = 011 100 101 = 011100101 binary

OCTAL TO HEXADECIMAL
When converting from octal to hexadecimal, it is often easier to first convert the octal
number into binary and then from binary into hexadecimal. For example, to convert 345 octal
into hex:
Octal = 3 4 5

Binary = 011 100 101 = 011100101 binary

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Drop any leading zeros or pad with leading zeros to get groups of four binary digits
(bits): Binary 011100101 = 1110 0101

Then, look up the groups in a table to convert to hexadecimal digits.

Binary: 0000 0001 0010 0011 0100 0101 0110 0111

Hexadecimal: 0 1 2 3 4 5 6 7

Binary: 1000 1001 1010 1011 1100 1101 1110 1111

Hexadecimal: 8 9 A B C D E F

Binary = 1110 0101

Hexadecimal = E 5 = E5 hex

Therefore, through a two-step conversion process, octal 345 equals binary 011100101
equals hexadecimal E5.

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OCTAL TO DECIMAL

The conversion can also be performed in the conventional mathematical way, by showing
each digit place as an increasing power of 8.

345 octal = (3 * 82) + (4 * 81) + (5 * 80) = (3 * 64) + (4 * 8) + (5 * 1) = 229

decimal OR

Converting octal to decimal can be done with repeated division.

1. Start the decimal result at 0.

2. Remove the most significant octal digit (leftmost) and add it to the result.
3. If all octal digits have been removed, you’re done. Stop.
4. Otherwise, multiply the result by 8.
5. Go to step 2.

Octal Digits Operation Decimal Result Operation Decimal Result

345 +3 3 ×8 24
45 +4 28 ×8 224
5 +5 229 done.
 (345)8 =(229)10

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HEXADECIMAL TO OTHER
1. HEXADECIMAL TO BINARY

Converting from hexadecimal to binary is as easy as converting from binary to

hexadecimal. Simply look up each hexadecimal digit to obtain the equivalent group of four
binary digits.

Hexadecimal: 0 1 2 3 4 5 6 7
Binary: 0000 0001 0010 0011 0100 0101 0110 0111
Hexadecimal: 8 9 A B C D E F
Binary: 1000 1001 1010 1011 1100 1101 1110 1111

Hexadecimal = A 2 D E
Binary = 1010 0010 1101 1110 = 1010001011011110 binary

2. HEXADECIMAL TO OCTAL (try it)

1's complement
The 1's complement of a number is found by changing all 1's to 0's and all 0's to 1's. This is
called as taking complement or 1's complement. Example of 1's Complement is as follows.

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Binary Addition
It is a key for binary subtraction, multiplication, division. There are four rules of binary addition.

In fourth case, a binary addition is creating a sum of (1 + 1 = 10) i.e. 0 is written in the
given column and a carry of 1 over to the next column.
Example − Addition

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2's complement

The 2's complement of binary number is obtained by adding 1 to the Least Significant Bit
(LSB) of 1's complement of the number.

2's complement = 1's complement + 1

Example of 2's Complement is as follows.

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Rules of Binary Addition

• 0 + 0 = 0
• 0 + 1 = 1
• 1 + 0 = 1
• 1 + 1 = 0, and carry 1 to the next more significant bit

For example,

00011010 + 00001100 = 00100110 1 1 Carries

0 0 0 1 1 0 1 0 = 26(base 10)
+ 0 0 0 0 1 1 0 0 = 12(base 10)
0 0 1 0 0 1 1 0 = 38(base 10)

00010011 + 00111110 = 01010001 1 1 1 1 1 carries

0 0 0 1 0 0 1 1 = 19(base 10)
+ 0 0 1 1 1 1 1 0 = 62(base 10)
0 1 0 1 0 0 0 1 = 81(base 10)

Rules of Binary Multiplication

• 0 x 0 = 0
• 0 x 1 = 0
• 1 x 0 = 0
• 1 x 1 = 1, and no carry or borrow bits

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For example,

00101001 × 00000110 = 11110110 0 0 1 0 1 0 0 1 = 41(base 10)

× 0 0 0 0 0 1 1 0 = 6(base 10)
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1
0 0 1 0 1 0 0 1

0 0 1 1 1 1 0 1 1 0 = 246(base 10)

Types of Logic Gates

A logic gate is a digital gate that allows data to be transferred. Logic gates, use logic to determine whether or not
to pass a signal. Logic gates, on the other hand, govern the flow of information based on a set of rules. The
following types of logic gates are commonly used:

1. AND 5. NAND
2. OR 6. XOR
3. NOT 7. XNOR
4. NOR

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Basic Logic Gates

AND Gate
An AND gate has a single output and two or more inputs.

1. When all of the inputs are 1, the output of this gate is 1.

1. The AND gate’s Boolean logic is Y=A.B if there are two inputs A and B.
An AND gate’s symbol and truth table are as follows: Truth Table
Input Output
A B A AND B
0 0 0

0 1 0
Symbol of AND gate 1 0 0
1 1 1

Therefore, in And gate, the output is high when all the inputs are high.

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OR Gate
Two or more inputs and one output can be used in an OR gate.

1. The logic of this gate is that if at least one of the inputs is 1, the output will be 1.
2. The OR gate’s output will be given by the following mathematical procedure if there are two inputs A
and B: Y=A+B Truth Table
Input Output
A B A OR B

Symbol of OR gate 0 0 0

0 1 1

1 0 1
Therefore, in the OR gate, the output is high when any of the inputs is high.
1 1 1

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NOT Gate
The NOT gate is a basic one-input, one-output gate.

1. When the input is 1, the output is 0, and vice versa. A NOT gate is sometimes called an inverter because
of its feature.
2. If there is only one input A, the output may be calculated using the Boolean equation Y=A’.

Input Output
Symbol of NOT gate A Not A

0 1

A NOT gate, as its truth table shows, reverses the input signal. 1 0

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Universal Logic Gates

NOR Gate
A NOR gate, sometimes known as a “NOT-OR” gate, consists of an OR gate followed by a NOT gate.

1. This gate’s output is 1 only when all of its inputs are 0. Alternatively, when all of the inputs are low, the
output is high.
2. The Boolean statement for the NOR gate is Y=(A+B)’ if there are two inputs A and B.
Input Output
A B A NOR B

0 0 1

Symbol of NOR gate 0 1 0

1 0 0
By comparing the truth tables, we can observe that the outputs of the NOR gate are the
1 1 0
polar opposite of those of an OR gate. The NOR gate is sometimes known as a universal
gate since it may be used to implement the OR, AND, and NOT gates.

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NAND Gate
A NAND gate, sometimes known as a ‘NOT-AND’ gate, is essentially a Not gate followed by an AND gate.

1. This gate’s output is 1 only if none of the inputs is 1. Alternatively, when all of the inputs are not high
and at least one is low, the output is high.
2. If there are two inputs A and B, the Boolean expression for the NAND gate is Y=(A.B)’

Input Output
A B A NAND B

Symbol of NAND gate 0 0 1

0 1 1

1 0 1

1 1 0

By comparing their truth tables, we can observe that their outputs are the polar opposite of an AND gate. The
NAND gate is known as a universal gate because it may be used to implement the AND, OR, and NOT gates.

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Other Logic Gates

XOR Gate
The Exclusive-OR or ‘Ex-OR’ gate is a digital logic gate that accepts more than two inputs but only outputs one
value.

1. If any of the inputs is ‘High,’ the output of the XOR Gate is ‘High.’ If both inputs are ‘High,’ the output
is ‘Low.’ If both inputs are ‘Low,’ the output is ‘Low.’
2. The Boolean equation for the XOR gate is Y=A’.B+A.B’ if there are two inputs A and B.

Input Output
A B A XOR B

0 0 0

0 1 1
Symbol of XOR gate
1 0 1

1 1 0
Its outputs are based on OR gate logic, as we can see from the truth table.

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XNOR Gate
The Exclusive-NOR or ‘EX-NOR’ gate is a digital logic gate that accepts more than two inputs but only outputs
one.

1. If both inputs are ‘High,’ the output of the XNOR Gate is ‘High.’ If both inputs are ‘Low,’ the output is
‘High.’ If one of the inputs is ‘Low,’ the output is ‘Low.’
2. If there are two inputs A and B, then the XNOR gate’s Boolean equation is: Y=A.B+A’B’.

Input Output
A B A XNOR B

0 0 1

0 1 0
Symbol of XNOR gate
1 0 0
The truth table shows that its outputs are based on NOR gate logic.
1 1 1

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Uses of Logic Gates

1. Logic gates are utilized in a variety of technologies. These are components of chips (ICs), which are
components of computers, phones, laptops, and other electronic devices.
2. Logic gates may be combined in a variety of ways, and a million of these combinations are necessary to
make the newest gadgets, satellites, and even robots.
3. Simple logic gate combinations can also be found in burglar alarms, buzzers, switches, and street lights.
Because these gates can make a choice to start or stop based on logic, they are often used in a variety of
sectors.
4. Logic gates are also important in data transport, calculation, and data processing. Even transistor-
transistor logic and CMOS circuitry make extensive use of logic gates.

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Chapter Exercise
1. Convert the binary number 1001.0010 to decimal.
2. Explain in detail: a. The difference between 1’s and 2’s complement. b. The advantage of 2’s
complement over 1’s complement.
3. What is the procedure for converting a decimal number to 2's complement representation?
4. Represent ±165 decimal number using sing-magnitude and 2’s techniques with an appropriate bit size.
5. Convert the given Octal 7652 to an equivalent hexadecimal
6. Convert 8B3F to binary.
7. Which one is the proper odd parity bit to the code 111001: A. 1111011 B. 0111111 C. 1111001 D.
0011111 E. None
8. Convert the following binary number to octal: 010111100
9. Convert the given binary, 1100101000110101 to hexadecimal.
10. Generate a truth table and Boolean expression for a three-input AND and OR gate.
11. Implement the AND, OR,NOT , NOR, XOR and XNOR gates using the universal NANAD gate.

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CHAPTER TWO
BOOLEAN ALGEBRA
BOOLEAN OPERATIONS AND EXPRESSIONS

Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to
represent a logical quantity. Any single variable can have a 1 or a 0 value. The complement is the
inverse of a variable and is indicated by a bar over variable (overbar). For example, the complement
of the variable A is A. If A = 1, then A = 0. If A = 0, then A = 1. The complement of the variable A
is read as "not A" or "A bar." Sometimes a prime symbol rather than an overbar is used to denote the
complement of a variable; for example, B' indicates the complement of B. A literal is avariable or
the complement of a variable.
Boolean Addition
Recall from part 3 that Boolean addition is equivalent to the ORoperation. In Boolean algebra, a sum
term is a sum of literals. In logic circuits, a sum term is produced by an OR operation with no AND
operations involved. Some examples of sum terms are A + B, A + B, A + B + C, and A + B + C
+ D.
A sum term is equal to 1 when one or more of the literals in the term are 1. A sum term is equal to 0
only if each of the literals is 0.

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Boolean Multiplication
Also recall from part 3 that Boolean multiplication is equivalent to the AND operation. In Boolean
algebra, a product term is the product of literals. In logic circuits, a product term is produced by an
AND operation with no OR operations involved. Some examples of product terms are AB, AB,
ABC, and ABCD.
A product term is equal to 1 only if each of the literals in the term is 1. Aproduct term is equal
to 0 when one or more of the literals are 0.
Example
Determine the values of A, B, C, and D that make the product term ABCDequal to 1.

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LAWS AND RULES OF BOOLEAN ALGEBRA

■ Laws of Boolean Algebra
The basic laws of Boolean algebra-the commutative laws for addition and multiplication, the
associative laws for addition and multiplication, and the distributive law-are the same as in ordinary
algebra.
Commutative Laws
► The commutative law of addition for two variables is written asA+B = B+A
This law states that the order in which the variables are ORed makes no difference. Remember, in
Boolean algebra as applied to logic circuits, addition and the OR operation are the same. Fig.(4-1)
illustrates the commutative law as applied to the OR gate and shows that it doesn't matter to which
input each variable is applied. (The symbol ≡ means "equivalent to.").

Fig. Application of commutative law of addition.

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►The commutative law of multiplication for two variables is

A.B = B.A
This law states that the order in which the variables are ANDed makes no difference. Fig.(4-2),
il1ustrates this law as applied to the AND gate.

Fig. Application of commutative law of multiplication.

Associative Laws :
► The associative law of addition is written as follows for three variables: A + (B + C) = (A + B)
+C
This law states that when ORing more than two variables, the result is the same regardless of the
grouping of the variables. Fig.(4-3), illustrates thislaw as applied to 2-input OR gates.

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Fig. Application of associative law of addition.

► The associative law of multiplication is written as follows for threevariables:

A(BC) = (AB)C

This law states that it makes no difference in what order the variables are grouped when ANDing
more than two variables. Fig. below illustrates this law as applied to 2-input AND gates.

Fig.(4-4) Application of associative law of multiplication

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Distributive Law:
► The distributive law is written for three variables as follows:A(B + C) = AB + AC
This law states that ORing two or more variables and then ANDing the result with a single variable
is equivalent to ANDing the single variable with each of the two or more variables and then ORing
the products. The distributive law also expresses the process of factoring in which the common
variable A is factored out of the product terms, for example,
AB + AC = A(B + C).
Fig. below illustrates the distributive law in terms of gateimplementation.

Fig. Application of distributive law.

■ Rules of Boolean Algebra

Table 4-1 lists 12 basic rules that are useful in manipulating and simplifying Boolean expressions.
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Rules 1 through 9 will be viewed in terms of their application to logic gates. Rules 10 through 12
will be derived in terms ofthe simpler rules and the laws previously discussed.

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Rule 1. A+0=A
A variable ORed with 0 is always equal to the variable. If the input variable A is 1, the output variable
X is 1, which is equal to A. If A is 0, the output is 0, which is also equal to A. This rule is illustrated
in Fig.(4-6), where the lower input is fixed at 0.

Fig.(4-6)
Rule 2. A+1=1
A variable ORed with 1 is always equal to 1. A 1 on an input to an OR gate produces a 1 on the
output, regardless of the value of the variable on the other input. This rule is illustrated in Fig.(4-7),
where the lower input is fixedat 1.

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Fig.(4-7)
Rule 3. A.0=0
A variable ANDed with 0 is always equal to 0. Any time one input to an AND gate is 0, the output
is 0, regardless of the value of the variable on the other input. This rule is illustrated in Fig.(4-8),
where the lower input is fixedat 0.

Fig.(4-8)

Rule 4. A.1=A
A variable ANDed with 1 is always equal to the variable. If A is 0 the outputof the AND gate is 0. If

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A is 1, the output of the AND gate is 1 because both inputs are now 1s. This rule is shown in Fig.(4-
9), where the lower input is fixed at 1.
Rule 5. A+A=A
A variable ORed with itself is always equal to the variable. If A is 0, then 0
+ 0 = 0; and if A is 1, then 1 + 1 = 1. This is shown in Fig.(4-10), where bothinputs are the same
variable.

Rule 6. A+A=1
A variable ORed with its complement is always equal to 1. If A is 0, then 0 +0 = 0 + 1 = 1. If A is
l, then 1 + 1 = 1+ 0 = 1. See Fig.(4-11), where oneinput is the complement of the other.

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Rule 7. A.A=A
A variable ANDed with itself is always equal to the variable. If A = 0, then 0.0 = 0; and if A =
1. then 1.1 = 1. Fig.(4-12) illustrates this rule.

Rule 8. A.A=0
A variable ANDed with its complement is always equal to 0. Either A or Awill always be 0: and
when a 0 is applied to the input of an AND gate. the output will be 0 also. Fig.(4-13) illustrates this
rule.

Rule 9 A=A
The double complement of a variable is always equal to the variable. If you start with the variable A
and complement (invert) it once, you get A. If you then take A and complement (invert) it, you get
A, which is the original variable. This rule is shown in Fig.(4-14) using inverters.

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Rule 10. A + AB = A
This rule can be proved by applying the distributive law, rule 2, and rule 4 asfollows:
A + AB = A( 1 + B) Factoring (distributive law)
=A.l Rule 2: (1 + B) = 1
=A Rule 4: A . 1 = A

The proof is shown in Table 4-2, which shows the truth table and theresulting logic circuit
simplification.

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Rule 11. A + AB = A + B
This rule can be proved as follows:
A + AB = (A + AB) + AB Rule 10: A = A + AB
= (AA + AB) + AB Rule 7: A = AA
=AA +AB +AA +AB Rule 8: adding AA = 0
= (A + A)(A + B) Factoring
= 1. (A + B) Rule 6: A + A = 1
=A + B Rule 4: drop the 1
The proof is shown in Table 4-3, which shows the truth table and theresulting logic circuit
simplification.

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Table 4-3

Rule 12. (A + B)(A + C) = A + BC

This rule can be proved as follows:
(A + B)(A + C) = AA + AC + AB + BC Distributive law
= A + AC + AB + BC Rule 7: AA = A
= A( 1 + C) + AB + BC Rule 2: 1 + C = 1
= A. 1 + AB + BC Factoring (distributive law)
= A(1 + B) + BC Rule 2: 1 + B = 1
= A. 1 + BC Rule 4: A . 1 = A
= A + BC

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The proof is shown in Table 4-4, which shows the truth table and theresulting logic circuit
simplification.

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DEMORGAN'S THEOREMS

DeMorgan, a mathematician who knew Boole, proposed two theorems that are an important part of
Boolean algebra. In practical terms. DeMorgan's theorems provide mathematical verification of the
equivalency of the NANDand negative-OR gates and the equivalency of the NOR and negative-AND
gates, which were discussed in part 3.
One of DeMorgan's theorems is stated as follows:
The complement of a product of variables is equal to the sum of thecomplements of the
variables,
Stated another way,
The complement of two or more ANDed variables is equivalent to the OR of the complements of
the individual variables.
The formula for expressing this theorem for two variables isXY = X + Y
DeMorgan's second theorem is stated as follows:
The complement of a sum of variables is equal to the product of thecomplements of the variables.
Stated another way,

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The complement of two or more ORed variables is equivalent to the ANDof the complements of
the individual variables,
The formula for expressing this theorem for two variables is X + Y = X Y
Fig. shows the gate equivalencies and truth tables for the twoequations above.

Fig.(4-15) Gate equivalencies and the corresponding truth tables that illustrate DeMorgan's theorems.

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As stated, DeMorgan's theorems also apply to expressions in which there are more than two variables.
The following examples illustrate the application of DeMorgan's theorems to 3-variable and 4-
variable expressions.
Applying DeMorgan's Theorems
The following procedure illustrates the application of DeMorgan's theoremsand Boolean algebra
to the specific expression

Example
The Boolean expression for an exclusive-OR gate is AB + AB. With this as a starting point, use
DeMorgan's theorems and any other rules or laws that are applicable to develop an expression for the
exclusive-NOR gate.
BOOLEAN ANALYSIS OF LOGIC CIRCUITS
Boolean algebra provides a concise way to express the operation of a logic circuit formed by a
combination of logic gates so that the output can be determined for various combinations of input
values.

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Boolean Expression for a Logic Circuit

To derive the Boolean expression for a given logic circuit, begin at the left- most inputs and work
toward the final output, writing the expression for each gate. For the example circuit in Fig.(4-16),
the Boolean expression is determined as follows:
• The expression for the left-most AND gate with inputs C and D is CD.
• The output of the left-most AND gate is one of the inputs to the OR gate and B is the other
input. Therefore, the expression for the ORgate is B + CD.
• The output of the OR gate is one of the inputs to the right-most AND gate and A is the other
input. Therefore, the expression for this AND gate is A(B + CD), which is the final output
expression for the entire circuit.

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Fig. A logic circuit showing the development of the Booleanexpression for the output.
Constructing a Truth Table for a Logic Circuit
Once the Boolean expression for a given logic circuit has been determined, a truth table that shows
the output for all possible values of the input variables can be developed. The procedure requires that
you evaluate the Boolean expression for all possible combinations of values for the input variables.
In the case of the circuit in Fig.(4-16), there are four input variables (A, B, C, and D) and therefore
sixteen (24 = 16) combinations of values are possible.
Putting the Results in Truth Table format
The first step is to list the sixteen input variable combinations of 1sand 0s in a binary sequence as
shown in Table 4-5. Next, place a 1 in the output column for each combination of input variables
that was determined in the evaluation. Finally, place a 0 in the output column for all other
combinations of input variables. These results are shown in the truth table below

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SIMPLIFICATION USING BOOLEAN ALGEBRA

A simplified Boolean expression uses the fewest gates possible toimplement a given expression.
Example
Using Boolean algebra techniques, simplify this expression:AB + A(B + C) + B(B + C)

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Solution
Step 1: Apply the distributive law to the second and third terms in theexpression, as follows:
AB + AB + AC + BB + BC
Step 2: Apply rule 7 (BB = B) to the fourth term.
AB + AB + AC + B + BC
Step 3: Apply rule 5 (AB + AB = AB) to the first two terms.
AB + AC + B + BC
Step 4: Apply rule 10 (B + BC = B) to the last two terms.
AB + AC + B
Step 5: Apply rule 10 (AB + B = B) to the first and third terms.
B+AC

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At this point the expression is simplified as much as possible.

Fig. Gate circuits for example above.

Exercise Simplify the Boolean expressions:1- AB + A(B + C) + B(B + C).

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Standard and Canonical Forms

STANDARD FORMS OF BOOLEAN EXPRESSIONS
All Boolean expressions, regardless of their form, can be converted into either of two standard forms:
the sum-of-products form or the product-of- sums form. Standardization makes the evaluation,
simplification, and implementation of Boolean expressions much more systematic and easier.
The Sum-of-Products (SOP) Form
When two or more product terms are summed by Boolean addition,the resulting
expression is a sum-of-products (SOP). Some examples are:
AB + ABC
ABC + CDE + BCDAB + BCD + AC
Also, an SOP expression can contain a single-variable term, as inA + ABC + BCD.
In an SOP expression a single overbar cannot extend over more than one variable.
Example
Convert each of the following Boolean expressions to SOP form:
(a) AB + B(CD + EF)

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(b) (A + B)(B + C + D)

(c) (A + B) + C

Fig. Implementation of the SOP expression AB + BCD + AC.

Fig. This NAND/NAND implementation is equivalentto the AND/OR in figure above.

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The Standard SOP Form

So far, you have seen SOP expressions in which some of the product terms do not contain all of the
variables in the domain of the expression. For example, the expression ABC + ABD + ABCD has a
domain made up of the variables A, B, C. and D. However, notice that the complete set of variables
in the domain is not represented in the first two terms of the expression; that is, D or D is missing
from the first term and C or C is missing from the second term.
Converting Product Terms to Standard SOP:
Each product term in an SOP expression that does not contain all the variables in the domain can be
expanded to standard SOP to include all variables in the domain and their complements. As stated in
the following steps, a nonstandard SOP expression is converted into standard form using Boolean
algebra rule 6 (A + A = 1) from Table 4-1: A variable added to its complement equals 1.
Step 1. Multiply each nonstandard product term by a term made up of the sum of a missing variable
and its complement. This results in two product terms. As you know, you can multiply anything by
1 without changing its value.
Step 2. Repeat Step 1 until all resulting product terms contain all variables in the domain in either
complemented or uncomplemented form. In converting a product term to standard form, the number

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of product terms is doubled for each missing variable.

shows for the expression (A + B)(B + C + D)(A + C). The output X ofthe AND gate equals the
POS expression.

The Standard POS Form

So far, you have seen POS expressions in which some of the sum terms do not contain all of the
variables in the domain of the expression. For example,the expression
(A + B + C) (A + B + D) (A + B + C + D)
has a domain made up of the variables A, B, C, and D. Notice that the complete set of variables in
the domain is not represented in e first two termsof the expression; that is, D or D is missing from the
first term and C or C is missing from the second term.
A standard POS expression is one in which all the variables in the domain appear in each sum term
in the expression. For example,
(A + B + C + D)(A + B + C + D)(A + B + C + D)

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is a standard POS expression. Any nonstandard POS expression (referred to simply as POS) can be
converted to the standard form using Boolean algebra.
Converting a Sum Term to Standard POS
Each sum term in a POS expression that does not contain all the variables in the domain can be
expanded to standard form to include all variables in the domain and their complements. As stated
in the following steps, a

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GG nonstandard POS expression is converted into standard form using Boolean algebra rule 8 (A A
= 0) from Table 4-1:
Step 1. Add to each nonstandard product term a term made up of the product of the missing variable
and its complement. This results in two sum terms. As you know, you can add 0 to anything without
changing its value.
Step 2. Apply rule 12 from Table 4-1: A + BC = (A + B)(A + C)
Step 3. Repeat Step 1 until all resulting sum terms contain all variables in the domain in either
complemented or noncomplemented form.
B + C + D = B + C + D + AA = (A + B + C + D)(A + B + C + D)
The third term, A + B + C + D, is already in standard form. The standard POS form of the original
expression is as follows:

(A + B + C)(B + C + D)(A + B + C + D) = (A + B + C + D)(A + B + C +D) (A + B + C + D)(A +

B + C + D) (A + B + C + D)

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Exercise

CANONICAL FORMS OF BOOLEAN EXPRESSIONS

With one variable x & x.

With two variables x y, x y, x y and x y.
With three variables x y z, x y z, x y z, x y z, x y z, x y z, x y z & x y z.These eight AND
terms are called minterms.
n variables can be combined to form 2n minterms.

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x y z minterm designation maxterm designation

0 0 0 xyz m0 x+y+z M0
0 0 1 xyz m1 x+y+z M1
0 1 0 xyz m2 x+y+z M2
0 1 1 xyz m3 x+y+z M3
1 0 0 xyz m4 x+y+z M4
1 0 1 xyz m5 x+y+z M5
1 1 0 xyz m6 x+y+z M6
1 1 1 xyz m7 x+y+z M7
(AND terms) (OR terms)
Note that each maxterm is the complement of its corresponding minterm and vice versa.

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For example the function F

x y z F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

F = m1 + m4 + m7

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Example
Express the Boolean function F = A + BC’ in a sum of minterms (SOP).
Solution
The term A is missing two variables because the domain of F is

(A, B, C)A = A(B + B) = AB + AB because B + B = 1

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BC missing A, so
BC(A + A) = ABC + ABCAB(C + C) = ABC +
ABCAB(C + C) = ABC + ABC
F = ABC + ABC + ABC + ABC + ABC + ABC
Because A + A = A
F = ABC + ABC + ABC + ABC + ABC
F = m7 + m6 + m5 + m4 + m1

In short notation
F(A, B, C) = ∑(1, 4, 5, 6, 7)
F(A, B, C) = ∑(0, 2, 3)

The complement of a function expressed as the sum of minterms equalto the sum of
minterms missing from the original function.

Truth table for F = A + BC’

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A B C B BC F
0 0 0 0 1 0 0
1 0 0 1 1 1 1
2 0 1 0 0 0 0
3 0 1 1 0 0 0
4 1 0 0 1 0 1
5 1 0 1 1 1 1
6 1 1 0 0 0 1
7 1 1 1 0 0 1

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Example
Express F = xy + xz in a product of maxterms form.Solution
F = xy + xz = (xy + x)(xy + z) = (x + x)(y + x)(x + z)(y + z)remember x + x = 1
F = (y + x)(x + z)(y + z)
F = (x + y + zz)(x + yy + z )(xx + y + z)
F = (x + y + z)(x + y + z)(x + y + z)(x + y + z)(x + y +z)(x + y + z)
========== ------------------ ---------------- ==========

F = (x + y + z)(x + y + z)(x + y + z)(x + y + z) F = M4 M5 M0 M2

F(x, y, z) = ∏(0, 2, 4, 5)
F(x, y, z) = ∏(1, 3, 6, 7)

The complement of a function expressed as the product of maxtermsequal to the product

of maxterms missing from the original function.
To convert from one canonical form to another, interchange the symbols ∑, ∏ and list those numbers
missing from the original form.
F = M4 M5 M0 M2 = m1 + m3 + m6 + m7F(x, y, z) = ∏(0, 2, 4,5)
= ∑(1, 3, 6, 7)

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Example
Develop a truth table for the standard SOP expression ABC + ABC + ABC.

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Converting POS Expressions to Truth Table Format

Reca11 that a POS expression is equal to 0 only if at least one of the sum terms is equal to 0. To
construct a truth table from a POS expression, list all the possible combinations of binary values of
the variables just as was done for the SOP expression. Next, convert the POS expression to standard
form if it is not already. Finally, place a 0 in the output column (X) for each binary value that makes
the expression a 0 and place a 1 for all the remaining binary values. This procedure is illustrated in
Example below:
Exercise
Determine the truth table for the following standard POS expression:

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5 KARNAUGH MAP MINIMIZATION

A Karnaugh map provides a systematic method for simplifying Boolean expressions and, if properly
used, will produce the simplest SOP or POS expression possible, known as the minimum expression.
As you have seen, the effectiveness of algebraic simplification depends on your familiarity with all the
laws, rules, and theorems of Boolean algebra and on your ability to apply them. The Karnaugh map,
on the other hand, provides a "cookbook" method for simplification.
A Karnaugh map is similar to a truth table because it presents all of the possible values of input
variables and the resulting output for each value. Instead of being organized into columns and rows
like a truth table, the Karnaugh map is an array of cells in which each cell represents a binary value
of the input variables. The cells are arranged in a way so that simplification of a given expression is
simply a matter of properly grouping the cells. Karnaugh maps can be used for expressions with two,
three, four. and five variables. Another method, called the Quine-McClusky method can be used for
higher numbers of variables.
The number of cells in a Karnaugh map is equal to the total number of
possible input variable combinations as is the number of rows in a truth table. For three variables,

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the number of cells is 23 = 8. For four variables,the number of cells is 24 = 16.

The 3-Variable Karnaugh Map
The 3-variable Karnaugh map is an array of eight cells. as shown in Fig. In this case, A, B, and C are
used for the variables although other letters could be used. Binary values of A and B are along the
left side (notice the sequence) and the values of C are across the top. The value of a givencell is
the binary values of A and B at the left in the same row combinedwith the value of C at the top in
the same column. For example, the cell in the upper left corner has a binary value of 000 and the cell
in the lower right corner has a binary value of 101. Fig. below shows the standard product terms that
are represented by each cell in the Karnaugh map.

Fig.A 3-variable Karnaugh map showing product terms.

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The 4-Variable Karnaugh Map

The 4-variable Karnaugh map is an array of sixteen cells, as shown in Fig. Binary values of A and B are
along the left side and the valuesof C and D are across the top. The value of a given cell is the binary
valuesof A and B at the left in the same row combined with the binary values of C and D at the top in the
same column. For example, the cell in the upper right corner has a binary value of 0010 and the cell in the
lower right corner has a binary value of 1010. Fig.(b) shows the standard product terms that arerepresented
by each cell in the 4-variable Karnaugh map.

(a) (b)
Fig. A 4-variable Karnaugh map.

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Cell Adjacency
The cells in a Karnaugh map are arranged so that there is only a single- variable change between
adjacent cells. Adjacency is defined by a single- variable change. In the 3-variable map the 010 cell
is adjacent to the 000 cell, the 011 cell, and the 110 cell. The 010 cell is not adjacent to the 001 cell,
the 111 cell, the 100 cell, or the 101 cell.

Fig. Adjacent cells on a Karnaugh map are those that differ by only one variable. Arrows point between adjacent cells.

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KARNAUGH MAP SOP MINIMIZATION

For an SOP expression in standard form, a 1 is placed on the Karnaugh map for each product term in
the expression. Each 1 is placed in a cell corresponding to the value of a product term. For example,
for the product term ABC, a 1 goes in the 10l cell on a 3-variable map.
Example
Map the following standard SOP expression on a Karnaugh map:
Example
Map the following standard SOP expression on a Karnaugh map:

(B)
(A)

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Example

Map the following SOP expression on a Karnaugh map:

Solution
The SOP expression is obviously not in standard form because each productterm does not have three
variables. The first term is missing two variables, the second term is missing one variable, and the
third term is standard. Firstexpand the terms numerically as follows:

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Example
Map the following SOP expression on a Karnaugh map:

Solution
The SOP expression is obviously not in standard form because each productterm does not have four
variables.

Map each of the resulting binary values by placing a 1 in the appropriate cellof the 4- variable
Karnaugh map.

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Karnaugh Map Simplification of SOP Expressions

Grouping the 1s, you can group 1s on the Karnaugh map according to the following rules by enclosing
those adjacent cells containing 1s. The goal is to maximize the size of the
groups and to minimize the number of groups.
• A group must contain either 1, 2, 4, 8, or 16 cells, which are all powers of two. In the case of
a 3-variable map, 23 = 8 cells is the maximum group.
• Each cell in a group must be adjacent to one or more cells in that same group.
• Always include the largest possible number of 1s in a group in accordance with rule 1.
• Each 1 on the map must be included in at least one group. The 1s already in a group can be
included in another group as long as the overlapping groups include noncommon 1s.

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Example:
Group the 1s in each of the Karnaugh maps in Fig below.

Fig.
Solution:
The groupings are shown in Fig.(5-7). In some cases, there may be morethan one way to group the
1s to form maximum groupings.

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Determine the minimum product term for each group.

a. For a 3-variable map:
(1) A l-cell group yields a 3-variable product term
(2) A 2-cell group yields a 2-variable product term
(3) A 4-cell group yields a 1-variable term
(4) An 8-cell group yields a value of 1 for the expression
b. For a 4-variable map:
(1) A 1-cell group yields a 4-variable product term
(2) A 2-cell group yields a 3-variable product term

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(3) A 4-cell group yields a 2-variable product term

(4) An 8-cell group yields a 1-variable term
(5) A 16-cell group yields a value of 1 for the expression
Example:
Determine the product terms for each of the Karnaugh maps in Fig.(5-7) andwrite the resulting
minimum SOP expression.

Fig.(5-8)

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Example: Use a Karnaugh map to minimize the following SOP expression:

"Don't Care" Conditions

Sometimes a situation arises in which some input variable combinations are not allowed. For example,
recall that in the BCD code there are six invalid combinations: 1010, 1011, 1100, 1101, 1110, and
1111. Since these unallowed states will never occur in an application involving the BCD code, they
can be treated as "don't care" terms with respect to their effect on the output. That is, for these "don't
care" terms either a 1 or a 0 may be assigned to the output: it really does not matter since they will
never occur.
The "don't care" terms can be used to advantage on the Karnaugh map. Fig.(5-9) shows that for each
"don't care" term, an X is placed in the cell. When grouping the 1 s, the Xs can be treated as 1s to make
a larger grouping or as 0s if they cannot be used to advantage. The larger a group, the simpler the
resulting term will be.

The truth table in Fig.(5-9)(a) describes a logic function that has a 1 output only when the BCD code for
7,8, or 9 is present on the inputs. If the "don't cares" are used as 1s, the resulting expression for the

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function is A + BCD, as indicated in part (b). If the "don't cares" are not used as 1s, the resulting
expression is ABC + ABCD: so you can see the advantage of using "don'tcare" terms to get the simplest
expression.

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KARNAUGH MAP POS MINIMIZATION

In this section, we will focus on POS expressions. The approaches are much the same except that with
POS expressions, 0s representing the standard sum terms are placed on the Karnaugh map instead of
1s.
For a POS expression in standard form, a 0 is placed on the Karnaugh map for each sum term in the
expression. Each 0 is placed in a cell corresponding to the value of a sum term. For example, for the
sum term A + B + C, a 0goes in the 0 1 0 cell on a 3-variable map.
When a POS expression is completely mapped, there will be a number of 0s on the Karnaugh map
equal to the number of sum terms in the standard POS expression. The cells that do not have a 0 are
the cells for which the expression is 1. Usually, when working with POS expressions, the 1s are left
off. The following steps and the illustration in Fig.(5-10) show the mapping process.
Step 1. Determine the binary value of each sum term in the standard POS expression. This is the binary
value that makes the term equal to 0.
Step 2. As each sum term is evaluated, place a 0 on the Karnaugh map in the corresponding cell.

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Fig.(5-10) Example of mapping a standard POS expression.

Example:
Map the following standard POS expression on a Karnaugh map:

Solution:

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Karnaugh Map Simplification of POS Expressions

The process for minimizing a POS expression is basically the same as for an SOP expression except
that you group 0s to produce minimum sum terms instead of grouping 1s to produce minimum product
terms. The rules for grouping the 0s are the same as those for grouping the 1s that you learned before.
Example:
Use a Karnaugh map to minimize the following standard POS expression:Also, derive the
equivalent SOP expression.

Solution:

Example: Use a Karnaugh map to minimize the following POS expression:

Example: Using a Karnaugh map, convert the following standard POS expression into a minimum POS expression, a
standard SOP expression, and a minimum SOP expression.

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FIVE-VARIABLE KARNAUGH MAPS

Boolean functions with five variables can be simplified using a 32-cell Karnaugh map. Actually, two 4-
variable maps (16 cells each) are used to construct a 5-variable map. You already know the cell adjacencies
within each of the 4- variable maps and how to form groups of cells containing 1s to simplify an SOP
expression. All you need to learn for five variables is the cell adjacencies between the two 4-variable maps
and how to group those adjacent 1s.
A Karnaugh map for five variables (ABCDE) can be constructed using two 4-variable maps with which
you are already familiar. Each map contains 16 cells with all combinations of variables B, C, D, and E. One
map is for A = 0 and the other is for A = 1, as shown in Fig.(5-11).
Cell Adjacencies
You already know how to determine adjacent cells within the 4-variablemap. The best way to visualize
cell adjacencies between the two 16-cel1 maps is to imagine that the A = 0 map is placed on top of the A
= 1 map. Each cell in the A = 0 map is adjacent to the cell directly below it in the A =1 map, see Fig.(5-
12).

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Example:
Use a Karnaugh map to minimize the following standard SOP 5-variableexpression:

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Chapter Exercise
1. Generate a truth table for the following min and max terms of the Boolean functions.

A. f(A,B,C,D) = ∑ m(1,3,5,7,9,11,13,15) B. f(A,B,C,D) = ∏ M(0,2,4,6,8,10,12,14,16, ,18,20,22,24,26,28,30)

2. Find the minimal SOP form for:

A. f(A,B,C,D) = ∑ m(0,1,2,3,7,8,10,13) B. f(A,B,C,D,E) = ∑ m(0,2,4,7,10,12,13,18,23,26,28,29)

3. Find minimal POS expression for:

A. f(A,B,C,D) = ∏ M(1,3,5,7,9,11,13,15) B. f(A,B,C,D,E) = ∏ M(0,2,4,6,8,10,12,14,16, ,18,20,22,24,26, ,28,30)

4. Minimize the function in SOP & POS forms using K-map and plot the logic diagram for both the given Boolean function and the

simplified expressions

a. F(A,B,C,D) = ∑ m(1,3,4,7,11) + d(5,12,13,14,15) b. F(A,B,C,D) = ∏ M(0,2,6,8,9,10) * d(5,12,13,14,15)

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CHAPTER THREE
Combinational Logic Circuits
INTRODUCTION
In digital circuit theory, sequential logic is a typeof logic circuit whose output depends not only on the present
value of its input signals but on the sequence of past inputs, the input history as well. This is in contrast to
combinational.

A combinational logic circuit performs an operation assigned logically by a Boolean expression or truth table.
Examples of common combinational logic circuits include: half adders, full adders, multiplexers,
demultiplexers, encoders and decoders

Half adder
An adder is a digital circuit that performs addition of numbers. Half adder has only two
inputs and two outputs. The half adder adds two binary digits called as augend and addend and
produces two outputs as sum and carry; XOR is applied to both inputs to produce sum and AND
gateis applied to both inputs to produce carry.
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• By using half adder, you can design simple addition with the help of logic gates.

Circuit Implementation Block Diagram

Truth Table

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Why it is called as Half-adder?

The half adder can add only two input bits (A and B) and has nothing to do with the carry if there
is any in the input. So if the input to a half adder have a carry, then it will neglect it and adds only
the A and B bits. That means the binary addition process is not complete and that's why itis
called a half adder

How Half Adder works?

Half adder is a simple combinational circuit used to add two single bits. It accepts two inputs and
produce two outputs that is a sum output and a carry output. A half adder consists of two logic
gates 1) XOR and 2) AND gate. And the carry operation performed by AND gate thus carry out
put will be A+B.

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FULL ADDER
The full adder adds 3 one bit numbers, where two can be referred to as operands and one
can be referred to as bit carried in. Itproduces 2-bit output and these can be referred to as
output carry and sum.
The full-adder has three inputs and two outputs. The first two inputs are A and B and the
third input is an input carry as C-IN. When a full-adder logic is designed, you string eight of
them together to create a byte-wide adder and cascade the carry bit from one adder to the
next.
Truth Table

Block Diagram

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Logic diagram

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With the truth-table, the full adder logic can be implemented. You can see that the output S is
an XOR between the input A and the half-adder, SUM output with B and C-IN inputs. We take
C-OUT will only be true if any of the two inputs out of the three are HIGH.

So, we can implement a full adder circuit with the help of two half addercircuits. At first, half
adder will be used to add A and B to produce a partial Sum and a second half adder logic can
be used to add C-IN to the Sum produced by the first half adder to get the final S output. If any
of the half adder logic produces a carry, there will be an output carry. So, C-OUT will be
an OR function of the half-adder Carry outputs.

The implementation of larger logic diagrams is possible with the above full adder logic a
simpler symbol is mostly used to represent the operation.Given below is a simpler schematic
representation of a full adder.

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• A full adder is a digital circuit that performs addition. Full

adders are implemented with logic gates in hardware.
A full adder adds three one-bit binary numbers, two operands and a carry bit. The
adder outputs two numbers,a sum and a carry bit.
• The Boolean expression for a full adder is as follows.
• For the CARRY-OUT (Cout) bit: CARRY-OUT = A AND B ORCin(A XOR B) =
A.B + Cin(A ⊕ B)

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4-Bit Parallel Binary adder :

• A binary parallel adder is a digital function that producesthe arithmetic sum of two binary numbers
in parallel.

• FOUR-BIT BINARY PARALLEL ADDER is a circuit in whichtwo binary numbers each of n bits
can be added by means of a full adder circuit. Consider the example that two 4-bit
binary numbers B 4B 3B 2B 1 and A 4A 3A 2A 1 are to be added with a carry input C1.

• A group of four bits is called a nibble. A basic 4-bit parallel adder is implemented with four full-adder
stages as shown in Figure.

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Again, the LSBs (A1 and B1) in each number being added go into the right- most full-adder: the higher-order
bits are applied as shown to the successively higher-order adders, with the MSBs (A4 and B4) in each number
being applied to the left-most full-adder. The carry output of each adder is connected to the carry input of the
next higher-order adder as indicated. These are called internal carries. In keeping with most manufacturers' data
sheets, the input labeled C, is the input carry to the least significant bit adder; C4 in the case of four bits, is the
output carry of the most significant bit adder; and ∑1 (LSB) through ∑4 (MSB) are the sum outputs. The logic
symbol for 4-bit parallel adder is shown in Figure.

Two binary numbers each of n bits can be added by means of a full adder circuit. Consider the example that
two 4-bit binary numbers B 4B 3B 2B 1 and A4 A 3A 2A 1 are to be added with a carry input C 1. This can

be done by cascading four full adder circuits as shown in figure. The least significant bitsA 1, B 1, and C 1

are added to the produce sum output S 1 and carry output C 2. Carry output C 2 is then added to the next

significant bits A 2 and B 2 producing sum output S 2 and carry output C 3. C 3 is then added to A 3 and B 3 and
so on. Thus finally producing the four-bit sum output S 4S 3S 2S 1 and final carry output Cout. Such type of

four-bit binary adder is commercially available in an IC package.

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Half Subtractor:
A half subtractor is an arithmetic circuit that subtracts two bits and produces their difference. The
circuit has two inputs minuend (X) and subtrahend (Y) and two output bits, one is the difference
bit (D) and the other is the borrow bit (B).

As like addition operation of 2 binary digits, which produces SUM and CARRY, the subtraction
of 2 binary digits also produces two outputs which are termed as difference and borrow. The
simplest possible subtraction of 2-bit binary digits consists of four possible operations, they are
0-0, 0-1, 1-0 and 1-1. The operations 0-0, 1-0 and 1-1 produces a subtraction of 1-bit output
whereas, the remaining operation 0-1 produces a 2-bit output. They are referred as
difference and borrow bit respectively. This borrow bit is used for subtraction of the next higher
pair bit. So, we can define half subtractor as a combinational circuit which is capable of performing
subtraction of 2-bit binary digits is known as a half subtractor. Here, the binary digit from which
the other digit is subtracted is called minuend and the binary digit which is to be subtracted is

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known as the subtrahend.

• It performs the operation X – Y. It should be noted that the weight of the output borrow bit is
-2, while the weight of the output difference bit is +1.
The truth table of the half subtractor is shown. The Boolean functions for the two outputs can
be obtained directly from the truth table as:
D = (XY + XY) = X ⊕Y

• The half subtractor Boolean expressions are :

D = (X’Y + XY’) = X ⊕ Y
B = X’Y

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Full Substractor
A full subtractor is a combinational circuit that performs a subtraction between two bits, taking
into account that a 1 may have been borrowedby a lower significant bit. The circuit has three inputs
and two outputs.

Input variables are minuend (X), subtrahend (Y), and previous borrow (Z); output variables are
difference (D) and output borrow (B).

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It performs the operation X – Y – Z. It should be noted that the weight of the output borrow bit is
-2, while the weight of the output differencebit is +1. The truth table of the full subtractor is shown.

The full subtractor Boolean expressions are:

(X’Y’Z + X’YZ’ + XY’Z’ + XYZ) = X ⊕ Y ⊕ Z
(X’Y’Z + X’YZ’ + X’YZ + XYZ) = X'(Y ⊕ Z) + YZ

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When there is a situation where the minuend and subtrahend number contains more significant bit, then the
borrow bit which is obtained from the subtraction of 2-bit binary digits is subtracted from the next higher order
pair of bits. In such situation, the subtraction involves the operation of 3 bits. Such situation of subtraction can’t
handle by asimple half subtractor. So, combining two half subtractor we can form another combinational circuit
which can perform this type of operation. This circuit is known as the full subtractor.

So we can define full subtractor as a combinational circuit which takes three inputs and produces two outputs
difference and borrow. Aboveis the truth table of the full subtractor, we have used three input variables X, Y
and Z which refers to the term minuend, subtrahend and borrow bit respectively. The two
outputs difference and borrow are named as D and B respectively.

The construction of full subtractor circuit diagram involves two half subtractor joined by an OR gate as shown
in the above circuit diagram of the full subtractor. The two borrow bits generated by two separate half
subtractor are fed to the OR gate which produces the final borrow bit. The final difference bit is the combination
of the difference output of the first half adder and the next higher order pair of bits.

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Multiplexers and Demultiplexers

There are many applications where many devices or system needs to access a common transmission media.
Let us consider our cable TV system, in which multiple TV channels are received at home via a shared
transmission media. Similarly, in computer networking, many computer needs to access a common printer
or other shared hardware. In Smart instrumentation, a PC or microcontroller can acquire data gathered from
many sensors through a single ADC. Our telephone exchanges utilize these multiplexers and
demultiplexers extensively Multiplexer and demultiplexers are normally used for sharing resources.
Multiplexers routes the data from many sources to one destination and demultiplexer redistributes data
back from one source to many destinations.

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In this module you will learn about the basic architecture of multiplexer and demultiplexers along with real
life applications.

Multiplexer

Multiplexer means many to one. A multiplexer (MUX) is a combinational circuit which is often used when the
information from many sources must be transmitted over long distances and it is less expensive to multiplex
data onto a single wire for transmission. Multiplexer can be considered as multi-position or rotary switch as
shown in fig. 2. There are n – inputs and one output. The switch position is controlled by the selector lines. The
select inputs decide which input is connected to the output.

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A multiplexer can be considered as semiconductor equivalent of multi-position switch. It is combinational logic

circuit which has many input lines and a single output line. The basic operation is controlled by a selector lines that
routes one of many input signals to the output. Fig.3 shows the logic symbol of general symbol of multiplexer.

Multiplexer are also called as DATA Selector or router because it accepts several data inputs and allows only one
of them to get through to the output at a time. The basic multiplexer has n input lines and single output line. It also
has m – select or control lines. The relation between number of select lines and number of data inputs are
2m = n. As multiplexer selects one out of many, it is often called as 2m to 1 line converter.
Applications of multiplexers
Multiplexer or data selectors are combinational circuits which transfer data from many sources to output under the
control of data select lines. Multiplexer has many applications right from data routing, time division multiplexing,

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function generator to parallel to serial converter etc. A single multiplexer can replace several logic gates ICs,
saving PCB area, interconnections, design efforts and cost. A list of popular applications is given below.
1. Data routing 5. Parallel to serial converter
2. Data bussing 6. Cable TV signal distribution
3. Switch setting comparator 7. Telephone network
4. Multiplexer as a function generator 8. Sharing printer /resources

Demultiplexer
Demultiplexer has a single input and n output lines. Demultiplexer can be visualized as reverse multi-position
switch. The select lines permit input data from single line to be switched to any one of the many output lines as
shown in fig. below.

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Applications of Demultiplexers

Digital demultiplexers are combinational devices controlled by a selector address that routes input data to one of
many outputs of the demultiplexers. These can be used in following applications.

1.Data demultiplexing 4.Four phase clock generator

2.Clock demultiplexing 5.Function generation using DMUX

6.Switch encoding
3.Memory addressing
7.Serial to parallel converter
Encoder
An encoder is a device, circuit, software program, algorithm or person that converts information from one format
or code to another. The purpose of encoder is standardization, speed, secrecy, security, or saving
space by shrinking size. If a device output code has fewer bits than the input code has, the device is usually called
an encoder.

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Decoder
A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique
output lines.

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Chapter Exercise
1. Construct a binary full adder using a multiplexer.
2. Construct a 16 X 1 multiplexer by using five 4x 1 multiplexers. Use block diagrams.
3. Design a combinational circuit that converts a 4-bit gray code to a 4-bit binary number.
Implement the circuit using exclusive-OR gates.
4. Construct a 16 x1 multiplexer with two 8 x1 and one 2 x1 multiplexers. Use block diagrams
5. Construct a 16 x1 multiplexer with four 4 x1 and 3 2 x1 multiplexers. Use block diagrams
and logical diagrams
6. Implement the following Boolean function with a 4 x 1 multiplexer:
7. F (A, B, C, D) = Σ (0, 1, 3, 4, 8, 9, 15)
8. Design an 8-bit parallel adder using a Full Adder. Use block diagrams and logical diagrams
9. Design an 8-bit parallel adder using a Full Adder. Use block diagrams and logical diagrams
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CHAPTER FOUR
Sequential Logic Circuits
Digital electronics is classified into combinational logic and sequential logic.
Combinational logic output depends on the present inputs’ levels, whereas sequential logic output not only
depends on the input levels, but also stored levels (previous output history).

A sequential circuit consists of a combinational circuit and feedback through the storage elements
in the circuit.

Inputs Combinational Outputs

Circuit
Memory
Element

- Sequential circuits can be categorized as being synchronous or asynchronous.

- A synchronous sequential circuit usually has a clock pulse (clocked sequential
circuits).
- Flip-flops are storage elements which are used in clocked sequential circuits.
- Each flip-flop can store one bit.

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LATCHES & FLIP-FLOPS

Both Latches and flip flops are circuit elements wherein the output not only depends on the current inputs, but
also depends on the previous input and outputs. The main difference between the latch and flip flop is that a
flip flop has a clock signal, whereas a latch does not.
A flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop
is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control
inputs and will have one or two outputs.
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit
of information. The main difference between latches and flip-flops is that for latches, their outputs are
constantly affected by their inputs as long as the enable signal is asserted. In other words, when they are
enabled, their content changes immediately when their inputs change. Flip- flops, on the other hand, have their
content change only either at the rising or falling edge of the enable signal. This enable signal is usually the
controlling clock signal. After the rising or falling edge of the clock, the flip-flop content remains constant
even if the input changes.

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S-R Latch using NAND & NOR Gate :

The bistable element is able to remember or store one bit of information. However, because it does not have
any inputs, we cannot change the information bit that is stored in it. In order to change the information bit, we
need to add inputs to the circuit. The simplest way to add inputs is to replace the two inverters with two NAND
gates as shown in Figure. This circuit is called a SR latch.
In addition to the two outputs Q and Q', there are two inputs S' and R' for set and reset respectively. Following
the convention, the prime in S and R denotes that these inputs are active low. The SR latch can be in one of
two states: a set state when Q = 1, or a reset state when Q = 0. Like the NOR Gate S-R flip flop, this one
also has four states. They are S=0, R=1 Q=0, Q’=1
This state is also called the SET state.
S=1, R=0 Q=1, Q’=0 This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of each other and that the value of Q follows
the compliment value of S.
S=0, R=0 Q=Q0, & Q’ =Q0’ No change
If both the values of S and R are switched to 0, then the circuit remembers the value of S and R in their previous

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state.
S=1, R=1 Q & Q’= Remember If both the values of S and R are switched to 1 it is an invalid state because the
values of both Q and Q’ are 1. They are supposed to be compliments of each other. Normally, this state must
be avoided. Another reason why we do not want both inputs to be asserted i.e. R=S=1 is that when they are
both asserted, Q is equal to Q', but we usually want Q to be the inverse of Q'. the following are NOR and
NAND gate latch

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D latch is designed to eliminate the indeterminate state in SR latch by making sure

that inputs S and R are never equal to 1 at the same time

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Clocked S-R Flip-Flop :

The problems with S-R flip flops using NOR and NAND gate is the invalid state. This problem can be
overcome by using a bistable SR flip- flop that can change outputs when certain invalid states are met,
regardless of the condition of either the Set or the Reset inputs. For this, a clocked S-R flip flop is designed by
adding two AND gates to a basic NOR Gate flip flop. The circuit diagram and truth table is shown below.
A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse is ‘0’, the outputs
of both the AND Gates remain ‘0’. As soon as a pulse is given the value of CP turns ‘1’. This makes the values
at S and R to pass through the NOR Gate flip flop. But when the values of both S and R values turn ‘1’, the
HIGH value of CP causes both of them to turn to ‘0’ for a short moment. As soon as the pulse is removed, the
flip flop state becomes intermediate. Thus either of the two states may be caused, and it depends on whether
the set or reset input of the flip-flop remains a ‘1’longer than the transition to ‘0’ at the end of the pulse. Thus
the invalid states can be eliminated. The circuit diagram of SR flip-flop is shown in the following figure.

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Clocked S-R Flip-flop

Present Inputs Present State Next State

S R Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x

Here, Q(t) & Q(t+1) are present state & next state respectively. So, SR flip-flop can be used for one of these
three functions such as Hold, Reset & Set based on the input conditions, when positive transition of clock
signal is applied. The following table shows the characteristic table of SR flip-flop.

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J-K FLIP-FLOP

A J-K flip flop can also be defined asa modification of the S-R flip flop. The only difference is that the
intermediate state is more refined and precise than that of a S-R flip flop. The behavior of inputs J and K is
same as the S and R inputs of the S-Rflip flop. The letter J stands for SET and the letter K stands for
CLEAR.
JK flip-flops are very similar to SR flip-flops. The J input is just like the S input in that when asserted, it sets
the flip-flop. Similarly, the K input is like the R input where it clears the flip-flop when asserted. The only
difference is when both inputs are asserted. For the SR flip-flop, the next state is undefined, whereas, for the
JK flip-flop, the next state is the inverse of the current state. In other words, the JK flip- flop toggles its state
when both inputs are asserted. The circuit, truth table and the logic symbol for the JK flip-flop is shown in
Figure. When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state. So, for
a value of Q = 1, it switches to Q=0 and fora value of Q = 0, it switches to Q=1.

The output may be repeated in transitions once they have been complimented for J=K=1 because of
the feedback connection in the JK flip-flop.

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Present Inputs Present State Next State

J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

D TYPE FLIP-FLOP:
Latches are often called level-sensitive because their output follows their inputs as long as they
are enabled. They are transparent during this entire time when the enable signal is asserted.
There are situationswhen it is more useful to have the output change only at the rising or
falling edge of the enable signal. This enable signal is usually the controlling clock signal.
Thus, we can have all changes synchronized to the rising or falling edge of the clock. An edge-
triggered flip-flop achieves this by combining in series a pair of latches.

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Figure shows a positive edge-triggered D flip-flop where two D latches are connected in series and a
clock signal Clk is connected to the E input of the latches, one directly, and one through an inverter.
The first latch is called the master latch. The master latch is enabled when Clk = 0 and follows the
primary input D. When Clk is a 1, the master latch is disabled but the second latch, called the slave
latch, is enabled so that the output from the master latch is transferred to the slave latch. The slave
latch is enabled all the while that Clk = 1, but its content changes only at the beginning of the cycle,
that is, only at the rising edge of the signal because once Clk is 1, the master latch is disabled and so
the input to the slave latch will not change. If the slave latchis enabled when the clock is low, then it
is referred to as a negative edge-triggered flip-flop. The circuit of Figure 10(a) is also referred to asa
master-slave D flip-flop because of the two latches used in the circuit. Figure 10(b) and (c) show the
truth table and the logic symbol respectively. Figure 10(d) shows the timing diagram for the D flip-
flop. The circuit diagram and truthtable is given in figure D flip flop is actually a slight modification
of the above explained clocked SR flip-flop. From the figure you can see that the D input is
connected to the S input and the complement of the D input is connected to the R input. The D input

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is passed on tothe flip flop when the value of CPis ‘1’. When CP is HIGH, the flip flop moves to the
SET state. If it is ‘0’,the flip flop switches to the CLEAR state.

D Q(t + 1)

0 0

1 1

T type Flip-Flop:
The T flip-flop has one input in addition to the clock. T stands for toggle for the obvious reason. When
T is asserted (T = 1), the flip-flop state toggles back and forth, and when T is de-asserted, the flip-flop
keeps its current state. The T flip-flop can be constructed using a D flip-flop with the two outputs Q and
Q' feedback to the D input through a multiplexer that is controlled by the T input as shown in Figure
below. This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected together

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and thus are also called a single input J- K flip flop. When clock pulse is given to the flip flop, the output
begins to toggle. Here also the restriction on the pulse width can be eliminated with a master-slave or
edge-triggered construction. Take a look at the circuit and truth table is shown in figure. The flip-flops
can be described fully and uniquely by its logic symbol, characteristic table, characteristic equation, state
diagram, or excitation table, and are summarized in Figure below.

Inputs Present State Next State

T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0

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Analysis of Clocked Sequential Circuits

The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence
of inputs, outputs, and internal states. It is also possible to write Boolean expressions that describe
the behavior of the sequential circuit. These expressions must include the necessary time sequence,
either directly or indirectly.
STATE TABLES AND STATE DIAGRAMS
In this model the effect of all previous inputs on the outputs is represented by a state of the circuit.
Thus, the output of the circuit at any time depends upon its current state and the input. These also
determine the next state of the circuit. The relationship that exists among the inputs, outputs, present
states and next states can be specified by either the state table or the state diagram.
State Table
The state table representation of a sequential circuit consists of three sections labeled present state,
next state and output. The present state designates the state of flip-flops before the occurrence of a
clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section
lists the value of the output variables during the present state.
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State Diagram
In addition to graphical symbols, tables or equations, flip-flops can also be represented graphically
by a state diagram. In this diagram, a state is represented by a circle, and the transition between states
is indicated by directed lines (or arcs) connecting the circles. The binary number inside each circle
identifies the state the circle represents. The directed lines are labelled with two binary numbers
separated by a slash (/). The input value that causes the state transition is labelled first. The number
after the slash symbol / gives the value of the output. For example, the directed line from state 00 to
01 is labelled 1/0, meaning that, if the sequential circuit is in a present state and the input is 1, then
the next state is 01 and the output is 0. If it is in a present state 00 and the input is 0, it will remain in
that state. A directed line connecting a circle with itself indicates that no change of state occurs. The
state diagram provides exactly the same information as the state table and is obtained directly from
the state table.
State Equations
The behavior of a clocked sequential circuit can be described algebraically by means of state

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equations. A state equation specifies the next state as a function of the present state and inputs.
Consider the sequential circuit shown in Fig. below. It consists of two D flip-flops A and B, an input
x and an output y.

These equations can be used to form the state table. Suppose the present state (i.e.Q1Q2) = 00 and
input x = 0. Under these conditions, we get Z = 0, D1 = 1, and D2 = 1. Thus the next state of the

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circuit D1D2 = 11, and this will be the present state after the clock pulse has been applied. The output
of the circuit corresponding to the present state Q1Q2 = 00 and x = 1 is Z = 0. This data is entered
into the state table as shown in Table.

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A clocked sequential circuit consists of a group of flip‐flops and combinational gates. The
flip‐flops are essential because, in their absence, the circuit reduces to a purely combinational
circuit (provided that there is no feedback among the gates). A circuit with flip‐flops is
considered a sequential circuit even in the absence of combinational gates. Circuits that
include flip‐flops are usually classified by the function they perform rather than by the name
of the sequential circuit. Two such circuits are registers and counters.
Chapter Exercise
Do analysis for the following sequential Circuits.
A
J Q Ax T Q y

x R Q
K Q

J Q B T Q
B

R Q
K Q

CLK CLK Reset

(A) (B)

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CHAPTER FIVE
REGISTERS AND COUNTERS
A register is a group of flip‐flops, each one of which shares a common clock and is
capable of storing one bit of information. An n‐bit register consists of a group of n flip‐flops capable
of storing n bits of binary information. In addition to the flip‐flops, a register may have combinational
gates that perform certain data‐processing tasks. In its broadest definition, a register consists of a
group of flip‐flops together with gates that affect their operation. The flip‐flops hold the binary
information, and the gates determine how the information is transferred into the register.
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a
group of flip-flops connected in a chain so that the output from one flip-flop becomes the
input of the next flip-flop. Most of the registers possess no characteristic internal sequence of
states. All the flip-flops are driven by a common clock, and all are set or reset simultaneously.
Shift registers are divided into two types.

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1. Uni directional shift registers

1.Serial in – serial out shift register
2.Serial in – parallel out shift register
3.Parallel in – serial out shift register
4. Parallel in – parallel out shift register
2. Bidirectional shift registers
1.Left shift register
2. Right shift register
Serial in – serial out shift register
A basic four-bit shift register can be constructed using four D flip-flops, as shown below. The
operation of the circuit is as follows. The register is first cleared, forcing all four outputs to zero. The
input data is then applied sequentially to the D input of the first flip-flop on the left (FF0). During
each clock pulse, one bit is transmitted from left to right. Assume a data word to be 1001. The least

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significant bit of the data has to be shifted through the register from FF0 to FF3.
Serial in – parallel out shift register
The difference is the way in which the data bits are taken out of the register. Once the data are stored,
each bit appears on its respective output line, and all bits are available simultaneously.
Parallel in – serial out shift register
A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-flops and
NAND gates for entering data (i.e writing) to the register.)
Parallel in –parallel out shift register
For parallel in - parallel out shift registers, all data bits appear on the parallel outputs immediately
following the simultaneous entry of the data bits. The following circuit is a four-bit parallel in -
parallel out shift register constructed by D flip-flops.
Bidirectional Shift Registers
The registers discussed so far involved only right shift operations. Each right shift operation has the
effect of successively dividing the binary number by two. If the operation is reversed (left shift), this

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has the effect of multiplying the number by two. With suitable gating arrangement a serial shift
register can perform both operations. A bidirectional, or reversible, shift register is one in which the
data can be shift either left or right.
COUNTERS
A counter is essentially a register that goes through a predetermined sequence of
binary states. The gates in the counter are connected in such a way as to produce the
prescribed sequence of states. Although counters are a special type of register, it is common to
differentiate them by giving them a different name.
Two of the most common types of shift register counters are introduced here: the Ring counter and
the Johnson counter. They are basically shift registers with the serial outputs connected back to the
serial inputs in order to produce particular sequences. These registers are classified as counters
because they exhibit a specified sequence of states.
Ring Counters
A ring counter is basically a circulating shift register in which the output of the most significant stage

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is fed back to the input of the least significant stage. The following is a 4-bit ring counter constructed
from D flip-flops. The output of each stage is shifted into the next stage on the positive edge of a
clock pulse. If the CLEAR signal is high, all the flip-flops except the first one FF0 are reset to 0. FF0
is preset to 1 instead.
Since the count sequence has 4 distinct states, the counter can be considered as a mod-4 counter.
Only 4 of the maximum 16 states are used, making ring counters very inefficient in terms of state
usage. But the major advantage of a ring counter over a binary counter is that it is self-decoding. No
extra decoding circuit is needed to determine what state the counter is in.
Johnson Counters
Johnson counters are a variation of standard ring counters, with the inverted output of the last stage
fed back to the input of the first stage. They are also known as twisted ring counters. An n stage
Johnson counter yields a count sequence of length 2n, so it may be considered to be a mod-2n counter.
The circuit above shows a 4-bit Johnson counter. The state sequence for the counter is given in the
table as well as the animation on the left.

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Chapter Exercise
1. Design a sequential circuit with two D flip-flops and one input X with the conditions when:
i. X=0, the state of the circuit remains the same
ii. X=1, the circuit goes through state transitions from
00 01 11 10 back to 00 and repeats.
2. Design a counter with the irregular binary count sequence shown in the state diagram using JK
flip flop.

3. Design the circuit represented by the diagram below. Treat unused states as don’t cares (use JK
flip-flops)

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