INSTRUCTION SET ARCHITECTURE

An instruction is a command to the hardware(CPU) for a basic operation.

Instruction Set Architecture (ISA) is a comprehensive specification that defines the fundamental instruction types and
their formats in both low-level and machine code, along with detailed descriptions of operand fields and addressing
modes.

There are 4 types of processors based on Instruction Set Architecture.

1. Stack-based CPU 2. Accumulator-based CPU 3. Register-Register CPU 4. Register-Memory CPU

1. Stack-based ISA

 Structure: Uses a stack to perform operations, with no explicit registers for general storage.
 Operation: Operands are pushed onto the stack, and operations (like addition or multiplication) use the
top elements.
 Example Instruction Sequence for Z = X * Y + W * U:
o PUSH X, PUSH Y, MULT, PUSH W, PUSH U, MULT, ADD, PUSH Z.
 Result Storage: Results are implicitly stored at the top of the stack.

In a stack-based ISA, the stack acts as both the source of data (where values for operations come from) and the place
where results are stored by default. You don’t need to specify the location for storing the result because it
automatically goes back on top of the stack. This is what we mean by the stack being "implicit" — the processor knows
to use the stack without needing extra instructions for data placement.

2. Accumulator-based ISA

 Structure: Uses a single accumulator (An accumulator register is a special register in a CPU that temporarily holds data for arithmetic and
logic operations, storing results for quick access.) register for all operations.
 Operation: Instructions assume one operand is in the accumulator; the result is also stored in the accumulator.
 Example:
o LOAD X (loads X into ACC),
o ADD Y (adds Y to ACC),
o STORE Z (stores ACC to Z).
 Advantages: Simplifies instruction format but limits flexibility to a single register.
3. Register-Register (Load-Store) Architecture

 Structure: Utilizes multiple general-purpose registers in the CPU, where any register can hold operands
or store results.
 Operation: Only LOAD and STORE instructions access memory; all other operations occur between
registers.
 Restriction: Memory cannot be directly referenced; operands and result locations must be explicitly
defined in registers.
 Example: LOAD R1, X; LOAD R2, Y; ADD R3, R1, R2; STORE Z, R3.
 Advantage: Increases efficiency in data processing by minimizing memory access.

4. Register-Memory Architecture

 Structure: Supports operations between a register and a memory location, allowing one operand to be
directly in memory.
 Operation: Reduces the need for multiple LOAD instructions by accessing memory directly.
 Compatibility: Can support Register-Register architecture, but the reverse is not possible.
 Example: LOAD R2, X; ADD R2, Y; STORE Z, R2.
 Advantage: Fewer instructions needed for accessing memory, though frequent memory access may
slow performance.

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How a computer works in 8 specific steps, with a simple example to illustrate each step. Let’s assume the
example is to "Add two numbers stored in memory locations 200H and 201H and store the result in a register."

 1. Load the Address of the First Instruction in the Program Counter (PC) (from a predefined
starting location in memory or sometimes from firmware instructions.)
The CPU starts by setting the Program Counter (PC) to the address of the first instruction in memory, so
it knows where to begin.
 Example: The PC is set to the memory location holding the instruction to load the number at address
200H.
 2. Load the Address from PC into the Memory Address Register (MAR)
The address in the PC is then copied to the Memory Address Register (MAR), which will hold the
memory address of the current instruction.
 Example: The address for the "load number from 200H" instruction is moved to the MAR.

 3. Place Address on the Address Bus and Select the Memory Location
The address in the MAR is placed onto the Address Bus (a pathway for sending addresses) and sent to
memory, selecting the memory location for the instruction.
 Example: The MAR places the "load from 200H" instruction's address on the Address Bus, selecting the
location in memory.

 4. Send Read Signal to Memory and Fetch the Instruction

The Control Unit sends a "Read" signal to memory, retrieving the instruction located at the specified
address. This instruction is then sent back to the CPU through the Data Bus.
 Example: The CPU fetches the instruction "Load the number from 200H" and brings it to the CPU.

 5. Load the Instruction into the Instruction Register (IR)

The fetched instruction is loaded into the Instruction Register (IR), which stores it temporarily so the
CPU can decode and understand it.
 Example: "Load the number from 200H" is placed in the IR.

 6. Increment PC to Point to the Next Instruction

After loading the instruction, the PC is incremented to point to the next instruction's address in memory.
This step prepares the CPU to fetch the next instruction after completing the current one.
 Example: The PC is incremented to the address for the next instruction, "Load the number from 201H."

 7. Decode the Instruction and Generate Control Signals

The Control Unit decodes the instruction in the IR to understand what operation to perform. Based on
this, it sends signals to activate the necessary CPU components.
 Example: The CPU decodes "Load the number from 200H" and signals to load data from 200H into a
register (say Register A).

 8. Execute the Instruction and Store the Result

The CPU executes the instruction, which could involve data movement, arithmetic, or logic operations.
The result is stored in the designated register or memory location.
 Example: The CPU loads the number from 200H into Register A, then repeats the process to load the
number from 201H into Register B. After both values are in registers, the CPU adds them and stores the
result in Register C.

 In Summary
The computer goes through this cycle—fetching, decoding, and executing instructions—to process tasks
step-by-step. For our example, it completes loading numbers, adding them, and storing the result.
Instruction Formats

The instruction ADD M, D1, D2 follows a three-operand format. Here’s what each part typically means:
 ADD: This is the opcode, indicating the operation to perform—in this case, addition.
 M: This is the destination, where the result of the addition will be stored. Here, M likely represents a memory
location.
 D1 and D2: These are the source operands, or the values to be added. They could be memory addresses or
register values, depending on the system.
What the Instruction Does
The instruction tells the CPU to:
1. Fetch the values from D1 and D2.
2. Add the values of D1 and D2 together.
3. Store the result in M.
Example
Suppose:
 D1 holds the value 10.
 D2 holds the value 5.
 M is an address in memory where we want to save the result.
The CPU will:
 Add 10 + 5, getting 15.
 Store 15 in the location specified by M.
So after executing ADD M, D1, D2, M will contain the value 15.

Three-Operand Format

 Structure: Uses three fields for operands.

 Example: ADD R1, R2, R3
o This instruction adds the values in registers R2 and R3, then stores the result in R1.
 Memory Version: ADD M1, M2, M3
o Adds values from two memory locations (M2 and M3) and stores the result in another memory
location (M1).
Two-Operand Format

 Structure: Uses two fields for operands.

 Example: ADD R1, R2
o Adds the values in R1 and R2, storing the result back in R1.
 Memory Version: ADD M1, M2
o Adds the values in memory locations M1 and M2, storing the result in M1.

One-Operand Format
 Structure: Opcode Operand
o Register Mode: ADD R1
 Adds the value in register R1 to the Accumulator (AC), storing the result back in AC.
o Memory Mode: ADD M
 Adds the value in memory location M to the Accumulator (AC), storing the result back in AC.
Example in Action:
 Suppose the Accumulator (AC) contains 10, and memory location M holds 5.
 The CPU will add 10 + 5 to get 15 and store 15 in the Accumulator.

Opcode-Only Format

 Structure: Opcode
o Register Mode: CLC
 Clears the Carry flag; operates directly on CPU flags with no operand required.

o Memory Mode: NOP

 No operation is performed; simply moves to the next instruction, with no operand needed.
What is Addressing Mode?

Addressing Mode refers to the way a CPU accesses data stored in memory. It determines how the operand (the
data to be used in an operation) is specified in an instruction. Different addressing modes allow programmers to
use various methods to access data, making programming more flexible and efficient.

Types of Addressing Modes

There are several addressing modes, but here are four common types based on different CPU architectures:

1. Stack-Based Addressing Mode

2. Accumulator-Based Addressing Mode
3. Register-Register Addressing Mode
4. Register-Memory Addressing Mode

Definitions and Characteristics of Addressing Modes

1. Stack-Based Addressing Mode

 Definition: Operands are accessed using a last-in, first-out (LIFO) structure called a stack.
 How it works:
o Data is pushed onto the stack using instructions.
o Data is popped from the stack for operations.
 Key Features:
o Efficient for function calls and local variable storage.
o Uses a stack pointer to keep track of the top of the stack.

2. Accumulator-Based Addressing Mode

 Definition: An implicit register, called the accumulator, is used to store intermediate results.
 How it works:
o Operations are performed directly using the accumulator.
o Only one operand is specified in the instruction; the other is assumed to be in the accumulator.
 Key Features:
o Simplifies instruction sets as only one operand needs to be specified.
o Fast for operations since it minimizes memory access.

3. Register-Register Addressing Mode

 Definition: Operands are located in the CPU's registers.

 How it works:
o Instructions specify registers directly as operands.
o All data processing occurs within registers, leading to fast execution.
 Key Features:
o Highly efficient as registers are faster than memory.
o Limited by the number of available registers.

4. Register-Memory Addressing Mode

 Definition: One operand is stored in a register and the other in memory.

 How it works:
o Instructions specify one operand in a register and the other in memory.
 oAllows for more complex operations with data in memory.
 Key Features:
o Combines the speed of registers with the capacity of memory.
o More flexible than register-register mode, allowing larger datasets.

Comparison Table of Addressing Modes

Feature Stack-Based Accumulator-Based Register-Register Register-Memory

Operand
Stack (LIFO) Accumulator CPU Registers Register and Memory
Location

Moderate (depends on stack Fast (minimal memory Moderate (memory access

Speed Fast (all in CPU)
management) access) required)

More complex (stack Simple (single Moderate (fixed Moderate (register/memory

Complexity
management) operand) operands) mix)

Simple arithmetic,
Use Cases Function calls, recursion Data processing Data manipulation
logic

Limited (only one Limited by register

Flexibility Limited (LIFO structure) Flexible (mixed access)
operand) count

This table highlights the differences among the four addressing modes in terms of operand location, speed,
complexity, use cases, and flexibility. Let me know if you need further clarification or additional information!