UNIT-3

Handshaking is a communication process used to make sure that two devices are ready to send and receive data safely and
efficiently, just like making sure both device are ready before starting a conversation.

Types of Handshaking:

• Hardware Handshaking: Uses physical signals (like wires or circuits) to coordinate data transfer.

• Software Handshaking: Uses software signals or commands for coordination, often found in network
communication.

Asynchronous data transfer enables computers to send and receive data without having to wait for a real-time response.
With this technique, data is conveyed in discrete units known as packets that may be handled separately.

• Sender: The machine or gadget that transfers the data.

• Receiver: A device or computer that receives data.

• Packet: A discrete unit of transmitted and received data.

• Buffer: A short-term location for storing incoming or departing data.

the STROBE METHOD is a way to transfer data between two devices, like a sender and a receiver, using a single signal called a
“strobe.”

Mode of Data Transfer refers to the different ways data can be moved between components, like from the CPU to memory
or from a storage device to the CPU.

Common Modes of Transfer:

1. Programmed I/O (Input/Output):

o The CPU is directly involved in transferring data.

It keeps checking if data is ready and then
manually moves it.

o It’s simple but keeps the CPU busy.

2. Interrupt-Driven I/O:

o The device tells the CPU when it’s

ready to send or receive data, and
the CPU only transfers data when
alerted by an interrupt.

o This saves the CPU’s time and effort.

3. Direct Memory Access (DMA):

o A special controller moves data

directly between memory and a device
without involving the CPU, making transfers
faster and more efficient.

o It’s efficient and allows the CPU to focus on

other tasks.

• Control Unit (CU)

The Control Unit is a part of the CPU that manages and
directs how the computer’s processor handles instructions
from a program.

2. Microprogrammed Control Unit

In a Microprogrammed Control Unit, the control signals are

generated using a set of instructions called microinstructions
stored in a small memory called the control memory.

3. Hardwired Control Unit

A Hardwired Control Unit uses fixed circuits and

logic to control the CPU. The control signals are
generated by a network of logic gates and
circuits that are “hardwired” or built into the
hardware.

• The Control Unit is like the brain inside the CPU

that coordinates tasks.

• A Microprogrammed Control Unit is flexible and

easier to program but slower.

• A Hardwired Control Unit is faster but fixed and

harder to change.
 Hardwired Control Unit Micro-programmed Control Unit

Implementation Fixed set of logic gates and circuits Microcode stored in memory

Flexibility Less flexible, difficult to modify More flexible, easier to modify

Instruction Set Supports limited instruction sets Supports complex instruction sets

Complexity of Design Simple design, easy to implement Complex design, more difficult to implement

Speed Fast operation Slower operation due to microcode decoding

Debugging and Testing Difficult to debug and test Easier to debug and test

Size and Cost Smaller size, lower cost Larger size, higher cost

Maintenance and Difficult to upgrade and maintain Easier to upgrade and maintain
Upgradability

Interrupts
To born hardware and software signal. Interrupt is a signal to processor execute essential process

Techniques to Handle Interrupts

There are several ways a computer handles

interrupts, making sure it doesn't forget to do other
tasks while responding to urgent events:

1. Interrupt Service Routine (ISR):

2. Interrupt Priorities:

3. Masking:.

4. Interrupt Vector:

5. Context Switching:

A Priority Interrupt system allows the computer to handle the most important events first, ensuring it responds
quickly to critical situations while still managing less urgent tasks.

Why DMA better then program I/O

1. Frees Up the CPU: Since DMA handles the data transfer.
2. Faster Data Transfer: DMA can transfer large chunks of data much faster.
3. Efficiency: With DMA, the data transfer happens more smoothly and with less overhead.
DIFFERENT I/O INTERFACE USED IN COMPUTER
In computers, various I/O (Input/Output) interfaces are used to connect and communicate with external devices
1. Serial Interface
2. Parallel Interface
3. USB (Universal Serial Bus)
4. SATA (Serial ATA)
5. PCI (Peripheral Component Interconnect) / PCIe (PCI Express)
6. HDMI (High-Definition Multimedia Interface)
7. VGA (Video Graphics Array)
8. Ethernet (LAN - Local Area Network)
9. Bluetooth

Cache Hit: The data is already in the fast cache memory (quick access).
Cache Miss: The data is not in the cache, so the CPU has to go to slower memory (RAM).
Page Hit: The needed data is already in RAM (quick access).
Page Fault: The data is missing from RAM and needs to be fetched from the slower hard drive.
Locality of Reference: Programs tend to reuse recently accessed data (temporal locality) or nearby data (spatial
locality).
Inclusion: If data is in a larger cache (like L2), it should also be in the smaller cache (like L1).
Coherence: Ensures that all caches have the same, correct data, so no conflicts happen.

Daisy chain in DMA is a way of organizing devices in a sequence where control over data transfer is passed from
one device to the next. Devices are prioritized, and only one device can transfer data at a time, making the process
orderly and efficient.
How it Works:
1. DMA Controller: The DMA controller is responsible for managing data transfers between devices (like hard
drives, sound cards) and memory.
2. Daisy Chain Connection: In a daisy chain, devices are connected one after the other in a series. Each device
has a priority level (like the order of people in the line).
3. Priority Order: The device at the beginning of the chain has the highest priority for using the DMA. If that
device doesn’t need DMA access, control is passed on to the next device in the chain, and so on.
4. Data Transfer: The device with control can start transferring data directly to memory. Once done, it passes
control to the next device in line, and the process continues.
 UNIT-4
Primary Memory:

• This is the main memory used by the

computer to store data and instructions
while tasks are being performed.

• It is divided into two types: RAM (Random

Access Memory) and ROM (Read-Only
Memory).

o RAM: It is temporary storage that is

volatile, meaning it loses data when
the power is turned off. It is further
divided into:

• Static RAM (SRAM): Faster and used for

cache memory.
• Dynamic RAM (DRAM): Slower compared
to SRAM and needs to be refreshed periodically.
o ROM: Permanent storage that retains data even when the computer is off. It is divided into:

• PROM (Programmable ROM): Can be programmed once.

• EPROM (Erasable Programmable ROM): Can be erased and reprogrammed using UV light.
• EEPROM (Electrically Erasable Programmable ROM): Can be erased and reprogrammed using electrical signals.
Secondary Memory:

• This refers to external storage devices used for data that doesn’t need to be accessed as quickly. Examples
include Hard Disks, Magnetic Tapes, CDs, DVDs, and Zip Disks.
• It is non-volatile, meaning it retains data even when the computer is turned off.
Cache Memory:

• This is a small and fast type of memory located close to the CPU. It stores frequently used data to speed up
processing.

Registers:

• These are small, extremely fast memory locations inside the CPU. They are used to store data temporarily while
performing operations.

Magnetic Disk: Fast and used for regular, everyday storage and retrieval of
data.

Magnetic Tape: Slower but cost-effective, ideal for backup and archival
storage.
Cache Memory:

• This is a small and fast type of memory located close to the CPU. It stores frequently used data to speed up
processing.

CACHE MEMORY DESIGN ELEMENTS

Cache Size:

• The total amount of data that the cache can hold. A larger cache can store more data, but it is also more
expensive and may increase power consumption.

• Designers have to balance the cache size with cost and efficiency.

Block Size (or Cache Line Size):

• The smallest unit of data that can be transferred between the cache and main memory.

• A larger block size reduces the number of transfers but might load unnecessary data, while a smaller size may
result in more frequent transfers.

Mapping Function:

o Direct Mapping: Each block of main memory maps to exactly one location in the cache, which is simple
but can cause conflicts.

o Fully Associative Mapping: A block can be placed in any location in the cache, reducing conflicts but
making the cache more complex.

o Set-Associative Mapping: A combination of both methods, where the cache is divided into sets, and
each block maps to any location within a specific set.

Replacement Policy:

o Least Recently Used (LRU): Removes the data that hasn’t been accessed for the longest time.

o First-In-First-Out (FIFO): Removes the oldest data in the cache.

o Random: Removes a random block of data.

Write Policy:

o Write-Through: Data is written to both the cache and main memory at the same time, ensuring data
consistency but possibly slowing down performance.

o Write-Back: Data is written only to the cache, and main memory is updated later, which is faster but may
cause issues if the cache is not properly managed.

Hit Rate and Miss Rate:

• Hit Rate: The percentage of times the data requested by the CPU is found in the cache. A higher hit rate means
better performance.

• Miss Rate: The percentage of times the data is not found in the cache and must be fetched from main memory,
slowing down performance.
Virtual memory is a computer system feature that allows a computer to use more memory than what is physically
available in the form of RAM (Random Access Memory). It does this by temporarily transferring data from RAM to a
space on the hard drive called the page file or swap space.

Need/Advantages/Significance of Virtual Memory

1. Handling Large Applications

2. Running Multiple Applications

3. Efficient Memory Management

4. Preventing System Crashes

5. Flexibility for Users

1. Direct Mapping

• Each block of main memory is mapped to only one specific location in the cache. If two different pieces of data
need to be stored in the same spot, the new data will replace the old data.

2. Fully Associative Mapping

• A block from main memory can be placed anywhere in the cache. The cache system searches the entire cache to
find a location for the data.

3. Set Associative Mapping

• Combines both methods. The cache is divided into groups called "sets." Each block of data from main memory
maps to a specific set, but within that set, it can be placed in any spot.

Summary:

• Direct Mapping: Simple but can cause more data conflicts.

• Fully Associative Mapping: Flexible but complex and costly.

• Set Associative Mapping: A balanced approach that minimizes conflicts while being efficient.
Page Replacement Algorithms help manage memory effectively by deciding what data to remove to make room
for new data, ensuring smooth system operation.
1. FIFO Page Replacement Algorithm

• FIFO stands for First-In-First-Out. It works like a queue: the oldest page in memory (the one that has been there
the longest) is removed first when a new
page needs to be loaded.

2. LIFO Page Replacement Algorithm

• LIFO stands for Last-In-First-Out. The

most recently loaded page is the first to
be removed when space is needed.

3. LRU Page Replacement Algorithm

• LRU stands for Least Recently Used. The

page that has not been used for the longest time is removed first. It tries to predict which page is least likely to
be needed soon based on past usage.

4. Optimal Page Replacement Algorithm

• This algorithm removes the page that will not be used for the longest time in the future. It’s the most efficient
method, but it’s hard to implement because it requires knowing future page requests.

Summary

• FIFO: Removes the oldest page.

• LIFO: Removes the most recent page.

• LRU: Removes the page that hasn’t been used for the longest time.

• Optimal: Removes the page that won’t be needed for the longest time in the future (ideal but hard to predict).

1. Memory Space

• Memory Space refers to the actual physical or virtual memory that is available in the computer system to store
data.

2. Address Space

• Address Space refers to the range of addresses that a program can use to access memory. It’s like a map
showing all the possible "locations" where data can be stored in the computer’s memory.

Address space is about where data could be stored, and Memory space is about where data is actually stored.

Content Addressable Memory

Content Addressable Memory (CAM) is a
special type of computer memory used to
search for data based on its content rather
than its address.
 UNIT 5
Speedup Ratio
The speedup ratio is a critical measure in parallel computing that indicates the improvement in performance
when a task is parallelized.
Parallel Processing/Organization
Parallel organization in computer architecture refers to the design and arrangement of hardware components
that allow multiple processes or tasks to be executed simultaneously, aiming to improve computational
efficiency and performance

Parallel Processing involves dividing a problem into smaller sub-problems and solving them concurrently to
reduce computation time.
Parallel processing

• Is carrying out the processes parallel.

• Makes a program run faster.
• Saves the execution time.

1. Single Instruction stream Single Data stream (SISD)

❖ Found in the single CPU systems.
2. Single Instruction stream Multiple Data streams
(SIMD)
3. Multiple Instruction stream Single Data stream (MISD)
4. Multiple Instruction Multiple Data stream (MIMD)

Multiprocessing: Refers to using multiple processors (or cores) to handle multiple processes, either in a
shared memory (SMP) or distributed memory model.
Asymmetric Multiprocessing (AMP) is a type of multiprocessing in which one processor (the master) controls
the system and coordinates tasks, while the other processors (slaves) execute specific tasks under the master’s
control.
Symmetric Multiprocessing (SMP) is a type of multiprocessing system where all processors have equal access
to shared memory and work independently on tasks. |||
Vector Computation: Refers to performing mathematical operations on entire arrays or vectors of data
simultaneously, often utilizing specialized hardware instructions like SIMD. |||
Cache Coherence
In a single CPU system, two copies of same data, one in cache memory and another in main memory may
become different. This data inconsistency is called as cache coherence problem.
Cache Coherence Approaches
cache coherence problem, several strategies and protocols
are used
1. Write Propagation
the update is propagated to all other caches that have a
copy of the data

Type
1. Write-through - Ensures that memory is always up
to date
2. Write-back - Reduces the number of writes to main memory, leading to improved performance.

2 MESI Protocol: A common snooping-based protocol is the MESI (Modified, Exclusive, Shared, Invalid)
protocol, which defines four states for each cache line:
❖ Modified (M): The cache has a copy of the data, and it is modified (i.e., not the same as the main memory).
❖ Exclusive (E): The cache has the only copy of the data, and it is unmodified (i.e., matches the main memory).
❖ Shared (S): The cache has a copy of the data, but it may be shared with other caches, and it is unmodified.
❖ Invalid (I): The cache does not have a valid copy of the data.

S. RISC CISC
1 RISC is a reduced instruction set. CISC is a complex instruction set.
The number of instructions is less as compared to The number of instructions is more as
2
CISC. compared to RISC.
3 The addressing modes are less. The addressing modes are more.
4 It works in a fixed instruction format. It works in a variable instruction format.
5 The RISC consumes low power. The CISC consumes high power.
6 The RISC processors are highly pipelined. The CISC processors are less pipelined.
It optimizes the performance by focusing on It optimizes the performance by focusing on
7
software. hardware.
8 Requires more RAM. Requires less RAM.
Concept of Arithmetic Pipeline
An arithmetic pipeline is a series of processing stages where each stage performs a specific arithmetic
operation. Data flows through each stage sequentially, and each stage performs its task in parallel with other
stages
Stages of an Arithmetic Pipeline
An arithmetic pipeline generally includes multiple stages, such as:
1. Fetch: Retrieve data from memory or registers.
2. Operand Fetch: Fetch the operands (inputs) for the arithmetic operation.
3. Arithmetic Operation: Perform the actual arithmetic calculation (e.g., addition, subtraction,
multiplication).
4. Result Write-back: Store or send the result back to memory or a register.
Illustration of Pipeline Execution
At each clock cycle, a new set of operands enters the pipeline, and each stage processes the data in parallel.
Here’s a step-by-step breakdown of how the pipeline works for four additions:

Stage 2 (Operand Stage 3 (Perform Stage 4 (Store

Clock Cycle Stage 1 (Fetch)
Fetch) Addition) Result)

Cycle 1 A1, B1
Cycle 2 A2, B2 A1, B1
Cycle 3 A3, B3 A2, B2 A1+B1
Cycle 4 A4, B4 A3, B3 A2+B2 A1+B1
Cycle 5 A4, B4 A3+B3 A2+B2
Cycle 6 A4+B4 A3+B3
Cycle 7 A4+B4
PIPELINE
Pipelining in computer architecture is a technique that allows a computer to process multiple instructions at
the same time, by breaking down the process into smaller stages. Each stage handles a part of the instruction,
and while one instruction is being processed at one stage, another instruction can be processed at the
previous stage.

Instruction Fetch (IF): The instruction is fetched from memory.

Instruction Decode (ID): The instruction is decoded, and the necessary registers are read.
 Execute (EX): The operation is executed (e.g., arithmetic or logic operations).
Memory Access (MEM): Access data memory, if necessary (for load/store instructions).
Write-back (WB): Write the result of the operation back to the register file.

What is Latenecy?
• single instruction to complete its execution.
• Lower latency indicates better performance .
• It is calculated as, Latency= Execution time/ Number of instruction executed.

Structural Hazard
Hardware resource conflicts among the instructions in the pipeline cause structural hazards.
Control Hazards
Branch hazards are caused by branch instructions and are known as control hazards in computer architecture.
The flow of program/instruction execution is controlled by branch instructions.
Data Hazards
A data hazard occurs in a pipeline when one instruction depends on the data of a previous instruction that has
not yet completed. There are three main types:
1. Read After Write (RAW): Occurs when an instruction needs to read a register that a previous
instruction is writing to, causing a delay.
2. Write After Read (WAR): Happens when an instruction writes to a register before a previous
instruction has finished reading from it.
3. Write After Write (WAW): Occurs when two instructions write to the same register, and the order of
writes matters.
Data resource conflicts among the instructions in the pipeline cause data hazards.
Data hazards in pipelining emerge when the execution of one instruction is dependent on the results of
another instruction that is still being processed in the pipeline.
INSTRUCTION SET ARCHITECTURE
Instruction Set Architecture (ISA) is the part of a computer's architecture that defines how the processor
communicates with the software. It is essentially a set of rules and instructions that a CPU can understand and
execute.
1. Instructions: The types of operations the
CPU can perform (e.g., adding numbers,
moving data).
2. Registers: Small storage locations in the
CPU used for temporary data storage.
3. Addressing Modes: Ways the CPU can
access memory (e.g., directly or
indirectly).
4. Data Formats: The way data is
represented and manipulated (e.g.,
integers, floating-point numbers).

❖ Instruction Cycle

1. Fetch instruction from memory.

2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.