PROGRAMMABLE PERIPHERAL INTERFACE – 8255

8255 is a device used to parallel data transfer between processor and slow peripheral devices like
ADC, DAC, keyboard, 7-segment display, LCD, etc.

The internal block diagram of 8255

PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines
depending upon the control word loaded into the control word register.
PC7-PC4: Upper nibble of port C lines. They may act as either output latches or input buffers
lines. This port also can be used for generation of handshake lines in mode 1 or mode 2.
PC3-PC0: These are the lower port C lines; other details are the same as PC7-PC4 lines.
PB0-PB7: These are the eight port B lines which are used as latched output lines or buffered
input lines in the same way as port A.
RD: This is the input line driven by the microprocessor and should be low to indicate read
operation to 8255.
WR: This is an input line driven by the microprocessor. A low on this line indicates write
operation.
CS: This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR
signals, otherwise RD and WR signal are neglected.
A1-A0: These are the address input lines and are driven by the microprocessor. These lines A1-
A0 with RD, WR and CS from the following operations for 8255. These address lines are used
for addressing any one of the four registers, i.e. three ports and a control word register as given
in table below. In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus,
the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.
D0-D7: These are the data bus lines those carry data or control word to/from the microprocessor.
RESET: Logic high on this line clears the control word register of 8255. All ports are set as
input ports by default after reset.

Operational Modes of 8255

There are two main operational modes of 8255:
Input/output mode
Bit set/reset mode
Input / Output Mode
There are three types of the input/output mode. They are as follows:
Mode 0
In this mode, the ports can be used for simple input/output operations without handshaking. If
both port A and B are initialized in mode 0, the two halves of port C can be either used together
as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of
port C are independent, they may be used such that one-half is initialized as an input port while
the other half is initialized as an output port. The input output features in mode 0 are as follows:
O/p are latched.
I/p are buffered not latched.
Port do not have handshake or interrupt capability.
Mode 1
When we wish to use port A or port B for handshake (strobed) input or output operation,
we initialize that port in mode 1 (port A and port B can be initialized to operate in different
modes, ie, for eg., port A can operate in mode 0 and port B in mode 1). Some of the pins of port
C function as handshake lines.
For port B in this mode (irrespective of whether is acting as an input port or output port),
PC0, PC1 and PC2 pins function as handshake lines. If port A is initialized as mode 1 input port,
then, PC3, PC4 and PC5 function as handshake signals. Pins PC6 and PC7 are available for use
as input/output lines. The mode 1 which supports handshaking has following features:
1. Two ports i.e. port A and B can be used as 8-bit I/O port.
2. Each port uses three lines of port c as handshake signal and remaining two signals can
be function as I/O port.
3. Interrupt logic is supported.
4. Input and Output data are latched.
Mode 2
Only group A can be initialized in this mode. Port A can be used for bidirectional
handshake data transfer. This means that data can be input or output on the same eight lines (PA0
- PA7). Pins PC3 -PC7 are used as handshake lines for port A. The remaining pins of port C
(PC0 - PC2) can be used as input/output lines if group B is initialized in mode 0. In this mode,
the 8255 may be used to extend the system bus to a slave microprocessor or to transfer data bytes
to and from a floppy disk controller.
Bit Set/Reset (BSR) mode
In this mode only port b can be used (as an output port). Each line of port C (PC0 - PC7)
can be set/reset by suitably loading the command word register. no effect occurs in input-output
mode. The individual bits of port c can be set or reset by sending the signal OUT instruction to
the control register.

A simple schematic for interfacing the 8255 with 8085 processor

 The 8255 can be either memory mapped or I/O mapped in the system. In the schematic
shown in above is I/O mapped in the system.
 Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.
 The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-
0 to IOCS-7) and in this, the chip select IOCS- 1 is used to select 8255.
 The address line A7 and the control signal IO/M (low) are used as enable for the decoder.
 The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected to
A1 of 8255 to provide the internal addresses.
 The data lines D0-D7 are connected to D0-D7 of the processor to achieve parallel data
transfer.
 The I/O addresses allotted to the internal devices of 8255 are listed in table.
 The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected to
A1 of 8255 to provide the internal addresses.
 The data lines D0-D7 are connected to D0-D7 of the processor to achieve parallel data
transfer.
 The I/O addresses allotted to the internal devices of 8255 are listed in table.
PROGRAMMABLE INTERRUPT CONTROLLER – 8259

It has eight functional blocks. They are,

1. Control logic
2. Read Write logic
3. Data bus buffer
4. Interrupt Request Register (IRR)
5. In-Service Register (ISR)
6. Interrupt Mask Register (IMR)
7. Priority Resolver (PR)
8. Cascade buffer.
The data bus and its buffer are used for the following activities.
1. The processor sends control word to data bus buffer through D0-D7.
2. The processor read status word from data bus buffer through D0-D7
3. From the data bus buffer the 8259 send type number (in case of 8086) or the call opcode and
address (in case of 8085) through D0-D7 to the processor.
 The processor uses the RD (low), WR (low) and A0 to read or write 8259.
 The 8259 is selected by CS (low).
 The IRR has eight input lines (IR0-IR7) for interrupts. When these lines go high, the
request is stored in IRR. It registers a request only if the interrupt is unmasked.
 Normally IR0 has highest priority and IR7 has the lowest priority. The priorities of the
interrupt request input are also programmable.
 First the 8259 should be programmed by sending Initialization Command Word (ICW)
and Operational Command Word (OCW). These command words will inform 8259 about
the following,
l. Type of interrupt signal (Level triggered / Edge triggered).
2. Type of processor (8085/8086).
3. Call address and its interval (4 or 8)
4. Masking of interrupts.
5. Priority of interrupts.
6. Type of end of interrupts.

 The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be
masked. The relevant information is send by the processor through OCW.
 The in-service register keeps track of which interrupt is currently being serviced.
 The priority resolver examines the interrupt request, mask and in-service registers and
determines whether INT signal should be sent to the processor or not.
 The cascade buffer/comparator is used to expand the interrupts of 8259.
 In cascade connection one 8259 will be directly interrupting 8086 and it is called master
8259.
 To each interrupt request input of master 8259 (IR0-IR7), one slave 8259 can be
connected. The 8259s interrupting the master 8259 are called slave 8259s.
  Each 8259 has its own addresses so that each 8259 can be programmed independently by
ending command words and independently the status bytes can be read from it.

INTERFACING 8259 WITH 8085 MICROPROCESSOR

 It requires two internal address and they are A =0 or A = 1.

 It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to
 8085 is shown in figure is I/O mapped in the system.
 The low order data bus lines D0-D7 are connected to D0-D7 of 8259.
 The address line A0 of the 8085 processor is connected to A0 of 8259 to provide the
internal address.
 The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select
signal for 8259.
 The address lines A4, A5 and A6 are used as input to decoder.
 The control signal IO/M (low) is used as logic high enables for decoder and the address
line A7 is used as logic low enable for decoder.
The I/O addresses of 8259 are shown in table.

Working of 8259 with 8085 processor:

First the 8259 should be programmed by sending Initialization Command Word (ICW) and
Operational Command Word (OCW). These command words will inform 8259 about the
following,
1. Type of interrupt signal (Level triggered / Edge triggered).
2. Type of processor (8085/8086).
3. Call address and its interval (4 or 8)
4. Masking of interrupts.
5. Priority of interrupts.
6. Type of end of interrupts.
 Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an
interrupt through any one of the interrupt lines IR0-IR7 it checks for its priority and also
checks whether it is masked or not.
 If the previous interrupt is completed and if the current request has highest priority and
unmasked, then it is serviced.
 For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085.In
response it expects an acknowledge INTA (low) from the processor.
 When the processor accepts the interrupt, it sends three INTA (low) one by one.
 In response to first, second and third INTA (low) signals, the 8259 will supply CALL
opcode, low byte of call address and high byte of call address respectively. Once the
processor receives the call opcode and its address, it saves the content of program counter
(PC) in stack and load the CALL address in PC and start executing the interrupt service
routine stored in this call address.
8253(8254) PROGRAMMABLE INTERVAL TIMER:

The 8254 programmable Interval timer consists of three independent 16-bit

programmable counters (timers). Each counter is capable of counting in binary or binary
coded decimal. The maximum allowable frequency to any counter is 10MHz. This
device is useful whenever the microprocessor must control real-time events. The timer
in a personal computer is an 8253. To operate a counter a 16-bit count is loaded in its
register and on command, it begins to decrement the count until it reaches 0. At the end
of the count it generates a pulse, which interrupts the processor. The count can count
either in binary or BCD Each counter in the block diagram has 3 logical lines connected
to it. Two of these lines, clock and gate, are inputs. The third, labeled OUT is an output.

Fig : 16 Block Diagram of 8253 programmable interval timer

Data bus buffer- It is a communication path between the timer and the microprocessor.
The buffer is 8-bit and bidirectional. It is connected to the data bus of the
microprocessor. Read /write logic controls the reading and the writing of the counter
registers. Control word register, specifies the counter to be used and either a Read or a
write operation. Data is transmitted or received by the buffer upon execution of INPUT
instruction from CPU as shown in figure 16. The data bus buffer has three basic
functions,

(i). Programming the modes of 8253.

(ii). Loading the count value in times

(iii).Reading the count value from timers.

 Pin Diagram of 8253

The data bus buffer is connected to microprocessor using D7 – D0 pins which

are also bidirectional. The data transfer is through these pins. These pins will be in high-
impedance (or this state) condition until the 8253 is selected by a LOW or CS and
either the read operation requested by a LOW RD on the input or a write operation WR
requested by the input going LOW.

Read/ Write Logic:

It accepts inputs for the system control bus and in turn generation the control signals for
overall device operation. It is enabled or disabled by CS so that no operation can occur
to change the function unless the device has been selected as the system logic.

CS :

The chip select input is used to enable the communicate between 8253 and the
microprocessor by means of data bus. A low an CS enables the data bus buffers, while
a high disables the buffer. The CS input does not have any affect on the operation of
three times once they have been initialized. The normal configuration of a system
employs an decode logic which actives CS line, whenever a specific set of addresses
that correspond to 8253 appear on the address bus.

RD & WR :

The read ( RD ) and write WR pins central the direction of data transfer on the 8-bit bus.
When the input RD pin is low. Then CPU is inputting data from 8253 in the form of
counter value. When WR pins is low, then CPU is sending data to 8253 in the form of
mode information or loading counters. The RD & WR should not both be low
simultaneously. When RD & WR pins are HIGH, the data bus buffer is disabled.

A0 & A1:

These two input lines allow the microprocessor to specify which one of the internal
register in the 8253 is going to be used for the data transfer. Fig shows how these two
lines are used to select either the control word register or one of the 16-bit counters.

Control word register:

It is selected when A0 and A1 . It the accepts information from the data bus buffer and
stores it in a register. The information stored in then register controls the operation
mode of each counter, selection of binary or BCD counting and the loading of each
counting and the loading of each count register. This register can be written into, no
read operation of this content is available.
Counters:

Each of the times has three pins associated with it. These are CLK (CLK) the gate
(GATE) and the output (OUT).

CLK:

This clock input pin provides 16-bit times with the signal to causes the times to
decrement maxm clock input is 2.6MHz. Note that the counters operate at the negative
edge (H1 to L0) of this clock input. If the signal on this pin is generated by a fixed
oscillator then the user has implemented a standard timer. If the input signal is a string
of randomly occurring pulses, then it is called implementation of a counter.

GATE:

The gate input pin is used to initiate or enable counting. The exact

effect of the gate signal depends on which of the six modes of

operation is chosen.

OUTPUT:

The output pin provides an output from the timer. It actual use depends on the mode of
operation of the timer. The counter can be read ―in the fly‖ without inhibiting gate pulse
or clock input.
Interfacing of ADC:

 The ADC0808, ADC0809 data acquisition component is a Monolithic CMOS

device with an 8-bit analog-to-digital converter, 8-channel multiplexer and
microprocessor compatible control logic.
 The 8-bit A/D converter uses successive approximations the conversion
technique.
 The converter features a high Impedance chopper stabilized comparator, a 256R
voltage divider with analog switch tree and a successive approximation register.

 IN0-IN7: Analog Input channels

 D0-D7: Data Lines
 A, B, C: Analog Channel select lines; A is LSB and C is MSB
 OE: Output enable signal
 ALE: Address Latch Enable
 EOC: End of Conversion signal
 Vref+/Vref-: Differential Reference voltage input
 Clock: External ADC clock input
Circuit Diagram (Interfacing of ADC0804 With 8051):

 The circuit initiates the ADC to convert a given analogue input, then accepts the
corresponding digital data and displays it on the LED array connected at P0.
 For example, if the analogue input voltage Vin is 5V then all LEDs will glow
indicating 11111111 in binary which is the equivalent of 255 in decimal.
 AT89s51 is the microcontroller used here. Data out pins (D0 to D7) of the
ADC0804 are connected to the port pins P1.0 to P1.7 respectively.
 LEDs D1 to D8 are connected to the port pins P0.0 to P0.7 respectively.
 Resistors R1 to R8 are current limiting resistors. In simple words P1 of the
microcontroller is the input port and P0 is the output port.
  Control signals for the ADC (INTR, WR, RD and CS) are available at port pins
P3.4 to P3.7 respectively. Resistor R9 and capacitor C1 are associated with the
internal clock circuitry of the ADC.
 Preset resistor R10 forms a voltage divider which can be used to apply a particular
input analogue voltage to the ADC.
 Push button S1, resistor R11 and capacitor C4 forms a debouncing reset
mechanism. Crystal X1 and capacitors C2, C3 are associated with the clock
circuitry of the microcontroller.

Interfacing of DAC:
 DAC0800 series are monolithic 8-bit high-speed current output digital-to-
analog converters (DAC) featuring typical settling times of 100 ns.
 The noise immune inputs will accept variety of logic levels.
 The performance and characteristics of the device are essentially
unchanged over the ±4.5V to ±18V power supply range and power
consumption at only 33 mW with ±5V supplies is independent of logic
input levels.

DAC 0808 Pin Description:
Pin diagram DAC 0808

DAC Interfacing with 8051:

 Microcontroller are used in wide variety of applications like for measuring and
control of physical quantity like temperature, pressure, speed, distance, etc.
 In these systems microcontroller generates output which is in digital form but the
controlling system requires analog signal as they don't accept digital data thus
making it necessary to use DAC which converts digital data into equivalent
analog voltage.
 In the figure shown, we use 8-bit DAC 0808. This IC converts digital data into
equivalent analog Current. Hence we require an I to V converter to convert this
current into equivalent voltage.

Ex 1: If data =00H [00000000], Vref= 10V

Therefore, V0= 0 Volts.

Ex 2: If data is 80H [10000000], Vref= 10V

Therefore, V0= 5 Volts.

Different Analog output voltages for different Digital signal are given as:

Data Output Voltage

00H 0V
80H 5V
FFH 10V

Interfacing of DAC0808/09 With 8051

 8279 - Keyboard/Display Controller

The Intel 8279 is a Keyboard/Display Controller is specially developed for interfacing

keyboard and display devices for the Intel 8085, 8086 and 8088 microprocessors. Its
important features are:

 Simultaneous keyboard and display operations.

 Scanned keyboard mode.
 Scanned sensor mode.
 8-character keyboard FIFO.
 Right or left entry 16-byte display RAM.
 Programmable scan timing.

I. Pin details of 8279

Figure 7 : Pin diagram of 8279

 A0: Selects data (0) or control/status (1) for reads and writes between micro and
8279.
BD: Output that blanks the displays.
CLK: Used internally for timing. Max is 3 MHz.
CN/ST: Control/strobe, connected to the control key on the keyboard.
CS: Chip select that enables programming, reading the keyboard, etc.
DB7-DB0: Consists of bidirectional pins that connect to data bus on micro.
IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.
OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant
nibble of display as shown in Figure 7.
RD(WR): Connects to micro's IORC or RD signal, reads data/status registers.
RESET: Connects to system RESET.
RL7-RL0: Return lines are inputs used to sense key depression in the keyboard
matrix.
Shift: Shift connects to Shift key on keyboard.
SL3-SL0: Scan line outputs scan both the keyboard and displays.
Block diagram of 8279:
The functional block diagram of 8279 is as shown in Figure 8.

Figure 8 :Block diagram of 8279

 The four major sections of 8279 are keyboard, scan, display and CPU interface.
Keyboard Section:

 The keyboard section consists of eight return lines RL0 - RL7 that can be used to
form the columns of a keyboard matrix.
 It has two additional input : shift and control/strobe. The keys are automatically
debounced.
 The two operating modes of keyboard section are 2-key lockout and N-key
rollover.
 In the 2-key lockout mode, if two keys are pressed simultaneously, only the first
key is recognized.
 In the N-key rollover mode simultaneous keys are recognized and their codes are
stored in FIFO.
 The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.
 The FIFO can store eight key codes in the scan keyboard mode. The status of
the shift key and control key are also stored along with key code. The 8279
generate an interrupt signal when there is an entry in FIFO. The format of key
code entry in FIFO for scan keyboard mode is,

 In sensor matrix mode the condition (i.e., open/close status) of 64 switches is

stored in FIFO RAM. If the condition of any of the switches changes then the
8279 asserts IRQ as high to interrupt the processor.

Display Section:

 The display section has eight output lines divided into two groups A0-A3 and B0-
B3.
 The output lines can be used either as a single group of eight lines or as two
groups of four lines, in conjunction with the scan lines for a multiplexed display.
 The output lines are connected to the anodes through driver transistor in case of
common cathode 7-segment LEDs.
 The cathodes are connected to scan lines through driver transistors.
 The display can be blanked by BD (low) line.
  The display section consists of 16 x 8 display RAM. The CPU can read from or
write into any location of the display RAM.

Scan Section:

 The scan section has a scan counter and four scan lines, SL0 to SL3.
 In decoded scan mode, the output of scan lines will be similar to a 2-to-4
decoder.
 In encoded scan mode, the output of scan lines will be binary count, and so an
external decoder should be used to convert the binary count to decoded output.
 The scan lines are common for keyboard and display.
 The scan lines are used to form the rows of a matrix keyboard and also
connected to digit drivers of a multiplexed display, to turn ON/OFF.

CPU Interface Section:

 The CPU interface section takes care of data transfer between 8279 and the
processor.
 This section has eight bidirectional data lines DB0 to DB7 for data transfer
between 8279 and CPU.
 It requires two internal address A =0 for selecting data buffer and A = 1 for
selecting control register of8279.
 The control signals WR (low), RD (low), CS (low) and A0 are used for read/write
to 8279.
 It has an interrupt request line IRQ, for interrupt driven data transfer with
processor.
 The 8279 require an internal clock frequency of 100 kHz. This can be obtained
by dividing the input clock by an internal prescaler.
 The RESET signal sets the 8279 in 16-character display with two -key lockout
keyboard modes.

Programming the 8279:

 The 8279 can be programmed to perform various functions through eight

command words.

II. Interfacing of 8279 with 8085

In a microprocessor b system, when keyboard and 7-segment LED display is interfaced

using ports or latches then the processor has to carry the following task.

 Keyboard scanning
  Key debouncing
 Key code generation
 Sending display code to LED
 Display refreshing

Interfacing 8279 with 8085 processor:

 A typical Hexa keyboard and 7-segment LED display interfacing circuit using
8279 is shown in figure 9.

Fig 9: keyboard and display interface with 8085 using 8279

 The circuit can be used in 8085 microprocessor system and consist of 16

numbers of hexa-keys and 6 numbers of 7-segment LEDs.

 The 7-segment LEDs can be used to display six digit alphanumeric character.

 The 8279 can be either memory mapped or I/O mapped in the system. In the
circuit shown is the 8279 is I/O mapped.

 The address line A0 of the system is used as A0 of 8279.

 The clock signal for 8279 is obtained by dividing the output clock signal of 8085
by a clock divider circuit.

 The chip select signal is obtained from the I/O address decoder of the 8085
system. The chip select signals for I/O mapped devices are generated by using a
3-to-8 decoder.

 The address lines A4, A5 and A6 are used as input to decoder. The address line
A7 and the control signal IO/M (low) are used as enable for decoder.

 The chip select signal IOCS-3 is used to select 8279.

 The I/O address of the internal devices of 8279 are shown in table.

 The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be
programmed in encoded scan. (Because in decoded scan, only 4 numbers of 7-
segment LEDs can be interfaced)

 In encoded scan the output of scan lines will be binary count. Therefore an
external, 3-to-8 decoder is used to decode the scan lines SL0, SL1 and SL2 of
8279 to produce eight scan lines S0 to S7.

 The decoded scan lines S0 and S1 are common for keyboard and display.

 The decoded scan lines S2 to S5 are used only for display and the decoded scan
lines S6 and S7 are not used in the system.

 Anode and Cathode drivers are provided to take care of the current requirement
of LEDs.

 The pnp transistors, BC 158 are used as driver transistors.

 The anode drivers are called segment drivers and cathode drivers are called digit
drivers.
 The 8279 output the display code for one digit through its output lines (OUT A0 to
OUT A3 and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.

 The display code is inverted by segment drivers and sent to segment bus.

 The scan code is decoded by the decoder and turns ON the corresponding digit
driver. Now one digit of the display character is displayed. After a small interval
(10 millisecond, typical), the display is turned OFF (i.e., display is blanked) and
the above process is repeated for next digit. Thus multiplexed display is
performed by 8279.

 The keyboard matrix is- formed using the return lines, RL0 to RL3 of 8279 as
columns and decoded scan lines S0 and S1 as rows.

 A hexa key is placed at the crossing point of each row and column. A key press
will short the row and column. Normally the column and row line will be high.

 During scanning the 8279 will output binary count on SL0 to SL3, which is
decoded by decoder to make a row as zero. When a row is zero the 8279 reads
the columns. If there is a key press then the corresponding column will be zero.

 If 8279 detects a key press then it wait for debounce time and again read the
columns to generate key code.

 In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid
key press. The keycode consist of the binary value of the column and row in
which the key is found and the status of shift and control key.

 After a scan time, the next row is made zero and the above process is repeated
and so on. Thus 8279 continuously scan the keyboard.